JP2004153131A - Method for manufacturing semiconductor device - Google Patents

Abstract

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing an output difference caused by divided exposure.
The method includes an in-line process in which a process of applying a resist, a process of exposing the resist, and a process of developing the exposed resist are integrated. A method of manufacturing a semiconductor device for forming a desired pattern by the in-line process, wherein the exposing step performs the exposing while sequentially exchanging a plurality of reticles, the pattern from the plurality of reticles obtained by the exposing This is a division exposure step of forming the desired pattern by joining together.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device.
[0002]
[Prior art]
In a wafer process in a semiconductor device manufacturing process, a semiconductor element is formed on a substrate using photolithography. In the photolithography process, a chip pattern is formed by transferring and exposing a mask pattern (also referred to as a reticle pattern) onto a wafer. Transfer exposure includes projection exposure and projection exposure. In particular, reduction projection exposure (also referred to as stepper exposure), which is one of projection exposure, can form a pattern with higher resolution than other exposure methods. , Are suitably used for highly integrated semiconductor devices.
[0003]
As an example, FIG. 4 schematically shows a main part of a reduction projection exposure apparatus disclosed in Patent Document 1. This reduction projection exposure apparatus aligns the reticle 122 with an XY stage 128 on which the wafer 127 is fixed, a reduction projection lens 123 for reducing and projecting a reticle pattern formed on the reticle 122 onto the wafer 127. An alignment optical system 121, an alignment optical system 125 for aligning the position of the wafer 127, and a laser interferometer 124 for detecting the amount of movement of the XY stage 128 in the XY directions are provided.
[0004]
In the above-described reduction projection exposure apparatus, the pattern is formed on the wafer 127 by the reduction projection lens 123 using the reticle pattern formed on the reticle 122, and the XY stage 128 is moved step by step for each shot to change the pattern. The entire wafer 127 is exposed by step and repeat printing. According to this stepper exposure, the limit resolution can be set to, for example, 1.0 μm or less. In this case, a field size that can be transferred by one projection exposure (hereinafter, referred to as an exposure field size) is about φ40 mm.
[0005]
Incidentally, in the case of the above-described reduced projection exposure apparatus, for a semiconductor device having a chip size exceeding the exposure field size, a target chip pattern cannot be formed on a wafer by one projection exposure. In view of this, divisional exposure for dividing and exposing a chip pattern is performed (see Patent Document 1). Hereinafter, the divided exposure will be specifically described.
[0006]
FIG. 5 shows an example of a reticle used for divided exposure, and FIG. 6 shows an example of a chip pattern formed on a wafer using the reticle. On reticle 100 shown in FIG. 5, three divided patterns of reticle pattern 100a corresponding to circuit pattern A, reticle pattern 100b corresponding to circuit pattern B, and reticle pattern 100c corresponding to circuit pattern C are formed. The circuit patterns A to C are obtained by dividing one circuit pattern. The reticle patterns 100a to 100c are connected and exposed on a wafer to form a chip pattern 200 in which circuit patterns A to C are connected as shown in FIG.
[0007]
In the example shown in FIG. 5, three reticle patterns 100a, 100b, and 100c are formed on one reticle 100. However, in divided exposure in the manufacture of a semiconductor device such as a solid-state imaging device, the reticle patterns 100a, Three reticles in which 100b and 100c are separately formed are used. For example, when forming a pattern of a color filter layer constituting a large-area solid-state imaging device in which one chip exceeds an exposure field of a reduction projection exposure apparatus, divided exposure is generally performed using a plurality of reticles. .
[0008]
In the process of manufacturing a semiconductor device such as a solid-state image sensor, a series of processes such as resist coating, pre-baking, exposure, development, and post-baking are usually performed for each lot with n (for example, 25) wafers as one lot. Done. FIG. 7 shows a flow of the series of processes.
[0009]
Referring to FIG. 7, with n wafers as one lot, three steps of a coating / pre-bake step, an exposure (division exposure) step, and a development / post-bake step are sequentially performed for each lot. First, in a coating / prebaking step, a resist is applied to the first wafer and prebaking is performed. Next, a resist is applied to the second wafer and prebaked. Similar processing is sequentially performed on the third to n-th wafers. Thus, resist application and pre-bake are performed on all wafers. After that, the process moves to the next exposure step.
[0010]
In the exposure step, divided exposure using m reticles is performed in a reduction projection exposure apparatus as shown in FIG. First, exposure is performed using the first reticle while sequentially changing wafers. When the exposure using the first reticle is performed on all the wafers, the reticle is replaced with a second reticle, and the exposure is performed while the wafers are sequentially replaced. Exposure is performed up to the m-th reticle in the same procedure. In this manner, the divided exposure using m reticles is performed on all the wafers. Thereafter, the process proceeds to the next step of development / post-bake.
[0011]
In the development / post-baking process, development and post-baking are performed on the first wafer. Next, development and post-baking are performed on the second wafer. Similar processing is sequentially performed on the third to n-th wafers. Thus, development and post-baking are performed on all the wafers.
[0012]
[Patent Document 1]
JP-A-5-6849
[Problems to be solved by the invention]
However, in the case where a semiconductor device such as a solid-state imaging device is manufactured by applying the above-described divisional exposure, it is clear from the analysis so far that the following problem occurs when the processing shown in FIG. 7 is performed. Became.
[0014]
In the processing step shown in FIG.
(1) Elapsed time from application of resist to completion of exposure (reservation time)
(2) Elapsed time from exposure to completion of development (baking time)
Are very long and their time varies between exposure shots at each reticle. For this reason, depending on the type of the resist, the size and shape of the transfer pattern may differ between the exposure shots due to the change over time in the resist characteristics, or the residue may differ in appearance.
[0015]
For example, in a pigment-dispersed resist used for forming a color filter layer constituting a solid-state imaging device, if the difference between the pull-out time and the baking time between exposure shots is significantly different, the pattern dimensions after development may vary. Or the manner in which the pigment residue after development is different. Also, in the case of a chemically amplified resist (an acid-generating type resist in which an acid is generated in a portion irradiated with light and the portion remains as a pattern), the size and shape of the developed pattern vary.
[0016]
As described above, if a difference occurs in the dimension, shape, and residue of the pattern between exposure shots, the difference may affect the output characteristics of the semiconductor device.
[0017]
Further, the difference between the above-mentioned pulling time and baking time differs between wafers. For example, the lay-out time relating to the exposure shot with the first reticle in the first wafer is included in the time required for application / pre-bake to all the wafers. The delay time for the exposure shot on the reticle does not include the time required for such coating / prebaking. In addition, the baking time for the exposure shot with the first reticle in the last wafer to be loaded includes the time required for development / post-baking performed on the wafers loaded so far, The baking time for the exposure shot on the first reticle in the first wafer to be loaded does not include the time required for such development / post-bake. In this case, the effect on the output characteristics of the semiconductor device due to the difference in the pattern size or shape between the exposure shots differs between wafers. As a result, some wafers with low sensitivity appear in a wafer group of one lot.
[0018]
Next, the effect of the difference in pattern size and shape between exposure shots on the output characteristics of the semiconductor device will be specifically described using a solid-state imaging device as an example.
[0019]
FIG. 8 is a schematic diagram illustrating a divided area when a pixel portion of a solid-state imaging device is divided into two and exposed. The pixel portion 300 shown in FIG. 8 includes a plurality of pixels having the same structure arranged in a matrix, has a joint 300c near the center, and has two divided regions 300a and 300b with the joint 300c as a boundary. Having. The divided areas 300a and 300b are areas formed by exposure shots with different reticles, and have the above-described pattern dimension difference.
[0020]
In the above-described pixel portion 300, a difference occurs in the output (electric signal) between the divided regions 300a and 300b. For example, when a certain amount of light is incident on the entire pixel unit 300, as shown in FIG. 9, the output of the divided region 300a is low and the output of the divided region 300b is high at the joint 300c. For this reason, in the captured image of the entire pixel portion 300, a streak that can be visually observed occurs at a position corresponding to the joint 300c.
[0021]
The output difference is caused by, for example, a difference in the size or shape of the color filter or a difference in the size of the gap between adjacent color filters between the divided regions 300a and 300b. FIG. 10 schematically shows the influence of the pattern size difference in the color filter layer.
[0022]
In the example illustrated in FIG. 10, the pixel unit 300 includes a wiring layer / interlayer insulating film 303 and a flat surface on a semiconductor substrate 301 on which a photoelectric conversion unit 302 is formed at a position corresponding to each pixel on the front surface side (main surface side). The structure has a structure in which a passivation layer 304, a color filter layer 305, and a flattening layer 306 are sequentially stacked, and a microlens 307 is formed on the flattening layer 306 at a position corresponding to each pixel. The wiring layer / interlayer insulating film 303 usually includes a plurality of wiring layers and a plurality of interlayer insulating films provided for each of these wiring layers, but their configuration is omitted in FIG. Further, a semiconductor element (for example, CMOS) for converting charges generated by the photoelectric conversion unit 302 according to the amount of incident light into an electric signal and transmitting the electric signal is also omitted.
[0023]
The photoelectric conversion unit 302, the wiring layer / interlayer insulating film 303, the color filter layer 305, and the microlens 307 are all formed using a photolithography process, and depending on the type of resist used, the divided region 300a , And 300b, the pattern size difference described above occurs. Here, the effect of the pattern size difference in the color filter layer 305 will be described.
[0024]
In the formation of the color filter layer 305, a photoresist layer in which a predetermined pigment is dispersed is formed on the flattening layer 304, and the photoresist layer is exposed to form a color filter corresponding to a pixel (photolithography step). . By performing this process for each color (R, G, B), a color filter layer 305 in which filters of each color (R, G, B) are arranged corresponding to pixels is obtained.
[0025]
In the above photolithography process, when the division exposure is performed, the size and the shape of the color filter are generated between the divided regions 300a and 300b due to the pattern dimension difference described above. For example, when the pattern size in the divided region 300a is smaller than the pattern size in the divided region 300b, the size of the color filter is smaller on the divided region 300a side than on the divided region 300b side. As a result, a difference occurs in the size of the gap between adjacent color filters between the divided areas 300a and 300b. In the example of FIG. 10, the size of the gap between the adjacent color filters is larger on the side of the divided region 300a.
[0026]
The incident light from the gap between the color filters is reflected by the flattening layer 304, the wiring layer / interlayer insulating film 303, etc., and enters the photoelectric conversion unit 302. When the size of the gap changes, the amount of incident light from the gap changes, and as a result, the amount of incident light on the photoelectric conversion unit 302 also changes. Therefore, when a difference occurs in the size of the gap between the adjacent color filters between the divided regions 300a and 300b, the difference appears as a difference in the amount of light incident on the photoelectric conversion unit 302, and the difference appears from the pixel unit 300. The output produces an output difference as shown in FIG.
[0027]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device which can solve the above-mentioned problem and can suppress an output difference caused by divided exposure.
[0028]
[Means for Solving the Problems]
In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes three steps: a step of applying a resist, a step of exposing the resist, and a step of developing the exposed resist. A method of manufacturing a semiconductor device forming a desired pattern by the in-line step, comprising:
The exposing step is a division exposure step of performing exposure while sequentially exchanging a plurality of reticles for each sequentially input wafer, and joining the patterns from the plurality of reticles obtained by the exposure to form the desired pattern. It is characterized by being.
[0029]
According to the invention described above, since the in-line process is performed, the loaded wafer is exposed immediately after the application of the resist, and is developed immediately after the exposure. Also, in the divided exposure step, exposure on each reticle is performed continuously. In this case, the time required from the start of resist coating to the end of development per wafer is greatly reduced as compared with the processing time in the conventional method shown in FIG. The effect on the output characteristics of the semiconductor device due to the difference between the exposure shots can be minimized. Further, the influence on the output characteristics of the semiconductor device due to the difference between the wafers in the withdrawal time and the baking time generated during the divided exposure can be minimized. Therefore, even when a pigment-dispersed resist or a chemically amplified resist is used, there is no difference in the output characteristics of the conventional semiconductor device.
[0030]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of the present invention will be described with reference to the drawings.
[0031]
FIG. 1 is a diagram showing an inline process according to an embodiment of the present invention, and FIG. 2 is a schematic configuration diagram of an inline system in which the inline process is performed.
[0032]
First, the configuration of the inline system will be described with reference to FIG. The in-line system, the resist coating unit 1, the bake unit 2, the developing unit 3 and the exposure unit 4 is in-line system, a wafer wafer W ₁ to _W-n of n sheets (e.g. 25 sheets) is stored It has a transport mechanism (not shown) in which wafers are sequentially loaded into the system from the carrier 5 and processing is performed in each unit.
[0033]
The resist coating unit 1, the baking unit 2, and the developing unit 3 are well-known units used in a wafer process, and perform resist coating, baking processing, and developing processing on a wafer loaded from the wafer carrier 5, respectively. . The exposure unit 4 includes an exposure device 41 having the same configuration as the reduction projection exposure device shown in FIG. 4 and a reticle changer in which _m reticles r _{1 to} rm for forming a desired pattern by divided exposure are stored. The reticle is sequentially supplied from the reticle changer 42 to the exposure device 41. The wafer loaded from the wafer carrier 5 is fixed on an XY stage (128 in FIG. 4) of the exposure apparatus 41 via a wafer chuck (not shown).
[0034]
The loading of the wafer from the wafer carrier 5, the delivery of the wafer between the resist coating unit 1, the baking unit 2, the developing unit 3 and the exposure unit 4, and the supply of the reticle from the reticle changer 42 to the exposure unit 4 Is also automatically controlled by a control unit (not shown).
[0035]
Next, a series of processes of the inline process of the present embodiment will be described with reference to FIG.
[0036]
First, the wafer W ₁ of the first sheet is introduced into a line system is taken out from the wafer carrier 5. The inserted wafers W ₁ is the resist in the resist coating unit 1 is applied (step S1), and after being subjected to pre-baking at the baking unit 2 (step S2), and the exposure unit 4 exposure device 41 on the stage Supplied to
[0037]
In the exposure unit 4, the reticle r ₁ is set in the exposure apparatus 41 is taken out from the reticle changer 42, to the wafer W ₁ supplied onto the stage, the exposure process line using a reticle r ₁ which is the set Be done. Then, the reticle r ₂ instead of the reticle r ₁ is set in the exposure apparatus 41, to the wafer W ₁ supplied onto the stage, exposure using a reticle r _2, which is the set is performed. In a similar procedure, the reticle r ₃ ~r _m is sequentially set to the exposure apparatus 41, exposure processing on the wafer W ₁ supplied onto the stage is performed (step S3).
[0038]
When exposure processing using all of the reticle r ₁ ~r _m as described above is performed, then the wafer W ₁ is transferred from the exposure unit 4 to the developing unit 3, developing process line at the developing unit 3 (Step S4). Wafer W ₁ to the development processing is performed, after the post-baking at bake unit 2 is subjected (step S5), and are unloaded from the line system is stored in the wafer carrier 5.
[0039]
The remaining wafers W _{2 to} W _n are also sequentially loaded into the in-line system from the wafer carrier 5 and, similarly to the case of the wafer W ₁ described above, resist coating (step S1), pre-bake (step S2), and division exposure ( Step S3), development (step S4), and post-bake (step S5) are sequentially performed.
[0040]
According to the above-described in-line process, resist coating, pre-baking, exposure (division exposure), development, and post-baking are sequentially performed on one wafer. Moreover, in the exposure step, exposure is performed on one wafer while sequentially replacing the _m reticles r _{1 to} rm. For this reason, the time required for the in-line process for one wafer (the time from the start of resist application to the end of post-bake) is greatly reduced as compared with the processing time in the conventional method shown in FIG. Is done.
[0041]
Further, by appropriately controlling the timing of the delivery of a wafer between the timing and the units of the wafer to the in-line system is turned on, the time required for the in-line process is the same between the wafer W ₁ to _W-n. That is, the time required for the in-line process in each of the wafers W _{1 to} W _n is:
T1f-T1s = T2f-T2s =... = Tnf-Tns
It becomes. Here, T1s, T2s,. . . , Tns are the wafers W ₁ , W ₂ ,. . . , A resist coating start time of _{W n,} T1f, T2f ,. . . , Tnf are wafers W ₁ , W ₂ ,. . . Is a post-baking end time of the _{W n.} In this case, it is possible to minimize the influence on the output characteristics of the semiconductor device due to the difference between the wafers in the withdrawal time and the bake time generated during the divided exposure.
[0042]
Further, at least the three units of the resist coating unit 1, the developing unit 3 and the exposure unit 4 can perform processing on different wafers. For example, while the wafer W ₁ by the developing unit 3 is developed, is a wafer W ₂ is exposed at the exposure unit 4, a resist coating unit 1 with the wafer W ₃ is applied, it is possible to parallel processing such as . As a result, the time required for the entire manufacturing process is also reduced. In the example shown in FIG. 1, the processing of the divided exposure on each wafer partially overlaps in time, but this is because the time axis of the processing on each wafer is reduced and shown. Since each wafer is exposed one by one, the processing does not overlap in time.
[0043]
Further, according to the in-line process described above, it is possible to minimize the difference in the holding time period and tempering holding time period between exposure shot (during the exposure process by the reticle r ₁ ~r _m). FIG. 3 shows a difference between a pull-up time and a baking time between exposure shots in the in-line process shown in FIG.
[0044]
In FIG. 3, the holding times Ta1, Ta2,. . . , Tam is an elapsed time from the respective resist coating start to the exposure end for each reticle _r 1 ~r _m,
Ta1 <Ta2 <,. . . , <Tam
In a relationship. Further, the baking times Tb1, Tb2,. . . , Respectively Tbm, a time elapsed until the termination of development from exposure end of each reticle _r 1 ~r _m,
Tb1>Tb2>,. . . ,> Tbm
In a relationship.
[0045]
When exposure is performed while sequentially replacing the _m reticles r _{1 to} rm for _one wafer, the difference between the shortest storage time Ta1 and the longest storage time Tam is basically (m− 1) It is the time required for exposure of a reticle. Also, the difference between the shortest baking time Tbm and the longest baking time Tb1 is basically the time required for (m-1) reticle exposures. These differences are much smaller than in the conventional method shown in FIG. For this reason, even when a pigment-dispersed resist is used, there is no difference between exposure shots that causes a problem in the dimensions and shape of the pattern and the manner in which the residue appears. Also, when a chemically amplified resist is used, there is no difference between exposure shots that causes a problem in the dimensions and shape of the pattern.
[0046]
The method of manufacturing a semiconductor device according to the present embodiment described above is particularly effective for a solid-state imaging device. When a solid-state imaging device is manufactured by using the method of manufacturing a semiconductor device of the present invention, for example, in the configuration shown in FIG. 10, the size of each color filter constituting the color filter layer 305 between the divided regions 300a and 300b And the difference in the shape and the gap, and the difference in the appearance of the residue in the color filters can be minimized. The same applies to an active element (for example, a CMOS transistor) for transferring an electric charge according to the amount of incident light from another layer (the layer on which the microlens 307 is formed, the photoelectric conversion unit 302) on which the divided exposure is performed. This is also true for a layer where is formed. Therefore, according to the method of manufacturing a semiconductor device of the present invention, the output difference as shown in FIG. 9 can be substantially eliminated, and the problem of streaks at a joint portion in a captured image can be solved.
[0047]
(Other embodiments)
It is desirable that the holding times Ta1 to Tam and the baking times Tb1 to Tbm shown in FIG. Here, a method for shortening the withdrawal time and the baking time will be described.
[0048]
In general, when performing divided exposure using a plurality of reticles, it is common to perform alignment of the reticle with respect to the base (hereinafter, referred to as alignment) using an alignment mark provided on the base for each exposure shot. is there. This alignment is performed using the alignment optical systems 121 and 125 in, for example, the reduction projection exposure apparatus shown in FIG. As described above, when the alignment is performed for each exposure shot, the pull-up time and the baking time are lengthened by the time required for the alignment.
[0049]
Therefore, in the present embodiment, the alignment information in the exposure shot performed earlier is used at least once as the alignment information in the exposure shot performed thereafter. For example, in the in-line process shown in FIG. 1, alignment is performed when performing “reticle r ₁ exposure”, and alignment information obtained by this alignment is used in “reticle r ₂ exposure”. In this case, the pull-out times Ta1 to Tam and the baking times Tb1 to Tbm shown in FIG. 3 are reduced by the time of one alignment. When used in each alignment information obtained in the "reticle r ₁ exposure" of "reticle r ₂ exposure" - "reticle r _m exposure" time placed pulling shown in FIG. 3 Ta1～Tam and tempering holding time period Tb1 ＴTbm is reduced by the time corresponding to the alignment (m−1) times.
[0050]
As described above, the embodiments of the present invention have been described with reference to the drawings. However, the present invention is not limited to the description range and the range of the drawings referred to, and may be appropriately changed without departing from the spirit of the present invention. Can be added. Hereinafter, examples of embodiments of the present invention will be listed.
[0051]
[Embodiment 1] An in-line process in which three steps of a step of applying a resist, a step of exposing the resist, and a step of developing the exposed resist are integrated. A method of manufacturing a semiconductor device for forming a pattern, wherein the exposing step performs exposure while sequentially exchanging a plurality of reticles for each wafer to be sequentially input, and a pattern from the plurality of reticles obtained by the exposure. A method of manufacturing a semiconductor device, comprising forming the desired pattern by joining together.
[0052]
[Embodiment 2] The method of manufacturing a semiconductor device according to embodiment 1, wherein the time from the start of application of the resist to the end of the exposure is substantially equal in each of the wafers sequentially charged.
[0053]
[Embodiment 3] The method of manufacturing a semiconductor device according to Embodiment 1, wherein the time required from the end of the exposure to the end of the development is substantially equal in each of the sequentially input wafers.
[0054]
[Embodiment 4] The method of manufacturing a semiconductor device according to embodiment 1, wherein the time required from the start of the application of the resist to the end of the development is the same for each of the wafers sequentially charged.
[0055]
[Embodiment 5] The method of manufacturing a semiconductor device according to any one of Embodiments 2 to 4, wherein the required time is within a predetermined time. Here, within the predetermined time, a difference (such as a difference in the output of the semiconductor device) between the exposure shots due to a change in resist characteristics with time, such as a difference in pattern size, shape, residue, or the like, does not occur. Time range.
[0056]
[Embodiment 6] The first to fifth embodiments are characterized in that the division exposure step includes a step of using alignment information in the exposure performed earlier as alignment information in the subsequent exposure at least once. The method for manufacturing a semiconductor device according to any one of the above.
[0057]
Embodiment 7 The method for manufacturing a semiconductor device according to any one of Embodiments 1 to 6, wherein the resist is a pigment-dispersed resist.
[0058]
Embodiment 8 The method of manufacturing a semiconductor device according to any one of Embodiments 1 to 6, wherein the resist is a chemically amplified resist.
[0059]
【The invention's effect】
As described above, according to the present invention, the characteristic difference due to the divided exposure can be minimized, so that it is possible to provide a semiconductor device having more stable operation characteristics than the conventional one. In particular, when the present invention is applied to a solid-state imaging device, a problem of a streak occurring at a joint of divided exposures of a captured image can be solved, so that a high-quality image can be provided.
[0060]
In addition, a semiconductor device with stable operation characteristics can be provided for the whole lot.
[Brief description of the drawings]
FIG. 1 is a view showing a procedure of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a schematic configuration of an in-line system to which the method of manufacturing the semiconductor device shown in FIG. 1 is applied;
FIG. 3 is a diagram for explaining a relationship between a pulling-in time and a baking time in the method of manufacturing the semiconductor device shown in FIG. 1;
FIG. 4 is a view for explaining a conventional method of manufacturing a semiconductor device.
FIG. 5 is a perspective view of an essential part showing an example of a reduction projection exposure apparatus.
FIG. 6 is a schematic diagram illustrating an example of a reticle.
FIG. 7 is a schematic diagram illustrating an example of a chip pattern.
FIG. 8 is a schematic diagram illustrating a divided region when a pixel portion of a solid-state imaging device is divided into two and exposed.
FIG. 9 is a diagram illustrating an output of a solid-state imaging device formed by a conventional method of manufacturing a semiconductor device.
FIG. 10 is a cross-sectional view of a solid-state imaging device formed by a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
Reference Signs List 100 reticle 100 a to 100 c reticle pattern 121 alignment optical system 122 reticle 123 reduction projection lens 124 laser interferometer 125 alignment optical system 127 wafer 128 XY stage 200 chip pattern 300 pixel portion 300 a, 300 b division region 300 c joint 301 semiconductor substrate 302 photoelectric conversion portion 303 Wiring layer / interlayer insulating film 304, 306 Flattening layer 305 Color filter layer 307 Micro lens

Claims (1)

A semiconductor for forming a desired pattern by the in-line process including three steps of applying a resist, exposing the resist, and developing the exposed resist; A method of manufacturing a device, comprising:
The exposing step is an exposing step in which the exposing is performed while sequentially exchanging a plurality of reticles for each wafer to be sequentially input, and the desired patterns are formed by joining patterns from the plurality of reticles obtained by the exposing. A method for manufacturing a semiconductor device.

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