JP2004164757A - Optical disk header signal detection circuit - Google Patents

Abstract

In a circuit for binarizing an input signal at an upper slice level and a lower slice level, a circuit for generating a lower slice level lower than a reference voltage is reduced, and an input asymmetric with respect to the reference voltage is performed. Is also intended to be normally binarized.
A slice level generating means for generating an upper slice level, a first comparator for binarizing the upper slice level, an upper peak voltage detecting means for detecting an upper peak voltage of an input signal, and an input. A lower peak voltage detecting means for detecting a lower peak voltage of the signal; and a second comparator for binarizing an input signal shifted below the reference voltage at a lower slice level. The lower slice level generated from the equation is generated to enable binarization.
[Selection] Fig. 2

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an optical disk header signal detection circuit used for detecting a header of a DVD-RAM.
[0002]
[Prior art]
A conventional optical disk header signal detection circuit will be described with reference to FIGS. Here, FIG. 7 is a block diagram showing the configuration of a conventional optical disk header signal detection circuit, and FIG. 8 is a timing diagram showing the timing and voltage relationship of the conventional optical disk header signal detection circuit.
[0003]
As shown in FIG. 7, a conventional optical disk header signal detection circuit includes a comparator 31 for binarizing an input signal shifted above a reference voltage by an upper slice level, and a comparator 31 for lowering the reference signal by a lower slice level. A comparator 32 for binarizing the shifted input signal; a slice level generating means 33 for generating an upper slice level from the outputs of the comparators 31 and 32; A voltage follower 34 feeds back to 31 and drives an inverting amplifier 35, and an inverting amplifier 35 inverts a voltage output from the voltage follower 34 with respect to a reference voltage and feeds back to the comparator 32.
[0004]
The operation of the optical disk header signal detection circuit configured as described above will be described below. First, when an optical disk header signal shifted above the reference voltage as an input signal is input to the comparator 31, the signal is binarized by the upper slice level generated at that time. The binarized signal is input to the slice level generating means 33, and a new upper slice level is generated. The upper slice level output from the slice level generator 33 is fed back to the comparator 31 via the voltage follower 34, and is also input to the inverting amplifier 35 to generate the lower slice level symmetrically with respect to the reference voltage. Then, it is fed back to the comparator 32. By the above operation, the optical disk header signal detection signal as shown in FIG.
[0005]
The slice level generating means 33 has a duty feedback. When the duty of the binarized signal is larger than 50%, the slice level is detected to be higher than an appropriate voltage and the slice level is reduced. . When the duty of the binarized signal is smaller than 50%, the operation reverse to the above is performed to increase the slice level. The slice level is automatically controlled so that the duty of the binarized signal becomes 50% by repeating this operation.
[0006]
However, in the conventional optical disk header signal detection circuit, after the slice level generating means 33 generates the upper slice level, the lower slice level symmetrical to the reference voltage is generated. For this reason, the output of the slice level generation means 33 is impedance-converted to lower the impedance and is fed back to the comparator 31 and the voltage follower 34 for driving the inverting amplifier 35, and the voltage output from the voltage follower 34 is compared with the reference voltage. An inverting amplifier 35 for inverting and feeding back to the comparator 32 is required, and there is a problem that a circuit area increases.
[0007]
There is also a problem that the shift amount of the input signal on the upper side and the lower side with respect to the reference voltage must be equal.
[0008]
[Patent Document 1]
JP, 2002-170242, A
[Problems to be solved by the invention]
In view of the above problems, an optical disk header signal detection circuit according to the present invention includes two pairs of differential pairs connected in parallel and a second comparator having a binarizing means, and includes a reference voltage along with an input signal and an upper slice level. Is input to the second comparator. With this configuration, the circuit area for arranging the voltage follower and the inverting amplifier required for generating the lower slice level can be reduced, and the conditional expression for inverting the output of the second comparator can be used. The purpose is to generate a side slice level.
[0010]
However, with the above configuration alone, when an asymmetric input is made to the reference voltage, an event occurs that binarization cannot be performed normally. In order to avoid this event, the optical disk header signal detection circuit of the present invention includes an upper peak voltage detector, a lower peak voltage detector, or a reference voltage generator together with the second comparator, so that the reference voltage can be adjusted. Instead, a first reference voltage set to a voltage higher by a predetermined amount than the upper peak voltage, a lower peak voltage or the reference voltage, and a second reference voltage set to a voltage lower by a predetermined amount than the reference voltage from the respective means. The lower slice level is generated by using a conditional expression that is input to the second comparator and inverts the output of the second comparator set in each configuration, and the input is normally performed even when the input is asymmetric with respect to the reference voltage. An object is to perform binarization.
[0011]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, an optical disk header signal detection circuit according to claim 1 of the present invention provides a slice level generation means for generating an upper slice level for binarizing an input signal shifted upward with respect to a reference voltage. A first comparator that binarizes an input signal shifted above the reference voltage by the upper slice level, and a second comparator that binarizes an input signal shifted below the reference voltage by a lower slice level. And (Comparative voltage of input signal) = (reference voltage) − {(upper slice level) − (reference voltage)} generated from a conditional expression for inverting the output of the second comparator. The lower slice level for binarizing an input signal shifted downward with respect to the reference voltage is generated.
[0012]
An optical disk header section signal detection circuit according to a second aspect of the present invention includes: a slice level generation unit configured to generate an upper slice level for binarizing an input signal shifted upward with respect to a reference voltage; A first comparator for binarizing an input signal shifted to an upper side with the upper slice level, a second comparator for binarizing an input signal shifted to a lower side than the reference voltage with a lower slice level, An upper peak voltage detecting means for detecting an upper peak voltage of the signal, and a lower peak voltage detecting means for detecting a lower peak voltage of the input signal, which are generated from a conditional expression for inverting an output of the second comparator. In addition, from (input signal voltage) = (lower peak voltage) + {(upper peak voltage) − (upper slice level)}, the reference voltage And so as to generate the lower slice level for binarizing the input signal shifted to the lower side.
[0013]
The optical disk header signal detection circuit according to claim 3 of the present invention further comprises: a slice level generating means for generating an upper slice level for binarizing an input signal shifted upward with respect to a reference voltage; A first comparator for binarizing an input signal shifted to an upper side with the upper slice level, a second comparator for binarizing an input signal shifted to a lower side than the reference voltage with a lower slice level, A second reference voltage generating means for outputting a first reference voltage set to a voltage higher than the reference voltage by a predetermined amount and a second reference voltage set to a voltage lower than the reference voltage by a predetermined amount; (Voltage of input signal) = (second reference voltage) − ｛(upper slice level) − (first reference voltage) generated from the conditional expression for inverting the output of the comparator More}, and so as to generate the lower slice level for binarizing the input signal shifted to the lower side with respect to the reference voltage.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of an optical disk header section signal detection circuit according to the present invention will be described with reference to FIGS.
[0015]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of an optical disc header signal detection circuit according to Embodiment 1 of the present invention, and FIG. 5 is a block diagram showing a configuration example of a second comparator 2 of the present invention.
[0016]
As shown in FIG. 1, the optical disk header signal detection circuit according to the first embodiment of the present invention includes a first comparator 1 for binarizing an input signal shifted upward from a reference voltage by an upper slice level, and a later-described comparator. The second comparator 2, which binarizes the input signal shifted below the reference voltage by the lower slice level generated from the conditional expression for inverting the output of the second comparator, the first comparator 1, and the second comparator And a slice level generating means 3 for generating an upper slice level from the output of the second comparator 2.
[0017]
FIG. 5 is a block diagram showing a configuration example of the second comparator 2 of the present invention. The positive input transistors 7 and 11, the negative input transistors 8 and 10, the constant current sources 9 and 12, and the binarizing means 13 The sources of the positive input transistor 7 and the negative input transistor 8 are connected and connected to a constant current source 9. Similarly, the sources of the positive input transistor 11 and the negative input transistor 10 are also connected and connected to a constant current source. 12 is connected. The drains of the positive input transistors 7 and 11 and the drains of the negative input transistors 8 and 10 are connected to each other and connected to the binarizing means 13.
[0018]
The operation of the optical disk header signal detection circuit configured as described above will be described below. First, when an optical disk header signal shifted above the reference voltage as an input signal is input to the first comparator 1, it is binarized by the upper slice level generated at that time. The binarized signal is input to the slice level generating means 3, and a new upper slice level is generated. This upper slice level, which is the output of the slice level generating means 3, is fed back to the first comparator 1 to binarize the input signal shifted upward and binarizes the input signal to the second comparator 2 as a differential input with a reference voltage. Is also entered.
Here, the condition that the output of the second comparator 2 is inverted is when the input potential differences of the respective differential input signals are equal in absolute value, and the differential output current at this time is also equal to the positive and negative sides. The output of the second comparator 2 is inverted.
[0019]
Under such a configuration, the condition that the output of the second comparator 2 is inverted is as follows.
(Voltage of input signal) + (upper slice level) = 2 × (reference voltage)
Rewriting the above formula,
(Input signal voltage) = (reference voltage) − {(upper slice level) − (reference voltage)}
And the lower slice level is symmetrical to the upper slice level with respect to the reference voltage.
[0020]
As described above, binarization can be performed on an input signal shifted below the reference voltage, so that a circuit for generating a lower slice level is not required, and the circuit area can be reduced. .
[0021]
The operation in which the outputs of the first comparator 1 and the second comparator 2 converge to the slice level optimum value by the slice level generation means 3 is the same as in the conventional example.
[0022]
(Embodiment 2)
FIG. 2 is a block diagram showing a configuration of an optical disk header section signal detection circuit according to Embodiment 2 of the present invention. FIG. 4 is a timing chart of the optical disk header section signal detection circuit according to Embodiment 2 of the present invention and definitions of respective voltages. FIG.
[0023]
As shown in FIG. 2, an optical disc header signal detection circuit according to the second embodiment of the present invention includes a first comparator 1 for binarizing an input signal shifted upward from a reference voltage by an upper slice level, and a later-described comparator. The second comparator 2, which binarizes the input signal shifted below the reference voltage by the lower slice level generated from the conditional expression for inverting the output of the second comparator, the first comparator 1, and the second comparator 2, a slice level generating means 3 for generating an upper slice level from an output of the comparator 2, an upper peak voltage detecting means 4 for detecting an upper peak voltage of the input signal, and a lower peak detecting means for detecting a lower peak voltage of the input signal. It comprises voltage detecting means 5.
[0024]
The difference between the present embodiment and the first embodiment is that two reference voltage inputs are output from the upper peak voltage detecting means 4 and output from the lower peak voltage detecting means 5 and are different from each other. The conditions for inverting the output of the second comparator 2 are different, but the other configurations and operations are the same as in the first embodiment.
[0025]
Under such a configuration, the condition that the output of the second comparator 2 is inverted is expressed by using the voltage shown in FIG.
(Input signal voltage) + (upper slice level) = (upper peak voltage) + (lower peak voltage)
Rewriting the above formula,
(Voltage of input signal) = (lower peak voltage) + {(upper peak voltage) − (upper slice level)}
It becomes.
[0026]
In this way, the lower slice level is higher than the lower peak voltage by the potential difference from the upper peak voltage to the upper slide level, and is optimal based on the upper and lower peak voltages even if the input is asymmetric with respect to the reference voltage. Since the appropriate slice level can be determined, binarization can be performed normally even when the upper shift amount and the lower shift amount of the input signal are not the same but are asymmetric.
(Embodiment 3)
FIG. 3 is a block diagram showing a configuration of an optical disk header section signal detection circuit according to Embodiment 3 of the present invention.
[0027]
As shown in FIG. 3, the optical disc header signal detection circuit according to the third embodiment of the present invention includes a first comparator 1 for binarizing an input signal shifted upward from the reference voltage by an upper slice level, and a later-described comparator. The second comparator 2, which binarizes the input signal shifted below the reference voltage by the lower slice level generated from the conditional expression for inverting the output of the second comparator, the first comparator 1, and the second comparator The second comparator 2 includes a slice level generator 3 for generating an upper slice level from the output of the comparator 2, and a reference voltage generator 6 for generating a first reference voltage and a second reference voltage.
[0028]
The difference between the present embodiment and the first embodiment is that two reference voltage inputs are a first reference voltage and a second reference voltage which are outputs from the reference voltage generating means 6. The conditions for inverting the output of the second comparator 2 are different, but the other configurations and operations are the same as in the first embodiment.
[0029]
Under such a configuration, the condition that the output of the second comparator 2 is inverted is as follows.
(Voltage of input signal) + (upper slice level) = (first reference voltage) + (second reference voltage)
Rewriting the above formula,
(Voltage of input signal) = (second reference voltage) − {(upper slice level) − (first reference voltage)}
The first reference voltage is set to a voltage higher than the reference voltage by a predetermined amount (for example, near a standard upper slice level), and the second reference voltage is set to the reference voltage. On the other hand, by setting the voltage to be lower by a predetermined amount (for example, near a standard lower slice level), the potential difference between the inputs of the differential pair can be somewhat reduced even if the amplitude of the input signal changes.
[0030]
When the potential difference between the inputs of the differential pair exceeds a certain limit, one of the differential output currents saturates and the other becomes zero. In this state, even if the potential difference between the inputs of the differential pair is further increased, the state of the differential output current does not change, so it can be said that the state exceeds the dynamic range. Therefore, as described above, even if the amplitude of the input signal changes, the dynamic range can be expanded by setting the potential difference between the inputs of the differential pair to be slightly smaller.
[0031]
As described above, in the first, second, and third embodiments, the upper slice level is generated by the conditional expression for inverting the output of the second comparator, but the input signal shifted below the reference voltage is converted to the first comparator. The signal may be input to 1 and binarized, and the second comparator 2 may be rearranged to binarize the input signal shifted above the reference voltage.
[0032]
FIG. 6 is a block diagram showing another example of the configuration of the second comparator 2 of the present invention. As shown in FIG. The sources of the differential pair of the input transistor 8 are connected by resistors 14, and the constant current sources 15 and 16 are connected to each source. Similarly, the sources of the differential pair of the negative input transistor 10 and the positive input transistor 11 are also And the constant current sources 18 and 19 are connected to the respective sources. The drains of the positive input transistors 7 and 11 and the drains of the negative input transistors 8 and 10 are connected to each other and connected to the binarizing means 13 to form two sets. May be connected in parallel.
[0033]
Further, the configuration in which two differential pairs are connected in parallel in the second comparator 2 has been described with reference to FIGS. 5 and 6 as an example of a differential pair using a MOS Nch transistor. Similar effects can be obtained by using a Pch transistor or a bipolar transistor, and in FIG. 6, a MOS type Pch transistor.
[0034]
【The invention's effect】
As described above, according to the optical disk header signal detection circuit of the present invention, there are provided two pairs of differential pairs connected in parallel and the second comparator having the binarizing means, and the reference signal is provided together with the input signal and the upper slice level. By inputting the voltage to the second comparator, a circuit area for arranging a voltage follower and an inverting amplifier required for generating a lower slice level can be reduced. When input is performed, a lower slice level is generated using a conditional expression for inverting the output of the second comparator, and binarization can be performed normally using the lower slice level.
[0035]
Further, an upper peak voltage detecting means, a lower peak voltage detecting means or a reference voltage generating means is provided together with the second comparator, and instead of the reference voltage, the upper peak voltage, the lower peak voltage or the reference voltage is supplied from each of the means. A first reference voltage set to a voltage higher by a predetermined amount and a second reference voltage set to a voltage lower by a predetermined amount than the reference voltage are input to the second comparator, and asymmetric input to the reference voltage is performed. At this time, the lower slice level can be generated by using the conditional expression for inverting the output of the second comparator set in each configuration, and the binarization can be performed normally by the lower slice level.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an optical disk header section signal detection circuit according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of an optical disk header section signal detection circuit according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of an optical disk header section signal detection circuit according to a third embodiment of the present invention.
FIG. 4 is a timing chart showing the timing of an optical disk header section signal detection circuit according to the second embodiment of the present invention and the definition of each voltage.
FIG. 5 is a block diagram showing a configuration example of a second comparator 2 of the present invention.
FIG. 6 is a block diagram showing another configuration example of the second comparator 2 of the present invention.
FIG. 7 is a block diagram showing a configuration of a conventional optical disk header signal detection circuit.
FIG. 8 is a timing chart showing the relationship between the timing and the voltage of the conventional optical disk header section signal detection circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 1st comparator 2 2nd comparator 3,33 Slice level generation means 4 Upper peak voltage detection means 5 Lower peak voltage detection means 6 Reference voltage generation means 7,8,10,11 MOS type Nch transistors 9,12, 15, 16, 18, 19 Constant current source 13 Binarization means 14, 17 Resistors 31, 32 Comparator 34 Voltage follower 35 Inverting amplifier

Claims (3)

Slice level generation means for generating an upper slice level for binarizing an input signal shifted upward with respect to a reference voltage;
A first comparator for binarizing an input signal shifted above the reference voltage by the upper slice level;
A second comparator for binarizing an input signal shifted below the reference voltage by a lower slice level;
Generated from a conditional expression for inverting the output of the second comparator,
(Input signal voltage) = (reference voltage) − {(upper slice level) − (reference voltage)}
An optical disk header signal detection circuit for generating the lower slice level for binarizing an input signal shifted downward with respect to the reference voltage. Slice level generation means for generating an upper slice level for binarizing an input signal shifted upward with respect to a reference voltage;
A first comparator for binarizing an input signal shifted above the reference voltage by the upper slice level;
A second comparator for binarizing an input signal shifted below the reference voltage by a lower slice level;
An upper peak voltage detecting means for detecting an upper peak voltage of the input signal;
A lower peak voltage detecting means for detecting a lower peak voltage of the input signal,
Generated from a conditional expression for inverting the output of the second comparator,
(Voltage of input signal) = (lower peak voltage) + {(upper peak voltage) − (upper slice level)}
An optical disk header signal detection circuit for generating the lower slice level for binarizing an input signal shifted downward with respect to the reference voltage. Slice level generation means for generating an upper slice level for binarizing an input signal shifted upward with respect to a reference voltage;
A first comparator for binarizing an input signal shifted above the reference voltage by the upper slice level;
A second comparator for binarizing an input signal shifted below the reference voltage by a lower slice level;
A reference voltage generator configured to output a first reference voltage set to a voltage higher than the reference voltage by a predetermined amount and a second reference voltage set to a voltage lower by a predetermined amount than the reference voltage;
Generated from a conditional expression that inverts the output of the second comparator,
(Voltage of input signal) = (second reference voltage) − {(upper slice level) − (first reference voltage)}
An optical disk header signal detection circuit for generating the lower slice level for binarizing an input signal shifted downward with respect to the reference voltage.

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