JP2004180386A - Synchronous rectification circuit - Google Patents

Abstract

The present invention relates to a synchronous rectifier circuit, and an object of the present invention is to provide a synchronous rectifier circuit that can reliably turn on a commutation diode when a main switch is off.
A synchronous rectifier circuit of a forward-type DC / DC converter that generates a secondary-side DC voltage by using a rectifying and commutating FET that is alternately turned on / off and that is provided on a secondary side of a conversion transformer T1. The auxiliary winding 4 provided on the secondary side of the conversion transformer T1, and receiving the output of the auxiliary winding 4, securely connect the gates of the rectification FET 2 and the commutation FET 3 disposed between the conversion transformer secondary windings. And an FET gate voltage holding circuit 3 for generating an on / off signal.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a synchronous rectifier circuit for a forward DC / DC converter.
[0002]
2. Description of the Related Art In recent years, as electronic devices have been downsized, power supplies for supplying energy to the electronic devices have also been required to be downsized. For this purpose, a DC / DC converter type power supply has been used as a power supply. In order to supply sufficient energy to a load (electronic device) with a small power supply, it is necessary to improve the efficiency of the power supply.
[0003]
[Prior art]
FIG. 4 is a diagram illustrating a configuration example of a conventional synchronous rectifier circuit, and FIG. 5 is a diagram illustrating operation waveforms of respective units. In FIG. 4, Vin is an input voltage, C1 is a smoothing capacitor connected to both ends of the input voltage, and T1 is a conversion transformer provided in the power conversion unit. The primary winding number of this conversion transformer T1 is N1, and the secondary winding number is N2. A series circuit of the primary winding of the conversion transformer T1 and the FET1, which is a main switch, is connected to both ends of the capacitor C1.
[0004]
Reference numeral 1 denotes a PWM control circuit that drives the main switch FET1. The PWM control circuit 1 changes the width of a pulse for turning on the main switch FET1, and controls the output voltage value on the secondary side of the conversion transformer T1 to be constant. FET2 is a rectifying FET connected in series to the secondary winding of the conversion transformer T1, and FET3 is a commutation FET connected in parallel to a series circuit composed of the secondary winding of the conversion transformer T1 and FET2. . The directions of the drain (D) and source (S) of these FET2 and FET3 are as shown in the figure.
[0005]
L is a choke coil connected to one end of the secondary winding, and Co is a smoothing capacitor connected between the other end of the choke coil L and a common line. A choke coil L and a capacitor Co constitute a smoothing circuit. A load 2 is connected to the secondary output.
[0006]
It should be noted that parasitic diodes D1 and D2 exist in the directions shown in the drawing in FET2 and FET3, respectively. The output voltage is fed back to the PWM control circuit 1, and the PWM control circuit 1 detects the output voltage and controls the time when the main switch FET1 is turned on so that the output value becomes constant.
[0007]
The operation of the circuit thus configured will be described with reference to FIG. In FIG. 5, (a) is an on / off pulse signal output from the PWM control circuit 1. In the figure, Ton is the time when the main switch FET1 is turned on, and Toff is the time when the main switch FET1 is turned off. (B) is the drain-source voltage Vds1 of the main FET1, (c) is the secondary winding voltage Vt2 of the conversion transformer T1, (d) is the gate voltage Vgs2 of the FET2, and (e) is the drain voltage Id2 flowing through the FET2. (F) is the gate voltage Vgs3 of the FET3, and (g) is the drain current Id3 flowing through the FET3.
[0008]
A voltage is applied between the gate and source of the main FET 1 by an on-voltage signal from the PWM control circuit 1 as shown in FIG. At this time, the input voltage Vin is applied between the primary windings of the conversion transformer T1, and an (A) voltage corresponding to the turns ratio (N2 / N1) is generated between the secondary windings as shown in (c). I do. In (c), since only the AC component of the primary winding voltage is transmitted to the secondary winding, the DC component of the voltage generated on the secondary side of the conversion transformer T1 is removed as shown in (c). It will be. Hereinafter, N1 is used as the primary winding of the conversion transformer T1, and N2 is used as it is as the secondary winding.
[0009]
The breakdown of one cycle of the voltage generated between the secondary windings can be considered as divided into (A), (B), and (C) as shown in (c). As described above, (A) corresponds to a period in which the main switch FET1 is on. At this time, the (A) voltage is applied between the gate and the source of the FET2 by the loop of the start of the winding of the secondary winding of the conversion transformer T1, the gate of the FET2, the source of the FET2, the parasitic diode D1 of the FET2, and the end of the winding of the secondary winding. Is applied. Therefore, the FET2 is turned on, and the current Id2 is supplied to the load 2 through the smoothing filter of the FET2 → the choke coil L → the smoothing capacitor Co.
[0010]
On the other hand, when the main FET 1 is off, the voltage of the secondary winding of the conversion transformer T1 is inverted as shown in (c), and a voltage as shown in (B) of (c) is generated. At this time, the (B) voltage is applied between the gate and source of the FET3 by the loop of the end of the winding of the secondary winding of the conversion transformer T1, the gate of the FET3, the source of the FET3, the parasitic diode D2 of the FET3, and the beginning of the winding of the secondary winding. Is applied. Therefore, the FET 3 is turned on, and the choke coil L becomes an energy supply source, and supplies energy to the load 2 through the choke coil L → the capacitor Co → the smoothing filter of the FET 3.
[0011]
However, in the section (C) of (c), since the secondary winding voltage is 0, the gate-source voltage is not applied, the FET 3 cannot be turned on, and all the load current flows to the parasitic diode D2 of the FET 3. It will flow.
[0012]
This circuit has a very simple configuration and is the most commonly used system. However, in recent years, it has been required to reduce the size and efficiency of a power supply and to output a low voltage.
[0013]
Note that a device for turning on the FET 3 is also provided during the section (C) described above (for example, see Patent Document 1).
[0014]
[Patent Document 1]
Japanese Patent No. 2999905 (page 4, FIG. 1)
[0015]
[Problems to be solved by the invention]
The above-described circuit is very simple and is the most commonly used circuit. However, in recent years, there has been a demand for downsizing, higher efficiency, and lower voltage output of a power supply. In the conventional circuit shown in FIG. 4, since there is a period shown in (C) of FIG. 5 (c), it cannot be turned on during a period when the FET 3 must be turned on. During this period, all the current flows through the parasitic diode D2 of the FET3. However, since the forward voltage Vf of the parasitic diode is about 1 V, the loss expressed by the current × voltage eventually becomes large, and the efficiency is improved. It is a factor that hinders.
[0016]
Furthermore, since the speed (reverse recovery time) of this parasitic diode is slow, even at the moment when the main FET 1 is turned on, a current still exists in the parasitic diode. In this period, since the short-circuit current flows through the main FET 1, the loss of the primary-side main FET 1 also increases.
[0017]
In order to solve such a problem, it is necessary to connect a Schottky barrier diode (Vf ≒ 0.4 V) having a low forward voltage Vf in parallel, which has been a factor for increasing the cost and increasing the size.
[0018]
In the case of low-voltage output, the turns ratio of the conversion transformer T1 is large, and a voltage sufficient to operate the rectifying FET 2 cannot be obtained. Therefore, generally, the drive winding of the rectifying FET 2 is wound around the conversion transformer T1. FIG. 6 is a diagram illustrating an example of an FET drive circuit using the auxiliary winding (tertiary winding) of the conversion transformer T1. The same components as those in FIG. 4 are denoted by the same reference numerals.
[0019]
In this circuit, an auxiliary winding (tertiary winding) N3 is provided in a conversion transformer T1, and a rectifying FET 2 and a commutation FET 3 are driven by a voltage generated in the auxiliary winding N3. In this case, the voltage Vo generated on the secondary side is represented by the following equation.
[0020]
Vo = (N2 / N1) · D · Vin
Here, Vo is the output voltage, N1 is the number of turns of the primary winding of the conversion transformer T1, N2 is the number of turns of the secondary winding of the conversion transformer T1, and D is the duty ratio, which is represented by (Ton / T). Here, T is a pulse period, and when a frequency is f, D is represented by the following equation.
[0021]
D = Ton / T
However, in this circuit as well, the voltage for turning on the FET 3 has a period shown in FIG. FIG. 7 is a diagram showing operation waveforms of each part of the circuit shown in FIG. (A) is the voltage Vt2 between the secondary windings of the conversion transformer T1, (b) is the gate voltage Vgs2 of the rectifying FET 2, (c) is the drain current Id2 flowing through the rectifying FET 2, and (d) is the gate of the commutating FET 3. The voltage Vgs3, (e) is the drain current Id3 flowing through the commutation FET3.
[0022]
Between the secondary windings of the conversion transformer T1, there is a period (C) in addition to (A) and (B). During this period, no voltage is applied to the gate of the commutation FET 3, so that the commutation FET 3 is turned on. No, the current flows through the parasitic diode D2.
[0023]
The present invention has been made in view of such a problem, and an object of the present invention is to provide a synchronous rectifier circuit that can reliably turn on a commutation diode when a main switch is off.
[0024]
[Means for Solving the Problems]
(1) FIG. 1 is a principle circuit diagram of the present invention. The same components as those in FIG. 4 are denoted by the same reference numerals. In the figure, reference numeral 4 denotes an auxiliary winding (tertiary winding) provided in the conversion transformer T1, and 3 denotes an auxiliary winding connected to the auxiliary winding 4. This is an FET gate voltage holding circuit that generates a signal for reliably turning on / off the gates of the synchronous rectification FETs (FET2 and FET3) arranged between the next windings.
[0025]
With this configuration, in the period (C) of FIG. 7A, the FET gate voltage holding circuit 3 generates a gate voltage for turning on the commutation diode FET3, so that the FET 3 is turned on. You can continue to. As a result, no current flows through the parasitic diode D2 of the FET3, and the occurrence of loss can be prevented.
[0026]
Further, according to the present invention, since the power supply for operating the FET gate voltage holding circuit 3 is obtained from the auxiliary winding of the conversion transformer T1, even if the voltage value of the output voltage Vo is extremely low, the circuit can be reliably formed. Can work.
(2) In the invention according to claim 2, the FET gate voltage holding circuit is for holding a Zener diode connected in series between an auxiliary winding of the conversion transformer and a gate of a commutation FET, and holding the Zener voltage thereof. Characterized in that it includes a capacitor.
[0027]
With this configuration, the voltage applied to the gate of the commutation FET 3 can be held by the Zener voltage of the Zener diode even during the period (C) in which the voltage of the secondary winding of the conversion transformer T1 is 0, The commutation FET 3 can be kept on.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0029]
FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1 are denoted by the same reference numerals. In the figure, reference numeral 3 denotes a gate voltage holding circuit that drives the rectification FET 2 and the commutation FET 3. An on / off signal is input from the gate voltage holding circuit 3 to the gates of the rectification FET 2 and the commutation FET 3.
[0030]
In the gate voltage holding circuit 3, C1 is a capacitor, D3 is a diode, R1 is a resistor, and ZD1 is a Zener diode. One end of the auxiliary winding 4 is connected to the capacitor C2 and the Zener diode ZD1, and the auxiliary winding 4 is provided with a midpoint potential, which is connected to the common line of the secondary side output circuit. Is connected to
[0031]
The other end of the auxiliary winding 4 is connected to the anode side of the diode D3, and the cathode side of the diode D3 is connected to the resistor R1. The other end of the Zener diode ZD1 is connected to the other end of the resistor R1. The other end of the capacitor C2 is connected to a connection point between the diode D3 and the resistor R1. Then, a drive signal is input to the gate of the commutation FET 3 from the connection point between the Zener diode ZD1 and the resistor R1. A drive signal is input to the gate of the rectifying FET 2 from one end of the auxiliary winding 4. The operation of the circuit thus configured will be described with reference to operation waveforms shown in FIG.
[0032]
FIG. 3 is a diagram showing operation waveforms of each unit according to the embodiment of the present invention. In the figure, (a) is the voltage Vt2 between the secondary windings of the conversion transformer T1, (b) is the gate voltage Vgs2 of the rectification FET 2 (voltage Vt3 between the auxiliary windings of the conversion transformer T1), and (c) is the rectification FET 2 , The drain voltage Id2 flowing through the commutation FET 3 is shown, (d) is the gate voltage Vgs3 of the commutation FET 3, and (f) is the drain current Id3 flowing through the commutation FET 3.
(When main switch FET1 is ON)
When the main switch FET1 is on, a voltage Vt3 as shown in (b) and a voltage Vt4 as shown in (d) are generated between the auxiliary windings 4 of the conversion transformer T1. A positive voltage is generated at Vt3, and the rectifying FET 2 is turned on. At this time, the capacitor C2 is charged by the loop of the auxiliary winding (a) of the conversion transformer T1, the diode D3, the capacitor C2, and the driving winding (b) of the transformer T1.
[0033]
This charged voltage is supplied to the Zener diode ZD1 via the resistor R1. Therefore, the holding voltage of the Zener diode ZD1 is applied to the gate voltage of the commutation FET 3 with respect to the auxiliary winding (b) of the conversion transformer T1. At this time, a negative voltage is generated at Vt4. here,
If the condition of the voltage | generated at the holding voltage | − | Vt4 of | ZD1 <the gate operating voltage of FET3 is satisfied, the commutation FET3 is not turned on.
(When main switch FET1 is off)
When the main switch FET1 is off, the voltage shown in (a) and (B) is generated as Vt4. In this voltage waveform, the period shown in (C) of (a) exists, but in the voltage Vgs3 applied to the gate of the FET 3, the voltage charged in the capacitor C1 is applied to the Zener diode ZD1 via the resistor R1. Supplied. Therefore, the holding voltage of the Zener diode ZD1 is applied to Vgs3 even in the period (C).
[0034]
By setting this holding voltage higher than the gate operation voltage of the commutation FET 3, the FET 3 can maintain the ON operation for a necessary period. The setting conditions of this circuit are as follows.
(N3 / N1) · Vin> Zener voltage> Gate operating voltage of FET3 where Vin is the input voltage, N1 is the number of primary turns of the conversion transformer T1, and N3 is the number of turns of the auxiliary winding.
[0035]
In FIG. 3, in the waveform (e) (gate voltage Vgs3 of FET3), the broken line indicates the voltage between the auxiliary windings of the conversion transformer T1, and the solid line indicates the waveform of Vgs3. The period during which the FET3 is turned on extends from t1 to t2. As a result, even in the region shown in FIG. 3C, the voltage applied to the gate of the FET3 is applied, and the FET3 is turned on.
[0036]
As described above, according to the present invention, since the FET 3 can be kept on, the current does not flow through the parasitic diode of the FET 3 and the occurrence of loss can be prevented. Further, according to the present invention, since the power supply for operating the FET gate voltage holding circuit 3 is obtained from the auxiliary winding of the conversion transformer T1, even if the voltage value of the output voltage Vo is extremely low, the circuit can be reliably formed. Can work.
[0037]
Furthermore, since the gate of the FET3 is driven by the Zener diode ZD1 operated by the capacitor C2, the voltage applied to the gate of the commutation FET3 is maintained even during the period when the voltage of the secondary winding of the conversion transformer T1 becomes zero. And the commutation FET 3 can be kept on.
[0038]
【The invention's effect】
As described above, according to the present invention, the following effects can be obtained.
(1) According to the first aspect of the present invention, the FET gate voltage holding circuit generates the gate voltage for turning on the commutation diode FET even during the period when the secondary voltage of the conversion transformer T1 becomes zero. The FET can be kept on. As a result, no current flows through the parasitic diode of the FET, and the occurrence of loss can be prevented.
[0039]
Further, according to the present invention, since the power supply for operating the FET gate voltage holding circuit is obtained from the auxiliary winding of the conversion transformer T1, the circuit can be reliably operated even when the voltage value of the output voltage is extremely low. be able to.
(2) According to the second aspect of the present invention, the voltage applied to the gate of the commutation FET 3 by the Zener voltage of the Zener diode is also maintained during the period (C) when the voltage of the secondary winding of the conversion transformer T1 becomes zero. The ON state of the commutation FET 3 can be maintained.
[0040]
As described above, according to the present invention, it is possible to provide a synchronous rectifier circuit that can reliably turn on a commutation diode when a main switch is off.
[Brief description of the drawings]
FIG. 1 is a principle circuit diagram of the present invention.
FIG. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a diagram showing operation waveforms of respective units according to the embodiment of the present invention.
FIG. 4 is a diagram illustrating a configuration example of a conventional synchronous rectification circuit.
FIG. 5 is a diagram showing operation waveforms of respective parts of the circuit shown in FIG.
FIG. 6 is a diagram illustrating an example of an FET drive circuit using an auxiliary winding.
FIG. 7 is a diagram showing operation waveforms of each part of the circuit shown in FIG. 6;
[Explanation of symbols]
2 Load 3 FET gate voltage holding circuit 4 Auxiliary winding T Conversion transformer Co Capacitor C1 Capacitor FET1 Main switch FET2 Rectifying FET
FET3 Commutation FET
L choke coil

Claims (2)

In a synchronous rectification circuit of a forward type DC / DC converter that generates a secondary-side DC voltage by using a rectification and commutation FET that is alternately turned on / off and provided on a secondary side of a conversion transformer,
An auxiliary winding provided on the secondary side of the conversion transformer;
An FET gate voltage holding circuit for receiving an output of the auxiliary winding and generating a signal for reliably turning on / off a gate of a rectifying FET and a commutating FET arranged between the conversion transformer secondary windings;
A synchronous rectifier circuit comprising: The FET gate voltage holding circuit includes a Zener diode connected in series between an auxiliary winding of the conversion transformer and a gate of a commutation FET, and a capacitor for holding the Zener voltage. 2. The synchronous rectifier circuit according to 1.

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