JP2004111549A - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an insulated gate field-effect transistor characterized by a gate electrode.
According to a method of manufacturing a semiconductor device of the present invention, an insulating layer is formed on a semiconductor layer. A metal layer 30a is formed on the insulating layer 20. A metal 32 different from the metal layer 30a is ion-injected into a desired region of the metal layer 30a. The metal layer 30a is patterned to form gate electrodes 30A and 30B.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an insulated gate field effect transistor characterized by forming a gate electrode.
[0002]
[Background Art]
In an insulated gate field effect transistor (MISFET) used in a current semiconductor integrated circuit, a polycrystalline silicon layer doped with a high concentration of impurities is often used as a gate electrode for lowering the resistance. In a semiconductor process used for a specific CMOS circuit (Complementary MOSFET circuit), in order to balance characteristics, as a gate electrode material, N-channel polycrystalline silicon is used for an N-channel MOSFET (NMOSFET) and P-channel MOSFET (PMOSFET) is used. ) Employs P-type polycrystalline silicon. The gate electrode generally has a structure having a refractory metal silicide layer above the gate electrode for the purpose of further lowering the resistance.
[0003]
However, it is known that the polycrystalline silicon layer forming the gate electrode is depleted despite being doped with impurities at a high concentration. When depletion occurs, this is equivalent to inserting a capacitor in series with the gate electrode, and the effective electric field applied to the channel decreases. As a result, the current driving capability of the MOSFET decreases.
[0004]
In order to solve these problems, gate electrode materials having low resistance, not causing gate depletion, and having various work functions have been proposed. For example, Non-Patent Document 1 proposes a structure using a beta tantalum (β-Ta) layer.
[0005]
[Non-patent document 1]
Jeong-Mo Hwang (IEDM Technical Digest 1992, p. 345)
[0006]
[Problems to be solved by the invention]
As described above, the work function of the metal used for the gate electrode often has a value around the intrinsic mid gap energy of silicon of 4.61 eV. Therefore, there is a problem that the absolute value of the threshold voltage increases. This problem can be avoided by lowering the impurity concentration of the channel region. However, if the impurity concentration of the channel region is lowered, punch-through cannot be suppressed.
[0007]
On the other hand, in a SOI (Silicon On Insulator) substrate, that is, a fully depleted SOI-MISFET in which a MISFET is formed in a semiconductor layer formed on an insulator, punch-through can be suppressed even if the concentration of the channel region is low. it can. However, in this case, since the threshold value is determined by the work function value of the metal used for the gate electrode, it is difficult to adjust the threshold value.
[0008]
The present invention relates to a method of manufacturing a semiconductor device having a MISFET, and more particularly, to a method of controlling a threshold voltage when a metal is used for a gate electrode.
[0009]
[Means for Solving the Problems]
The method for manufacturing a semiconductor device according to the present invention includes:
Forming an insulating layer on a semiconductor layer provided on the substrate;
Forming a metal layer made of a first metal on the insulating layer;
Ion-implanting a second metal different from the first metal into the metal layer;
Patterning the metal layer to form a gate electrode.
[0010]
According to the present invention, a metal species different from the metal constituting the gate electrode is ion-implanted into the gate electrode. Therefore, the work function of the gate electrode made of a metal layer can be adjusted. By adjusting the work function, the threshold value can be adjusted, and as a result, a high-performance semiconductor device can be manufactured.
[0011]
Further, the method for manufacturing a semiconductor device according to the present invention includes:
A method for manufacturing a complementary semiconductor device, in which an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor are mounted,
Forming an insulating layer on a semiconductor layer provided on the substrate;
Forming a metal layer made of a first metal on the insulating layer;
Ion-implanting a second metal different from the first metal into a region of the metal layer where a gate electrode of the N-channel insulated gate field effect transistor is formed;
Patterning the metal layer to form gate electrodes of the N-channel insulated gate field-effect transistor and the P-channel insulated gate field-effect transistor, respectively.
[0012]
Further, the method for manufacturing a semiconductor device according to the present invention includes:
A method for manufacturing a complementary semiconductor device, in which an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor are mounted,
Forming an insulating layer on a semiconductor layer provided on the substrate;
Forming a metal layer made of a first metal on the insulating layer;
Ion-implanting a second metal different from the first metal into a region of the metal layer where a gate electrode of the P-channel insulated gate field effect transistor is formed;
Patterning the metal layer to form gate electrodes of the N-channel insulated gate field-effect transistor and the P-channel insulated gate field-effect transistor, respectively.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0014]
(Structure of semiconductor device)
First, the structure of the semiconductor device obtained by the manufacturing method of the present embodiment will be described. FIG. 1 is a sectional view schematically showing a semiconductor device 1000 according to the present embodiment. The semiconductor device 1000 is a CMOS semiconductor device and includes an N-channel insulated gate field effect transistor (NMOSFET) 100A and a P-channel insulated gate field effect transistor (PMOSFET) 100B. The NMOSFET 100A and the PMOSFET 100B are formed on the SOI substrate 10. In the SOI substrate 10, an insulating layer (silicon oxide layer) 14 is formed on a supporting substrate 12, and a semiconductor layer 16 is formed on the insulating layer 14. Note that, in the present embodiment, the semiconductor layer 16 is composed of a low-concentration P-type silicon layer 16. The NMOSFET 100A and the PMOSFET 100B are electrically isolated from each other by element isolation regions 18 formed in the P-type silicon layer 16 of the SOI substrate 10. The element isolation region 18 is formed by an STI (Shallow Trench Isolation) method or the like.
[0015]
Each of the MOSFETs 100A and 100B has a structure in which gate electrodes 30A and 30B are formed on a P-type silicon layer 16 with a gate insulating layer 20 interposed therebetween. The gate electrodes 30A and 30B are metal gate electrodes made of a metal layer.
[0016]
What is important in this embodiment is that when the threshold value of the gate electrode needs to be adjusted, another metal having a work function different from that of the metal is ion-implanted into the base metal layer. The region where the metal ions are implanted in the gate electrode may be either the NMOSFET 100A or the PMOSFET 100B, or both. However, a preferred example of the present embodiment is an example in which tantalum is used for a metal layer serving as a base and nickel is ion-implanted only in a gate electrode region of the PMOSFET 100B. It is preferable that a cap layer (not shown) is formed on the upper surfaces of the gate electrodes 30A and 30B. A channel region (not shown) is provided in the silicon layer 16 immediately below the gate insulating layer 20. The silicon layer 16 is provided with impurity diffusion regions 50 and 60 constituting a source region or a drain region with the channel region interposed therebetween.
[0017]
Then, sidewall insulating layers 40 are formed on both side surfaces of the gate electrodes 30A and 30B. In the NMOSFET 100A, the impurity diffusion layers 50 and 60 are N-type, and in the PMOSFET 100B, the impurity diffusion layers 50 and 60 are P-type. Above the impurity diffusion layers 50 and 60, a silicide layer 70 is formed.
[0018]
(Method of Manufacturing Semiconductor Device)
Next, a method for manufacturing the semiconductor device 1000 shown in FIG. 1 will be described with reference to FIGS. 2 to 4 are cross-sectional views schematically showing manufacturing steps of the semiconductor device shown in FIG.
[0019]
(1) The SOI substrate 10 includes an insulating layer (silicon oxide layer) 14 having a thickness of 100 nm on a supporting substrate 12 and a silicon layer 16 having a thickness of 30 nm on the insulating layer (silicon oxide layer) 14. Use what you have. First, as shown in FIG. 2, an element isolation region 18 is formed in the silicon layer 16 by a known method.
[0020]
(2) Next, as shown in FIG. 2, a gate insulating layer 20a to be the gate insulating layer 20 is formed. As the gate insulating layer 20a, for example, a silicon oxide layer is formed by a thermal oxidation method. Next, a gate electrode layer 30a to be the gate electrodes (metal gate electrodes) 30A and 30B is formed on the gate insulating layer 20a. The gate electrode layer 30a is formed by sputtering, for example, by reactive sputtering. The gate electrode layer 30a is not particularly limited as long as it functions as a metal gate electrode, and preferably has low resistance and can withstand heat treatment in a later step. For example, aluminum, molybdenum, tantalum, tungsten, titanium, or a nitride thereof can be given. Further, a stacked film of a tantalum nitride layer and a tantalum layer can be used for the gate electrode layer 30a. It is preferable to form a cap layer (not shown) on the gate electrode layer 30a in order to prevent the gate electrode layer 30a from being damaged by oxidation in a subsequent oxidation step. Examples of the cap layer include a silicon nitride layer.
[0021]
(3) Then, a metal species different from the metal species constituting the gate electrode layer 30a is ion-implanted into the gate electrode layer 30a. The implantation of the metal ions is performed for adjusting the work function of the gate electrode 30. In the present embodiment, a case where metal ions are implanted into gate electrode 30B of PMOSFET 100B will be described. First, as shown in FIG. 2, a mask layer M1 such as a resist is formed in a region where the NMOSFET 100A is formed so that metal ions are not implanted. Next, metal ions 32 are implanted. As the metal ion 32, a metal species having a work function necessary to obtain a desired work function is used. For example, as a metal having a work function larger than the intrinsic mid gap energy of silicon, nickel, cobalt, platinum, and the like can be given. Examples of the metal having a work function smaller than the intrinsic mid gap energy of silicon include tantalum, aluminum, iron, zinc, and gallium.
[0022]
Next, heat treatment is performed at a temperature of about 450 to 550 ° C. By this heat treatment, the metal ions implanted into the gate electrode layer 30a in the region where the PMOSFET 100B is formed can be diffused, and the gate electrode 30a in which the metal ions are uniformly mixed can be formed in the gate electrode layer 30a.
[0023]
(4) Next, as shown in FIG. 4, the gate electrodes 30A and 30B are patterned by lithography and etching. Thus, the gate insulating layer 20 and the gate electrodes 30A and 30B can be formed.
[0024]
Then, as shown in FIG. 4, impurities are introduced by using the gate electrodes 30A and 30B as a mask to form impurity diffusion layers 50 and 60 constituting a source region or a drain region. Specifically, for example, arsenic ions (As ⁺ ) are implanted into the NMOSFET and boron difluoride ions (BF ²⁺ ) are implanted into the PMOSFET. When forming the impurity diffusion layers of the NMOSFET and the PMOSFET, a mask layer (not shown) such as a resist layer is formed in a predetermined region so that impurity ions of the opposite polarity are not doped. Thereafter, low-temperature annealing at 700 ° C. or lower, preferably 450 to 550 ° C. is performed, whereby the impurity diffusion layers 50 and 60 can be formed in a self-aligned manner.
[0025]
Next, for example, a silicon oxide layer is entirely deposited on the SOI substrate 10 on which the gate electrode 30 is formed by a CVD (Chemical Vapor Deposition) method, and then etched back by a dry etching method to form a sidewall. An insulating layer 40 (see FIG. 1) is formed.
[0026]
Next, a transition metal layer, for example, a Ni layer is formed by a sputtering method, and a silicide layer 70 (see FIG. 1) is formed on exposed portions of the impurity diffusion layers 50 and 60 through annealing. The metal for forming the silicide layer may be any metal such as titanium (Ti) or cobalt (Co) that can form silicide. After that, the unreacted transition metal layer is removed, and the silicide layer 70 is formed by self-alignment. Through the above steps, the semiconductor device 1000 of this embodiment can be formed. Thereafter, an interlayer insulating layer (not shown) and a wiring layer (not shown) can be formed through a wiring process using a normal CMOS process technology.
[0027]
In the present embodiment, the case where metal ions are implanted only into gate electrode 30B of PMOSFET 100B has been described, but the present invention is not limited to this, and metal ions may be implanted only into gate electrode of NMOSFET 100A. Further, the ions may be injected into both gate electrodes of the PMOSFET 100A and the NMOSFET 100B. Although an example in which the SOI substrate 10 is used as the semiconductor layer has been described, a bulk semiconductor substrate may be used.
[0028]
The advantages of the manufacturing method of the present embodiment are as follows.
[0029]
In the present embodiment, in (3), metal ions are implanted into the metal layer forming the gate electrode. Therefore, the work function of the gate electrode can be controlled. By controlling the work function of the gate electrode 30, the threshold value can be adjusted to a desired value. As a result, a high-performance semiconductor device can be manufactured.
[0030]
Further, in the present embodiment, metal is implanted into gate electrode 30 in a region where PMOSFET 100B is formed. Therefore, the work function of the gate electrode 30 can be adjusted. That is, even when the gate electrodes 30A and 30B are formed of the same material for both the NMOSFET 100A and the PMOSFET 100B, the gate electrodes 30A and 30B having different work functions can be formed. In a semiconductor device using a metal gate, there is a method of forming gate electrodes having different work functions by changing the material for forming the gate electrodes 30A and 30B. However, according to this method, for example, after the gate electrode of the PMOSFET is formed, the gate electrode layer formed in the region where the NMOSFET 100A is formed must be peeled off. By peeling off the gate electrode layer, the gate insulating layer is exposed, and the reliability of the semiconductor device is reduced. According to the manufacturing method of the present embodiment, gate electrodes having different work functions can be formed without increasing the number of manufacturing steps, and the threshold can be adjusted. As a result, a high-performance semiconductor device can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment.
FIG. 2 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device shown in FIG.
FIG. 3 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device shown in FIG.
FIG. 4 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device shown in FIG.
[Explanation of symbols]
Reference Signs List 10 SOI substrate, 12 support substrate, 14 silicon oxide layer, 16 semiconductor layer, 20 gate insulating layer, 30A, 30B gate electrode, 40 sidewall insulating layer, 50, 60 source or drain region, 70 silicide layer

Claims (5)

Forming an insulating layer on a semiconductor layer provided on the substrate;
Forming a metal layer made of a first metal on the insulating layer;
Ion-implanting a second metal different from the first metal into the metal layer;
Patterning the metal layer to form a gate electrode. A method of manufacturing a complementary semiconductor device in which an N-channel insulated gate field-effect transistor and a P-channel insulated gate field-effect transistor are mounted,
Forming an insulating layer on a semiconductor layer provided on the substrate;
Forming a metal layer made of a first metal on the insulating layer;
Ion-implanting a second metal different from the first metal into a region of the metal layer where a gate electrode of the N-channel insulated gate field effect transistor is formed;
Patterning the metal layer to form gate electrodes of the N-channel insulated gate field-effect transistor and the P-channel insulated gate field-effect transistor, respectively. A method of manufacturing a complementary semiconductor device in which an N-channel insulated gate field-effect transistor and a P-channel insulated gate field-effect transistor are mounted,
Forming an insulating layer on a semiconductor layer provided on the substrate;
Forming a metal layer made of a first metal on the insulating layer;
Ion-implanting a second metal different from the first metal into a region of the metal layer where a gate electrode of the P-channel insulated gate field effect transistor is formed;
Patterning the metal layer to form gate electrodes of the N-channel insulated gate field-effect transistor and the P-channel insulated gate field-effect transistor, respectively. In claim 3,
The method of manufacturing a semiconductor device, wherein the first metal is tantalum, and the second metal is nickel. In any one of claims 1 to 4,
A method for manufacturing a semiconductor device, wherein the substrate uses an SOI substrate.

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