JP2004111602A - Semiconductor storage device - Google Patents

Abstract

Disturbance and reflow deterioration can be improved, and information retention time can be lengthened.
A memory cell has a structure in which four word lines 2 are provided on one active region 1 and two word lines 2 are provided in a 1-bit corresponding region 8. The first transistor having the first gate 3 uses the diffusion layer 5 at the bit line side junction and the diffusion layer 6 at the second gate 4 side junction as a source / drain, and a second transistor having the second gate 4. The transistor uses the diffusion layer 7 at the junction on the capacitor side and the diffusion layer 6 at the junction on the first gate 3 side as the source / drain. That is, between the first gate 3 and the second gate 4, there is a common source / drain diffusion layer 6 for the two gates, and two first transistors using the diffusion layer 6 as a common source / drain. It has a structure in which the second transistors are connected in series.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a word line structure and operation of a cell transistor in a DRAM (Dynamic Random Access Memory), and more particularly, to a disturbance failure that occurs as a disturbing effect of a miniaturized circuit structure, and an adjacent word line after reflow. The present invention relates to a semiconductor memory device that can prevent reflow degradation in an adjacent word potential mode in which information retention time varies depending on a potential.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a typical memory cell in a DRAM as a semiconductor storage device of this type includes two elements: a capacitor for charge storage and a MOSFET (metal oxide semiconductor / field effect transistor) for charge input / output.
[0003]
For example, as shown in the layout diagram of FIG. 10, the structure is such that two word lines (WL) 102 are arranged on one active region 101 (for example, see Patent Document 1).
[0004]
As shown in FIG. 11, one cell transistor in this structure has one word line (WL) as a gate (G) and one bit line (BL) orthogonal to the word line (WL). The MOSFET connects the source (S) and the capacitor (C) to the drain (D).
[0005]
On the other hand, the amount of information charge has been drastically reduced due to the high integration of the memory cells of the DRAM, and data destruction of the memory cells has occurred. In order to suppress the occurrence of such a defect, an FRAM (ferroelectric RAM) in which a ferroelectric material is introduced into a parallel plate capacitor has been introduced. In this FRAM, in a switch operation using a bistable state of ferroelectric polarization as a storage logic using a bistable state of ferroelectric polarization, there is a problem in reliability such as fatigue deterioration due to a decrease in the amount of polarization and imprint deterioration due to a polarization habit. .
[0006]
In order to solve such a problem, an FRAM including a CMOS transistor formed as a second transistor as shown in FIG. 12 and including a second word line WL2 orthogonal to the word line WL1 has also been proposed (for example, Patent Document 2).
[0007]
[Patent Document 1]
JP-A-2002-9261 (FIG. 2)
[0008]
[Patent Document 2]
JP-A-2002-94024 (FIG. 7)
[0009]
[Problems to be solved by the invention]
In the conventional semiconductor memory device described above, if the cell structure of the DRAM described above has a dimension F where the half pitch of the minimum processing dimension portion is the dimension F as shown in FIG. Is dimension F or less. When the width of a word line is reduced by miniaturization with such a structure, there are the following problems.
[0010]
First, the first problem is that the information holding time is shortened.
[0011]
The reason is as follows. As the width of the word line is reduced by miniaturizing the cell, the threshold voltage Vth of the cell transistor is significantly reduced. In order to prevent this, it is necessary to increase the substrate concentration, but this increases the junction electric field. When the junction electric field is increased in this way, the junction leakage current caused by the junction electric field increases. Therefore, as shown in FIG. 13, as the width of the word line is reduced, the information retention time is shortened.
[0012]
The second problem is that the disturbance (disturb) failure to the cell increases. If the substrate concentration is increased in order to avoid this, a writing failure occurs, and it is difficult to take measures against the disturb failure and the writing failure at the same time. As a result, element performance cannot be achieved.
[0013]
The reason is as follows. As the cells are miniaturized, variations in the processing dimensions of the word lines are the main cause of the variations in the threshold voltage Vth, and therefore, disturb defects increase. In order to avoid this, it is necessary to increase the substrate concentration. However, when the substrate concentration is increased, the variation of the threshold voltage Vth further increases. In addition, when the substrate concentration is increased, the variation toward the high threshold voltage Vth side increases, so that the number of insufficiently written bits increases to cause a writing failure. That is, it is difficult to simultaneously take measures against the disturb failure and the writing failure.
[0014]
A third problem is that reflow degradation increases. A phenomenon in which junction leakage increases after reflow due to thermal stress during IR (infrared) reflow and shortens the information retention time is called reflow deterioration.
[0015]
The reason is as follows. As the cell is miniaturized, the adjacent word line running in parallel approaches the diffusion region, and the junction electric field on the adjacent word line side increases. In this state, if there is a defect on the adjacent word line side, the junction leak current increases due to the stress from the STI (shallow trench element isolation) structure and the stress from the package. Since the stress from this package increases due to thermal stress at the time of IR reflow, junction leakage increases after reflow, and the information retention time is shortened. Such reflow deterioration can be avoided by increasing the potential of the adjacent word line, and is called reflow deterioration in the adjacent word potential mode. As described above, the increase in the junction leak current on the adjacent word line side increases the reflow degradation in the adjacent word potential mode.
[0016]
An object of the present invention is to solve such a problem, disturb failure which occurs as a disturbing effect of a miniaturized circuit structure, and an adjacent word potential mode in which an information retention time varies depending on an adjacent word line potential after reflow. It is an object of the present invention to provide a semiconductor memory device that can prevent reflow deterioration of the semiconductor memory device.
[0017]
[Means for Solving the Problems]
In a semiconductor memory device according to the present invention, one memory cell connected to one bit line in a DRAM has one capacitor and two MOSFETs as transistors. The two transistors have two word lines each consisting of a separate gate electrode orthogonal to the bit line, and are sandwiched between the diffusion layer connected to the bit line and the respective gate electrodes and shared by both. It has a structure in which a diffusion layer and a diffusion layer connected to the capacitor are formed in source / drain regions and connected in series.
[0018]
Specifically, in this semiconductor memory device, one memory cell connected to one bit line has a first word line composed of a first gate electrode and a second word line composed of a second gate electrode. Orthogonal to the bit line, and has one capacitor and the following two transistors formed in the MOSFET.
[0019]
The first transistor is formed by the first gate electrode, and includes a diffusion layer connected to a bit line and a diffusion layer sandwiched between the first gate electrode and the second gate electrode, each of which is a source / drain region. And The second transistor is formed by a second gate electrode, and a diffusion layer sandwiched between the second gate electrode and the first gate electrode and a diffusion layer connected to the capacitor are each a source / drain region. .
[0020]
As described above, the two transistors have a structure in which the diffusion layer sandwiched between the two gate electrodes is connected in series with the common source / drain.
[0021]
Further, at the time of writing / reading, an “on” voltage (Vpp) is applied to the two gates to turn on the two transistors. When information is held, an “off” voltage (0 V) is applied to the first gate, and an intermediate voltage (for example, Vpp / 2) between the “on” voltage and the “off” voltage is applied to the second gate. Is applied.
[0022]
As a result, the channel leak at the time of retaining information is extremely reduced as compared with the case of the conventional single gate electrode, so that the probability of disturb failure becomes extremely small. Further, the transistor having the second gate electrode is in a depleted state, and the electric field at the capacitor-side junction at the end of the second gate electrode can be reduced. As a result, the deterioration of the information retention characteristic due to the junction leak accelerated by the electric field is reduced. Therefore, the deterioration of the information retention characteristic, which is a problem when the adjacent word line is “zero” V after the reflow, that is, the reflow deterioration is not a problem because the second gate electrode is the closest word line on the adjacent word line side. Disappears. In this way, reflow degradation depending on the adjacent word line potential is avoided.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0024]
FIG. 1 is a diagram showing one embodiment of a planar layout of a memory cell portion according to the present invention.
[0025]
In the semiconductor memory device shown in FIG. 1, four word lines 2 orthogonal to the length direction of the active region 1 are arranged on one active region 1. Therefore, one memory cell in the area 8 corresponding to one bit has a structure having two word lines 2. That is, a cell transistor having the first gate 3 and the second gate 4 having substantially the same dimensions on the active region 1 is formed. The first transistor having the first gate 3 has the diffusion layer 5 at the bit line side junction and the diffusion layer 6 at the second gate side junction as the source / drain regions, and the first transistor having the second gate 4. The two-transistor uses the diffusion layer 7 at the capacitor-side junction and the diffusion layer 6 at the first gate-side junction as source / drain regions. That is, between the first gate 3 and the second gate 4, there is a source / drain diffusion layer 6 common to the first gate 3 and the second gate 4, and this diffusion layer 6 is used as a common source / drain region. The first transistor and the second transistor are connected in series (see FIG. 8).
[0026]
Here, assuming that the minimum processing line width F is 0.15 μm, the width Fc of each of the first gate 3 and the second gate 4, the distance between the first gate 3 and the second gate 4, the first gate 3 and the adjacent one. The distance between the first gate 3, the distance between the second gate 4 and the second gate 4 adjacent thereto, and the width Fa of the active region 1 are each “F” of 0.15 μm, and the length of the active region 1 is A memory cell having nine times the size of “F” was formed.
[0027]
FIG. 2 is a sectional view taken along the line AA in the one-bit corresponding area 8 surrounded by a broken line shown in FIG. The one-bit corresponding area 8 indicates the size of one bit, and the cross-sectional structure will be described with reference to FIG.
[0028]
In the p-type well layer 10, a shallow trench isolation layer 11 having a depth of 250 nm in which a silicon oxide film is embedded is formed. Threshold voltage control layers 12 and 13 having different substrate concentrations are formed on the surface of the substrate on which the p-type well layer 10 is formed. One of the threshold voltage control layers 12 having a low substrate concentration is formed in a portion where the second gate 4 is formed. The other threshold voltage control layer 13 having a high substrate concentration is formed in a portion where the first gate 3 is formed. The gate oxide film 14 is the same for the first gate 3 and the second gate 4.
[0029]
A first transistor using the diffusion layer 5 and the diffusion layer 6 of the bit line side portion 18 as a source / drain using the first gate 3 as a gate electrode, and a diffusion layer 7 and a diffusion layer of the capacitor side portion 19 using the second gate 4 as a gate electrode. One cell is composed of two MOSFETs including a second transistor having the layer 6 as a source and a drain. Each of the diffusion layers 5 and 7 may have a structure in which deep diffusion layers 20 and 21 are formed at a deeper portion.
[0030]
Next, a process flow for achieving the structure shown in FIG. 2 will be described with reference to FIGS. Note that the drawings are schematic diagrams, and do not match the scales of the dimensions described. Further, the peripheral circuit portion is not necessary for the description of the present invention, and is therefore omitted.
[0031]
First, as shown in FIG. 3, a p-type well layer 10 having a retrograde boron concentration distribution and a shallow trench element isolation layer 11 having an element isolation width of 0.15 μm and a depth of 0.25 μm are provided on a substrate. Is formed. Specific boron concentration distribution is about 1 × ¹⁰ 17 ^{cm -3} to a depth of approximately the depth 250nm from the surface of the substrate consisted deeper than partial and 3 × ¹⁰ 17 ^{cm -3} approximately to a depth of about 750nm .
[0032]
Next, as shown in FIG. 4, boron is introduced into the entire surface of the active region to form a threshold voltage control layer 12 having a peak concentration of 6 × 10 ¹⁷ cm ⁻³ at a depth of about 50 nm. .
[0033]
Thereafter, as shown in FIG. 5, boron is introduced into the center of the active region to form a threshold voltage control layer 13 having a peak concentration of 1.5 × 10 ¹⁸ cm ⁻³ at a depth of about 30 nm. Is done.
[0034]
Next, as shown in FIG. 6, a gate oxide film 14 having a thickness of 7 nm is formed, a gate electrode made of polycrystalline silicon having a thickness of 70 nm and tungsten silicide having a thickness of 120 nm, a first gate 3 and a second gate. Gate 4 is formed. Note that a silicon nitride film 15 for gate processing is formed on the first gate 3 and the second gate 4.
[0035]
Next, as shown in FIG. 7, after the step of oxidizing the gate side surface (not shown), phosphorus is introduced into a portion serving as a source / drain to obtain a peak concentration of 2 × 10 ¹⁸ cm ⁻³ at a depth of about 25 nm. The diffusion layers 5, 6, 7 are formed as follows.
[0036]
Thereafter, as shown in FIG. 2, sidewalls 16 are formed on the side surfaces of the first gate 3 and the second gate 4, respectively, and a bit line connection is formed on the diffusion layer 5 by depositing an interlayer insulating film 17 and performing contact processing. A contact hole 18 for connecting a capacitor and a contact hole 19 for connecting a capacitor are formed on diffusion layer 7. After the formation of the contact holes 18 and 19, phosphorus is introduced from the contact holes 18 and 19 into portions deeper than the diffusion layers 5 and 7, so that a peak concentration of 1 × 10 ¹⁸ cm ⁻³ is obtained at a depth of about 50 nm. Such diffusion layers 20 and 21 are formed.
[0037]
Thereafter, a plug is formed by burying polycrystalline silicon in the contact hole by a usual method, a bit line is connected to the plug on the bit line side, and a base electrode of the capacitor is connected to the plug on the capacitor side. A capacitor film and an upper electrode are formed on the capacitor base electrode to form a capacitor.
[0038]
Next, with reference to FIGS. 8 and 9 and FIG. 2, an operation function at the time of writing and reading and at the time of holding information in the above structure will be described.
[0039]
First, as shown in FIG. 8, one first transistor has a first gate 3 as a gate G1, a diffusion layer 5 at a bit line (BL) side junction as a source S1, and a diffusion layer at a second gate side junction. 6 is the drain D1. In the other second transistor, the second gate 4 is a gate G2, the diffusion layer 7 at the capacitor (C) side junction is a drain D2, and the diffusion layer 6 at the first gate side junction is a source S2. That is, the diffusion layer 6 serves as a common drain D1 and source S2 for the first transistor and the second transistor, and the first transistor and the second transistor are connected in series. Accordingly, the bit line BL is connected to the source S1, and the drain D2 is connected to the capacitor C via the first and second transistors in series.
[0040]
The gates G1 and G2 are respectively connected to word lines WL1 and WL2 orthogonal to the bit line BL, and the voltage applied to each can be independently controlled by the word lines WL1 and WL2.
[0041]
As shown in FIG. 9, at the time of writing and reading, an on-voltage (Vpp) is applied to the two gates G1 and G2 to turn on both the first transistor and the second transistor. When information is held, an off voltage (0 V) is applied to the gate G1, and an intermediate voltage (for example, Vpp / 2) between the on voltage and the off voltage is applied to the gate G2.
[0042]
As a result, the channel leak at the time of retaining information is extremely reduced as compared with the case of the conventional single gate electrode, so that the probability of disturb failure becomes extremely small. Further, the second transistor having the gate G2 is in a depleted state, and the electric field at the junction on the capacitor side at the end of the gate G2 can be reduced. As a result, the deterioration of the information retention characteristic due to the junction leak accelerated by the electric field is reduced. Therefore, the information retention characteristic deterioration, which is a problem when the adjacent word line becomes 0 V after the reflow, that is, the reflow deterioration is a problem because the nearest word line WL2 by the gate G2 is arranged in the middle on the adjacent word line WL1 side. Will not be. In this way, reflow degradation depending on the potential of the adjacent word line is avoided.
[0043]
The potentials of the gate G1 and the gate G2 were operated as shown in FIG.
[0044]
First, the threshold voltage Vth of the first transistor having the gate G1 was 1 V, and the threshold voltage Vth of the second transistor having the gate G2 was 0.5 V.
[0045]
At the time of writing and reading, an on-voltage (Vpp = 3.6 V) was applied to the two gates G1 and G2 to turn on both the first transistor and the second transistor. When information is held, 0 V is applied to the gate G1 to turn off the first transistor, and 0 V and an intermediate voltage "1.8 V" of "Vpp = 3.6 V" are applied to the gate G2. By applying the voltage, the second transistor was turned on from the depletion state. At this time, the ON voltage Vpp and the intermediate potential are applied almost alternately to the gate G2 on the side of the adjacent word line WL1.
[0046]
At the time of writing and reading, an on-voltage (Vpp) is applied to the two gates to turn on both the first transistor and the second transistor. In this case, since the second transistor having the gate G2 is arranged in series with the first transistor having the gate G1, there is a concern that the on-current may be reduced. However, the second transistor having the gate G2 can obtain a sufficient on-current because the threshold voltage Vth is low. For this reason, there is almost no influence on the on-current controlled by the first transistor having the gate G1.
[0047]
On the other hand, when information is held, 0 V is applied to the gate G1 to turn off the first transistor, and an intermediate voltage between 0 V and the on-voltage Vpp is applied to the gate G2. In this case, the channel current of the second transistor having the gate G2 was about "1/10" of the normal on-current. As a result, the total channel current of the first transistor and the second transistor was about "1/10" of the channel current in the case of only the first transistor having the gate G1. Usually, the fact that the channel current becomes “1/10” corresponds to the fact that the threshold voltage Vth has increased by about 90 mV. Therefore, if the variation σ of the threshold voltage Vth is about 90 mV, the probability of causing information leakage due to the channel current, that is, a disturbance failure can be reduced by σ. The conventional probability of disturb failure is about 10 ⁻⁷ , and from this probability, in this embodiment, the probability of disturb failure can be reduced by σ, which means that the probability of disturb failure can be reduced to about 10 ⁻⁹ .
[0048]
Also, in the case of information retention, the information retention characteristics may be degraded by a junction leak current affected by a junction electric field between the capacitor-side diffusion layer and the p-type well layer. In particular, when the stress near the bonding position increases due to thermal stress during reflow, the electric field equivalently increases as the band cap becomes narrower. Therefore, the junction leakage current further increases, and the information retention characteristics are likely to deteriorate. This phenomenon is called reflow deterioration. In this case, the junction field is extremely small because the substrate concentration of the second transistor having the gate G2 is low. As a result, information retention characteristics are improved. Due to the improvement of the information holding characteristic, the reflow deterioration rate is reduced. Further, when the junction electric field is small, the influence of the band gap narrowing due to the stress is reduced, and the reflow deterioration rate is reduced.
[0049]
Further, the on-voltage Vpp and the intermediate potential are applied almost alternately to the gate G2 on the adjacent word line side. The junction electric field is easily affected by the potential of the gate to which the diffusion layer is in contact. When comparing the case where the potential of the gate is 0 V and the intermediate voltage between 0 V and the ON voltage Vpp, the intermediate electric field between 0 V and the ON voltage Vpp is obtained. Voltage is smaller. As a result, since the gate in contact with the capacitor-side diffusion layer is the gate G2, the reflow deterioration rate is reduced by the small junction electric field. As a result, it was possible to almost avoid the deterioration of the information holding characteristic which becomes a problem when the adjacent word line is at 0 V after the reflow. In the present embodiment, the reflow deterioration rate was reduced to the conventional "1/5" at the reflow of 260 degrees Celsius.
[0050]
In the above description, the width of the second gate has been described as the dimension F, which is the same as that of the first gate, but a dimension smaller than the dimension F may be used. When the size is smaller than the dimension F, the cell size can be reduced accordingly.
[0051]
Further, when the potential of the second gate was made lower than that in the above embodiment, the probability of disturb failure could be further reduced. However, since the junction electric field became large, the reflow deterioration rate increased compared to the case of the above embodiment. Further, when the potential of the second gate is higher than in the above embodiment, the probability of disturb failure is higher than in the above embodiment, but the reflow deterioration rate is smaller than in the above embodiment.
[0052]
As described above, by selecting the potential at the second gate at the time of holding information, it is possible to cope with both cases where there are many disturbance failures and where there is a lot of reflow deterioration.
[0053]
Further, as described above, the channel impurity concentration immediately below the first gate electrode is higher than the impurity concentration immediately below the second gate electrode in order to maintain the information retention characteristics. The threshold voltage is set to approximately "1/2" of the threshold voltage applied to the first transistor.
[0054]
Further, in the above description, the boosted voltage “Vpp” is applied to each of the first gate electrode and the second gate electrode at the time of data writing and reading of the memory cell, and the first gate of the first gate is held at the time of information holding. Although the voltage “zero” is applied to the electrode and the voltage “Vpp / 2” is applied to the electrode of the second gate, the voltage “zero” is applied to the electrode of the first gate and the second An intermediate voltage from the voltage “zero” to the voltage “Vpp” may be applied to the gate electrode.
[0055]
【The invention's effect】
As described above, according to the present invention, the disturbance failure which is a problem in the miniaturization of the DRAM and the deterioration in which the information retention time fluctuates depending on the adjacent word line potential after reflow, that is, in the adjacent word potential mode, The countermeasure against reflow deterioration can be taken, and the information holding time can be lengthened. As a result, a highly reliable memory cell can be obtained in addition to a reduction in power consumption.
[0056]
The reason is that, in the memory cell, a second transistor is further formed between one transistor and one capacitor and inserted in series, and a second word line including a second gate electrode in the second transistor is formed. Is provided in parallel with the main first word line.
[0057]
With this structure, the channel impurity concentration immediately below the gate electrodes of the two transistors, the threshold voltage of the two transistors, or the voltage applied to the gate electrodes of the two transistors can be changed so as to obtain an optimum effect. Because.
[Brief description of the drawings]
FIG. 1 is a diagram showing one embodiment of a layout in a memory cell according to the present invention.
FIG. 2 is a diagram showing an embodiment of an AA cross section of the memory cell of FIG. 1;
FIG. 3 is a diagram showing an embodiment of an initial process result for obtaining the structure of FIG. 2;
4 is a diagram showing an embodiment of a process result subsequent to FIG. 3 in order to obtain the structure of FIG. 2;
FIG. 5 is a diagram showing an embodiment of a process result subsequent to FIG. 4 in order to obtain the structure of FIG. 2;
6 is a diagram showing an embodiment of a process result subsequent to FIG. 5 in order to obtain the structure of FIG. 2;
7 is a diagram showing an embodiment of a process result in the process of proceeding to FIG. 2 following FIG. 6 in order to obtain the structure of FIG. 2;
FIG. 8 is a diagram showing an embodiment of an equivalent circuit in the memory cell of FIG. 1;
FIG. 9 is a diagram showing an embodiment of application of an applied voltage to a gate during operation in the memory cell circuit of FIG. 8;
FIG. 10 is a diagram showing an example of a layout in a conventional memory cell.
11 is a diagram illustrating an example of an equivalent circuit in the memory cell of FIG. 10;
FIG. 12 is a diagram showing an example of a layout in a conventional memory cell different from FIG. 10;
FIG. 13 is a diagram showing a relationship between a conventional word line width and information retention characteristics.
[Explanation of symbols]
Reference Signs List 1 active region 2 word line 3 first gate 4 second gate 5, 6, 7, 20, 21 diffusion layer 8 one-bit corresponding region 10 p-type well layer 11 shallow trench element isolation layer 12, 13 threshold voltage control layer 14 gate oxide film 15 silicon nitride film 16 sidewall 17 interlayer insulating film 18, 19 contact hole

Claims (6)

In a DRAM (Dynamic Random Access Memory) composed of a plurality of memory cells, one memory cell connected to one bit line has one capacitor and two transistors. The transistor has two word lines each including a gate electrode orthogonal to the bit line, and a diffusion layer connected to the bit line and a diffusion layer sandwiched between the gate electrodes and common to the transistor. A semiconductor memory device comprising a layer and a diffusion layer connected to the capacitor as a source / drain region for each of the two gate electrodes, and has a structure in which the layers are connected in series. In a DRAM, one memory cell connected to one bit line has one capacitor, a first transistor and a second transistor, and a first word line including a first gate electrode And a second word line composed of a second gate electrode orthogonal to the bit line,
The first transistor includes a diffusion layer formed by the first gate electrode and connected to a bit line, and a diffusion layer sandwiched between the first gate electrode and the second gate electrode. Region, and the second transistor is formed by a second gate electrode, each of a diffusion layer sandwiched between the second gate electrode and the first gate electrode and a diffusion layer connected to the capacitor. A semiconductor memory device having a structure including a second transistor serving as a source / drain region. 3. The semiconductor memory device according to claim 2, wherein a channel impurity concentration immediately below the first gate electrode is higher than an impurity concentration immediately below the second gate electrode. 3. The semiconductor memory device according to claim 2, wherein the threshold voltage of the second transistor is set to substantially "1/2" of the threshold voltage applied to the first transistor. 3. The method according to claim 2, wherein a step-up voltage “Vpp” is applied to each of the first gate electrode and the second gate electrode during data writing and reading of the memory cell. A semiconductor memory device, wherein a voltage “zero” is applied to the first gate electrode and a voltage “Vpp / 2” is applied to the second gate electrode. 3. The method according to claim 2, wherein a step-up voltage “Vpp” is applied to each of the first gate electrode and the second gate electrode during data writing and reading of the memory cell. A semiconductor memory device, wherein a voltage “zero” is applied to the first gate electrode and an intermediate voltage from a voltage “zero” to a voltage “Vpp” is applied to the second gate electrode.

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