JP2004112077A - AD converter, multi-channel AD converter, X-ray sensor module, and control method thereof - Google Patents

Abstract

An object of the present invention is to suppress the influence of substrate noise and enable a signal reading operation with high accuracy and high speed.
A sampling and holding circuit for sampling an output signal level from a charge detection circuit, and a sampling and holding circuit output signal level sampled by the sampling and holding circuit, the charge detection circuit receiving a signal from an external charge generation circuit. An oversampling AD converter 7 which is an AD conversion circuit which performs AD conversion by sampling for AD conversion within a predetermined period (T3) excluding a stable read period (T4) from a charge read period for reading charges. .
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an AD converter, a multi-channel AD converter, an X-ray sensor module, and a control method thereof, and more particularly, includes an electric charge detection circuit, an amplifier circuit, a sample-and-hold circuit, and an oversampling AD (Analog to Digital) converter. The present invention relates to an AD converter, a multi-channel AD converter in which a plurality of the circuit systems are arranged, an X-ray sensor module in which an X-ray sensor is provided in the circuit system, and a control method thereof.
[0002]
[Prior art]
In the field of medical X-ray inspection apparatuses, X-ray image sensors are being developed in place of X-ray films and image intensifiers (photomultipliers). The X-ray image sensor has characteristics such as high resolution of pixels, high-speed processing of pixel signals, etc., can cope with moving image shooting, and is easily digitized. Further, since the X-ray image sensor can be applied to a wide range of examinations from general still image photography to contrast examinations of digestive organs, hearts, blood vessels, and the like, it will be important for the network age of medical information in the future. A signal readout circuit used in such an X-ray image sensor includes an A / D converter that reads out pixel signals with high precision and high speed in order to cope with reading out of a still image and a moving image at a high resolution as described above. Becomes indispensable.
[0003]
FIG. 4 is a block diagram showing a configuration of a multi-channel AD converter used for a signal readout circuit of an X-ray image sensor disclosed in Japanese Patent Application Laid-Open No. 2002-94379.
[0004]
The multi-channel AD converter shown in FIG. 4 has a plurality of signal input terminals 1 to n corresponding to the multi-channel. In the multi-channel A / D converter, a charge detection circuit 100, an amplification circuit 110, a sample-and-hold circuit 60, an oversampling A / D converter 70, and a latch circuit 120 at the output of the A / D converter are connected to the respective signal input terminals 1 to n. Each of the latch circuits 120 is connected to a multiplexer (multiplex circuit) 130 for selecting and outputting one of the AD signals of the signals input from the respective channels. Further, a buffer 140 for amplifying the output signal of the multiplexer 130 and outputting the amplified signal to an external circuit is connected.
[0005]
With such a configuration, the multi-channel A / D converter shown in FIG. 4 operates in a circuit system connected to each of the signal input terminals 1 to n to simultaneously process a large number of pixel data and convert the A / D converted output signal into a latch circuit 120. The output signal is time-divisionally selected by the multiplexer 130 and output to the external circuit via the buffer 140.
[0006]
FIG. 5 is a block diagram showing a configuration of an X-ray sensor module using the multi-channel AD converter shown in FIG.
[0007]
The X-ray sensor module shown in FIG. 5 has a sensor screen 16. The sensor screen 160 converts X-rays irradiated on the screen into signal charges. This is a 9-inch panel on which line conversion elements are arranged. Each X-ray conversion element is provided with a TFT (thin film transistor) for extracting a signal charge generated in each X-ray conversion element. Further, the X-ray sensor module shown in FIG. 5 includes a gate driver circuit 150 for driving a TFT for extracting a signal charge of the X-ray conversion element, and a multi-channel AD conversion for converting a signal charge output from the TFT into an electric signal. A signal conversion circuit 170 using the device is provided, and the gate driver circuit 150 and the signal conversion circuit 170 are connected to the sensor screen 160 by a gate line and a data line, respectively.
[0008]
FIG. 6 is a circuit diagram showing a part of the X-ray conversion element constituting the sensor screen 160.
[0009]
In the circuit diagram shown in FIG. 6, the gate lines 330 and 320 are orthogonal to the data lines 190 and 200, and four TFTs 210, 220, 230 and 240 and four X-ray conversion elements 250 , 260, 270 and 280 are arranged in pairs. For example, the drain terminal and the gate terminal of the TFT 210 are connected to the data line 190 and the gate line 330, respectively, and the source terminal of the TFT 210 is connected to the X-ray conversion element 250. The drain terminal and the gate terminal of the TFT 220 are connected to the data line 190 and the gate line 320, respectively, and the source terminal of the TFT 220 is connected to the X-ray conversion element 260. The drain terminal and the gate terminal of the TFT 230 are connected to the data line 200 and the gate line 330, respectively, and the source terminal of the TFT 230 is connected to the X-ray conversion element 270. The drain terminal and the gate terminal of the TFT 240 are connected to the data line 200 and the gate line 320, respectively, and the source terminal of the TFT 240 is connected to the X-ray conversion element 280.
[0010]
The operation of the X-ray sensor module will be described with reference to the circuit diagram shown in FIG. Although the total number of the gate lines shown in FIG. 5 is 2,880, only one of the sets of the divided 1440 gate lines is selected at the time of signal readout in operation. It is controlled as follows.
[0011]
In the circuit diagram shown in FIG. 6, when the gate line 330 is selected, the TFTs 210 and 230 are turned on, and only the signal charges generated by the X-ray conversion element 250 are read out to the data line 190. Only the signal charges generated by the X-ray conversion element 270 are read from the data line 200. The signal charges read from the data lines 190 and 200 are digitized by a signal conversion circuit 170 in which the above-described multi-channel AD converter is incorporated.
[0012]
In this case, in order to capture a moving image with the X-ray sensor module, it is necessary to AD convert signal charges corresponding to image data of 30 screens per second.
[0013]
The number of gate lines that are driven and controlled in one screen is 1440 as described above. Therefore, the time for AD conversion of a signal selected and read out from one gate line is 1 second ÷ 30 screens ÷ 1440 lines ≒ 23 μs (43.2K samples / sec).
[0014]
FIG. 7 is a detailed circuit diagram of the signal reading unit of the multi-channel AD converter and the X-ray sensor pixel unit of the X-ray sensor module.
[0015]
The signal readout unit 250 shown in FIG. 7 corresponds to the charge detection circuit 100, the amplification circuit 110, and the sample hold circuit 60 of the multi-channel AD converter shown in FIG. 4, and the X-ray sensor pixel of the X-ray sensor module shown in FIG. The unit 180 is a charge generation source including the above-described X-ray conversion element and TFT.
[0016]
When X-rays enter the X-ray sensor of the X-ray sensor pixel unit 180 shown in FIG. 7, a pair of electrons (e) and holes (h) are generated in the photoelectric conversion layer of the X-ray conversion element. The electrons (e) or holes (h) reach the pixel electrode of the X-ray conversion element by the bias voltage and are held by the charge holding capacitor 101. The charge storage capacitor 101 is connected between the pixel electrode and ground (ground). The pixel electrode is connected to, for example, a source terminal of the TFT 102. The signal charge held in the charge holding capacitor 101 is applied to the gate line to which the gate terminal of the TFT 102 is connected by applying a TFT gate clock a to turn on the TFT 102, so that the signal charge is transferred from the source terminal to the drain terminal of the TFT 102. Then, the charge flows out to the data line to which the drain terminal is connected, and is input to the charge detection circuit 100 of the signal reading unit 250 connected to the data line, and the charge amount is detected.
[0017]
The charge detection circuit 100 of the signal reading unit 250 includes an operational amplifier 105, a feedback capacitor 104, and a reset switch 103. A reference voltage Vr is input to a non-inverting input terminal (+) of the operational amplifier 105 and fixed. A feedback capacitor 104 is connected between the inverting input terminal (−) and the output terminal of the operational amplifier 105, and a negative feedback circuit is configured. A reset switch 103 whose on / off state is controlled by the first reset clock b is connected in parallel to the feedback capacitor 104.
[0018]
The amplifier circuit 110 provided at the next stage of the charge detection circuit 100 includes an operational amplifier 133, a feedback capacitor 132, and a reset switch 131. The reference voltage Vr is input to a non-inverting input terminal (+) of the operational amplifier 133. It is fixed, and a feedback capacitor 132 is connected between the inverting input terminal (−) and the output terminal of the operational amplifier 133 to form a negative feedback circuit. A reset switch 131 whose on / off state is controlled by the second reset clock f is connected to the feedback capacitor 132 in parallel.
[0019]
The amplifier circuit 110 is provided to amplify the signal voltage to a voltage range where the dynamic range of the AD converter can be effectively used when the output voltage of the charge detection circuit 100 is small. In the case of an X-ray sensor, in a shooting mode of still image shooting, the period during which X-rays are irradiated is short, so that even if the X-ray dose is sufficiently increased, the effect on the human body is small. Therefore, in the shooting mode of still image shooting, the X-ray dose is large and the signal charge amount is large, so that the amplifier circuit 11 is not necessarily required.
[0020]
However, in the moving image capturing mode, it is necessary to set the X-ray irradiation period to a minute unit. In order to avoid the influence on the human body, the irradiated X-ray dose of the moving image capturing is compared with that of the still image capturing. It is necessary to make it about two digits weaker. Therefore, in the moving image shooting mode, the signal charge amount at the time of shooting a moving image is extremely small, and the output voltage of the charge detection circuit 100 is reduced. Therefore, the amplifier circuit 11 is required. Specifically, it is necessary to handle a charge amount of about 700e (e indicates a unit charge amount).
[0021]
A resistor 290 and a capacitor 300 are connected in series between the output terminal of the operational amplifier 105 of the charge detection circuit 100 and the inverting input terminal of the operational amplifier 133 of the amplifier circuit 110. The resistance element 290 and the capacitor 300 connected in series constitute a low-pass filter, and the capacitor 300 constituting the low-pass filter also acts as an input capacitance Cin for the inverting input terminal of the operational amplifier 133 of the amplifier circuit 110. As described above, the feedback capacitor 132 is connected between the inverting input terminal and the output terminal of the operational amplifier 133 to form a negative feedback circuit. In this case, the amplification factor (G) of the operational amplifier If Cf, G = Cin / Cf.
[0022]
The output signal of the amplifier circuit 111 is input to the sample and hold circuit 60, sampled and held by the sample and hold circuit 60, and sent to the oversampling AD converter 70. As described above, the operation of the sample and hold circuit 60 needs to be controlled by the sample and hold clock c of 43.2K samples / sec (23 μs) in order to cope with the operation in the shooting mode of moving image shooting.
[0023]
Such a configuration is disclosed in Japanese Patent Application Laid-Open No. 2002-51264. With this configuration, low-frequency noise or the like output from an X-ray sensor is removed by a correlated double sampling method, and a resistance element, a capacitance, and the like are removed. The low-pass filter eliminates thermal noise due to the parasitic resistance of the data line in the X-ray sensor.
[0024]
That is, since a low-frequency noise is generally superimposed on a signal output from a solid-state imaging device and adversely affects image quality, noise is reduced by a correlated double sampling method in order to read out a signal and perform AD conversion. There is a need. In the correlated double sampling method, a reference input (referred to as INr) and a data input (referred to as INd) which are successively input in time are respectively sampled, and a difference signal (INr-INd) is output to an actual pixel output. This is a method that uses data. Thereby, even if low frequency noise is superimposed on the input signal, it can be canceled by the difference processing. By simply adding the resistance element 290 and the capacitor 300 to the correlated double sampling circuit, a low-pass filter capable of reducing the thermal noise of the data line in the X-ray sensor can be configured.
[0025]
FIG. 8 is a block diagram showing a configuration of the oversampling AD converter 70. In the application of the X-ray sensor, it is necessary to improve the accuracy of a 14-bit class in order to realize a high resolution, and it is necessary to use an oversampling ΔΣ method.
[0026]
An oversampling AD converter 70 shown in FIG. 8 includes an A / D analog unit 340 including a switched capacitor type integrator using an operational amplifier, a capacitor, and a switch and a comparator, and an A / D that performs digital filter processing. It comprises a digital section 350. The A / D analog section 340 receives the output signal of the sample hold circuit 60, and the A / D digital section 350 outputs the signal that has been subjected to the AD conversion processing to the latch 120. The latch circuit 120 is controlled based on the sample and hold clock f.
[0027]
The A / D analog section 340 has the configuration of the oversampling ΔΣ type AD converter as described above, outputs the result of the AD conversion processing as a 1-bit bit stream, and outputs the output signal as a next-stage decimation filter. It is input to the functioning A / D digital section 350. The over-sampling clock d used in the over-sampling AD converter 70 is about 256 times 11 MHz which is about 256 times as large as 43.2 K samples / sec of the sample and hold clock f for controlling the operation of the sample and hold circuit 60 described above. It is necessary to oversample.
[0028]
The reason why an oversampling frequency 256 times the sample and hold frequency of the sample and hold circuit 60 is necessary for the operation of the oversampling AD converter 70 will be described. The oversampling ΔΣ method uses two high-precision techniques of noise shaping by oversampling and a ΔΣ circuit.
[0029]
Oversampling is a technique for reducing the quantization noise in the signal band and sampling the signal by sampling at a speed faster than twice the required signal band. For example, the quantization noise in the signal band becomes 1 / N by N times oversampling.
[0030]
In the noise shaping, the signal is integrated, quantized, and differentiated by the oversampling AD converter 70, whereby only the quantization noise is multiplied by the differentiation characteristic, the quantization noise in the low frequency region is reduced, and the signal is increased. This is a technique for improving accuracy.
[0031]
Combining the two techniques of oversampling and noise shaping can significantly reduce quantization noise in the signal band. As described above, when the quantization resolution is 1 bit and the order of the noise shaping is the second order, oversampling of 256 times is theoretically required to secure the accuracy of 14 bits or more.
[0032]
Thus, the oversampling AD converter 70 receives the oversampling clock d of about 11 MHz into the A / D analog unit 340 and the A / D digital unit 350, and the oversampling AD converter 70 performs a high-speed operation. .
[0033]
The signal output from the sample hold circuit 60 and input to the oversampling AD converter 70 is modulated into a 1-bit signal of 11 MHz by a 1-bit ΔΣ circuit in the A / D analog section 340, and decimation is performed in the A / D digital section 350. The data is converted to 14-bit data while being thinned out to 43.2 KHz by the filter.
[0034]
As described above, the decimation filter of the A / D digital section 350 removes the high-frequency quantization noise included in the 11 MHz 1-bit output signal output from the A / D analog section 340, and removes the target 43.2 KHz. An operation of thinning out a 14-bit signal by a factor of 1/256 is performed by a digital circuit.
[0035]
FIG. 9 is a block diagram of a read section of the output data subjected to the AD conversion processing of the multi-channel AD converter shown in FIG.
[0036]
The reading unit of the output data that has been subjected to the AD conversion processing illustrated in FIG. 9 includes a multiplexer 130 and a buffer 140. The 14-bit data simultaneously processed by the over-sampling AD converter of each channel and sampled at a period of 43.2K samples / sec are latched by the respective latches 120 for each channel at the same time, and then multi-sequenced by the multiplexer 130. Is converted to time-divided data for each stream. The converted data is sequentially output from the multi-channel AD converter to the external circuit by the buffer 140, and the operation of the multi-channel AD converter is completed. In this case, the multiplexer 130 and the buffer 140 operate based on the AD read clock g.
[0037]
Next, the overall operation of the multi-channel AD converter shown in FIG. 4 will be described with reference to the timing chart of each signal shown in FIG.
[0038]
In a period T1, which is a reset period of the timing chart shown in FIG. 10A, the first reset clock b and the second reset clock f are each in the ON state, and the charge detection circuit 100 of the signal reading unit 250 shown in FIG. The reset switch 103 and the reset switch 131 of the amplifier circuit 110 are both turned on by the first reset clock b and the second reset clock f, respectively, to connect between the inverting input terminal and the output terminal of each of the operational amplifiers 105 and 133. Both are short-circuited and reset. At this time, since the TFT gate clock a is off, the TFT 2 of the X-ray sensor pixel unit 180 of the X-ray sensor panel is off. At this time, the output terminal of the amplifier circuit 110 is in the reset state, and the reference voltage Vr is being output.
[0039]
Subsequently, in the period T8, the first reset clock b is turned off, the reset switch 103 of the charge detection circuit 100 is turned off by the first reset clock b, and the operational amplifier 105 of the charge detection circuit 100 starts operating. On the other hand, the second reset clock f keeps the on state, and the second reset clock f keeps the on state of the reset switch 131 of the amplifier circuit 110, so that the offset noise and flicker noise of the operational amplifier 105 and X The low frequency component noise of the line sensor pixel section 180 is absorbed by the capacitor 300 (correlated double sampling method). At this time, the output terminal of the amplifier circuit 110 is in the reset state, and the reference voltage Vr is being output.
[0040]
Next, in the period T2, the second reset clock f is also turned off, the reset switch 131 of the amplifier circuit 110 is also turned off by the second reset clock f, and the operational amplifier 133 of the amplifier circuit 110 starts operating. .
[0041]
Next, in a period T3 which is a charge reading period, the TFT gate clock a is turned on, and the TFT 102 is turned on by the TFT gate clock a, so that the charge holding capacitance of each X-ray sensor pixel unit 180 constituting the X-ray sensor panel is turned on. From 101, a signal charge corresponding to the received X-ray dose is transmitted from the source terminal of the TET 102 to the drain terminal, and further transmitted to the charge detection circuit 100 via a data line to which the drain terminal is connected, and is converted into a signal voltage.
[0042]
Reading the signal charge from the charge storage capacitor 101 requires time due to the influence of the parasitic resistance and the parasitic capacitance of the data line in the X-ray sensor pixel unit 180. Therefore, it is necessary to set the period T3 sufficiently long so that the charges in the charge storage capacitor 101 are completely read. The signal voltage based on the read signal charges output from the charge detection circuit 100 is amplified by the low-pass filter including the resistor 290 and the capacitor 300 while removing the thermal noise of the data line while having the feedback capacitor 132 and the operational amplifier 133. The voltage is amplified by the circuit 110 and output from the output terminal of the amplifier circuit 110. In this output signal, offset noise and flicker noise of the operational amplifier 105 and low-frequency component noise of the X-ray sensor pixel unit 180 are canceled by the correlated double sampling method.
[0043]
Next, in the period T5, the TFT gate clock a is turned off, the TFT 102 is turned off by the TFT gate clock a, and the signal charge is read out from the charge holding capacitor 101 of each X-ray sensor pixel unit 180, and the charge detection is performed. The output voltage of the signal read circuit including the circuit 100 and the amplifier circuit 110 is determined.
[0044]
Next, in the period T6, the sample hold clock c is turned on, and the output voltage signal of the signal readout circuit amplified by the amplifier circuit 110 is sampled by the sample hold circuit 60 and held until the next cycle. On the other hand, the oversampling AD converter 70 oversamples the sample and hold output voltage of the sample and hold circuit 6 based on an oversampling clock d having a frequency of 11 MHz which is 256 times the sample and hold clock frequency of 43.2 KHz.
[0045]
Then, in the period T7, each oversampling AD converter 70 outputs 14-bit data, which is an AD converter output signal, and is simultaneously latched by each latch circuit 120 for each stream. Thereafter, the 14-bit data output from the latch circuit 120 is converted by the multiplexer 130 operating based on the AD read clock g into data obtained by time-dividing each series of data for each series. The time-divided data is sequentially output from the buffer 140 that operates based on the AD read clock g to an external circuit, for example, as an AD output m-1, an AD output m, and an AD output m + 1. Operation is completed.
[0046]
The above-described multi-channel AD converter includes a large-scale digital circuit that operates with a high-speed clock such as an A / D digital unit 350 that performs digital filter processing in the oversampling AD converter 70, and an A / D analog unit 340. A simple analog circuit is an analog / digital mixed circuit in which the analog circuits are mixed on the same substrate, and it is necessary to sufficiently consider digital noise measures. Digital noise generated by the operation of the digital circuit causes deterioration of characteristics of the analog circuit. That is, when the digital circuit operates, a relatively large current is momentarily generated in the power supply line due to the on / off operation of the transistor, and the power supply voltage fluctuates, or the voltage fluctuation of the diffusion layer of the transistor causes the capacitance between the substrate and the substrate to change. To generate noise on the substrate. Such substrate noise affects an analog circuit sharing a semiconductor substrate and causes a deterioration in characteristics of the analog circuit.
[0047]
FIG. 10B is a timing chart of each signal when there is substrate noise from the digital circuit.
[0048]
As shown in FIG. 10B, substrate noise is generated by the operation of the digital circuit of the oversampling AD converter 70 that operates based on the oversampling clock d. This substrate noise is mixed into the charge detection circuit 100 that is most sensitive to noise, and the signal amplified by the amplifier circuit 11 is sampled and held by the sample and hold circuit 6 and output. As a result, the performance of the correlated double sampling operation deteriorates, and the performance of the sample and hold circuit 60 deteriorates due to the superposition of noise on the sample and hold output signal.
[0049]
Japanese Patent Laying-Open No. 5-143187 discloses a configuration for preventing the characteristic degradation of an analog circuit caused by such substrate noise. In the configuration disclosed in this publication, when an analog signal is sampled into a capacitor based on the operation timing of a switch, that is, when the switch is turned off and the sampled information is held, the operation reference clock of the digital circuit is stopped. By providing the means, digital noise is not added to the analog signal held by the capacitor, and the characteristic deterioration of the analog circuit can be prevented.
[0050]
[Patent Document 1]
JP-A-2002-94379 (page 4, FIG. 1)
[Patent Document 2]
JP-A-2002-51264 (page 3, FIG. 1)
[Patent Document 3]
JP-A-5-143187 (page 3, FIG. 1)
[0051]
[Problems to be solved by the invention]
However, if the configuration disclosed in JP-A-5-143187 is directly incorporated into the multi-channel AD converter shown in FIG. 4, the following problem occurs.
[0052]
Considering the oversampling AD converter 70, a high-speed oversampling clock d having a frequency of 11 MHz is generated by a switched capacitor type integrator using an operational amplifier, a switch and a capacitor, and a comparator, as shown in FIG. The A / D analog unit 340 and the A / D digital unit 350 that perform digital filter processing as a digital noise source are input to both the A / D analog unit 340 and the A / D digital unit 350. Signal processing is performed at the same clock frequency. In this case, the operation of only the digital circuit unit cannot be stopped as in the configuration disclosed in Japanese Patent Application Laid-Open No. 5-143187. In addition, there is a method of adjusting the phase of the oversampling clock d input to the A / D digital unit 350 and the A / D analog unit 340. However, the oversampling clock frequency is as high as 11 MHZ, and the influence of digital noise is reduced. Detection of no phase difference is very difficult.
[0053]
Considering the signal reading unit 250 including the charge detection circuit 100, a signal handled by the charge detection circuit 100 at the time of capturing a moving image is an extremely small signal. Therefore, in the charge detection circuit 100, in addition to suppressing the thermal noise generated in the operational amplifier 105 and the feedback capacitor 104 and securing the dynamic range of the signal, it is necessary to suppress the power supply noise, the ground noise, and the silicon substrate noise as low as possible. . In particular, in the charge detection circuit 100, when the capacitance value of the built-in feedback capacitor 104 is Cf, and the total capacitance of the data line connected to the X-ray sensor unit and the input terminal of the charge detection circuit 100 is Ct, The noise on the input side of the amplifier 100 is amplified by a factor of Ct / Cf and appears at the output terminal of the charge detection circuit 100.
[0054]
Specifically, for example, when Cf is determined to be 4 pF from the detection sensitivity of the signal charge, since Ct is about Ct = 40 pF, noise generated from a transistor or the like on the input side of the charge detection circuit 100 is amplified about 10 times. Output. Therefore, as compared with the noise mixing in the analog circuit of the A / D analog section 340 of the oversampling AD converter 70, the noise mixing in the charge detection circuit 100 particularly causes a remarkable reduction in S / N.
[0055]
As described above, when the oversampling AD converter 70 is used for high-precision reading of a signal, a large-scale digital circuit of the A / D digital unit 350 and a switched capacitor integration circuit of the A / D analog unit 340 are used. Since high-speed operation is performed by a high-frequency clock signal, silicon substrate noise, power supply noise, ground noise, and the like flow into the charge detection circuit 100 and the amplification circuit 110, and the accuracy of signal reading in the entire multi-channel AD converter can be improved. I can't.
[0056]
An object of the present invention is to solve such a problem, and an object of the present invention is to provide an AD converter, a multi-channel AD converter, which can perform a signal reading operation with high accuracy and high speed while suppressing the influence of substrate noise. An object of the present invention is to provide an X-ray sensor module and a control method thereof.
[0057]
[Means for Solving the Problems]
An AD converter according to the present invention includes a sampling and holding circuit for sampling an output signal level from a charge detection circuit, and an AD conversion circuit for sampling and sampling the output signal level of the sampled sampling and holding circuit for AD conversion within a predetermined period. And the above object is achieved.
[0058]
Preferably, in the AD converter according to the present invention, the charge detection circuit is reset by a reset clock, the sample and hold circuit controls a sampling operation by a sampling and hold clock, and the AD conversion circuit performs an AD conversion by an oversampling clock. The operation is controlled, and the oversampling clock is controlled so that the charge detection circuit performs the sampling operation within a predetermined period excluding the stable readout period from the end of the charge readout period for reading out the signal charge from the external charge generation circuit. A / D-converts the output signal level of the sampling and holding circuit sampled by the sampling and holding clock.
[0059]
Further, preferably, in the AD converter of the present invention, the reset clock, the sampling hold clock, and the oversampling clock can be independently controlled.
[0060]
Still preferably, in the AD converter according to the present invention, an amplifier circuit including a low-pass filter is provided between the charge detection circuit and the sample hold circuit, and the amplifier circuit is reset by a reset clock, and the reset clock can be independently controlled. It is.
[0061]
A multi-channel AD converter according to the present invention includes the AD converter according to any one of claims 1 to 4 arranged for each channel, and outputs each AD converter and an AD output signal of each AD converter. Each latch circuit for latching, a multiplexer for selectively outputting each output signal from each latch circuit in a time-division manner, and a buffer for driving the output signal of the multiplexer are provided on the same semiconductor substrate, Thereby, the above object is achieved.
[0062]
An X-ray sensor module according to the present invention includes an X-ray sensor and the multi-channel AD converter according to claim 6, wherein an output signal of the X-ray sensor is input to a charge detection circuit. This achieves the above object.
[0063]
Further, preferably, in the X-ray sensor module of the present invention, the X-ray sensor includes an X-ray conversion element, a charge holding capacity means for holding the charge generated in the X-ray conversion element, and a charge storage capacity means for storing the charge. A plurality of X-ray sensor pixel units each including a switch circuit for controlling output are arranged.
[0064]
Further, preferably, in the X-ray sensor module of the present invention, the charge readout clock for controlling the on / off operation of the switch circuit can be independently controlled.
[0065]
In the control method of the AD converter according to the present invention, a first step of resetting an output signal level of a charge detection circuit by a reset signal, and after resetting, reading out a signal charge from an external charge generation circuit to a sample and hold circuit; A second step of performing an A / D conversion process on the output signal level of the sample and hold circuit by turning on the oversampling clock; and outputting the output of the A / D conversion circuit after completion of the A / D conversion operation within a predetermined period of the oversampling clock. A third step of outputting a signal, a fourth step of providing a predetermined noise removal period in the charge generation circuit, and an output signal level of a sample and hold circuit to be A / D converted in a next signal readout period by a sampling and holding clock. Sampled until the next signal readout period. A fifth step of holding the output signal level of the hold circuit, which has at least one cycle a series of steps including the above-described object can be achieved.
[0066]
According to the control method of the multi-channel AD converter of the present invention, a first step of resetting an output signal level of a charge detection circuit by a reset signal, and reading out a signal charge from an external charge generation circuit to a sample and hold circuit after resetting A second step of performing an A / D conversion process on the output signal level of the sample and hold circuit by turning on the oversampling clock; and outputting the A / D conversion circuit output after the completion of the A / D conversion process within a predetermined period of the oversampling clock. A third step of outputting a signal, a fourth step of providing a predetermined noise elimination period in the charge generation circuit, and a sampling and holding clock for setting the output signal level of the sample and hold circuit to be A / D converted in the next signal reading period. Sampling and sampling until the next signal readout period A fifth step of holding the output signal level of the AD converter circuit in the latch circuit and latching the output signal of the AD converter circuit in the latch circuit, and reading the AD converter circuit output signal of the AD converter circuit latched by the latch circuit. A sixth step of time-divisionally selecting with a clock controlled multiplexer and outputting to an external circuit via a buffer, comprising at least one cycle, thereby achieving the above object. You.
[0067]
The method for controlling an X-ray sensor module according to the present invention includes a first step of resetting an output signal level of a charge detection circuit by a reset signal, reading a signal charge from the X-ray sensor to a sample and hold circuit after resetting, and performing oversampling. A second step of performing an A / D conversion process on the output signal level of the sample and hold circuit by turning on the clock, and outputting an output signal of the A / D conversion circuit after the completion of the A / D conversion process within a predetermined period of the oversampling clock. A third step, a fourth step of providing a predetermined noise elimination period in the X sensor, and sampling by a sampling and holding clock as an output signal level of a sample and hold circuit to be A / D-converted in a next signal reading period. Sample hold until signal readout period A fifth step of holding the output signal level of the AD converter circuit and latching the output signal of the AD converter circuit in the latch circuit, and reading out the AD converter circuit output signal of the AD converter circuit latched by the latch circuit. A sixth step of time-divisionally selecting with a clock-controlled multiplexer and outputting to an external circuit via a buffer, comprising at least one cycle, thereby achieving the above object. Is done.
[0068]
The operation of the above configuration will be described below.
[0069]
The AD converter according to the present invention turns on an oversampling clock for controlling an oversampling A / D converter as an A / D conversion circuit within a predetermined period excluding a stable reading period from an end portion of a charge reading period and performs oversampling A / D conversion. By operating the detector, it is possible to prevent the substrate noise from being mixed into the input portion of the charge detection circuit, which is most affected by the substrate noise, to realize high-precision reading of the signal charges, and to perform high-speed reading.
[0070]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0071]
FIG. 1A is a block diagram illustrating a configuration of a main part of an AD converter according to an embodiment of the present invention and a charge generation circuit that outputs signal charges to the AD converter.
[0072]
An AD converter 9 shown in FIG. 1A includes a charge detection circuit 10 for detecting signal charges on the same semiconductor substrate, a sample-and-hold circuit 6 for sampling an output signal level from the charge detection circuit 10, and a sample-and-hold circuit 6. An oversampling A / D converter 7 which is an A / D conversion circuit for performing an A / D conversion on the output signal of the X-ray sensor is provided. read out. FIG. 1B shows a timing chart of each signal in the AD converter 9 at the time of reading the signal. Here, the charge generation circuit 8 shown in FIG. 1A assumes the X-ray sensor pixel unit 180 including the X-ray conversion element, the charge storage capacitor 101, and the TFT 102 shown in FIG. The X-ray sensor pixel unit 180 is not limited as long as it has a function of generating electric charges.
[0073]
The charge generation circuit 8 shown in FIG. 1A performs an on / off operation based on a charge generation unit (not shown), a charge storage capacitor 1 for holding signal charges generated by the charge generation unit, and a charge read clock a. It has a read switch 2. The charge storage capacitor 1 is connected between one terminal of the read switch 2 and a region in which the reference voltage Vr is set, and the other terminal of the read switch 2 is connected to a charge detection circuit of the AD converter 9 via a data line. Connected to circuit 10. The signal charge held in the charge holding capacitor 1 is transmitted to the data line to which the read switch 2 is connected and connected to the data line when the charge read clock a is applied and the read switch 2 is turned on. The charge is input to the charge detection circuit 10 of the AD converter 9 and the charge amount is detected.
[0074]
The charge detection circuit 10 of the AD converter 9 includes an operational amplifier 5, a feedback capacitor 4, and a reset switch 3. A reference voltage Vr is input to a non-inverting input terminal (+) of the operational amplifier 5, and is fixed. The feedback capacitor 4 is connected between the inverting input terminal (−) and the output terminal of the operational amplifier 5 to form a negative feedback circuit. A reset switch 3 whose on / off state is controlled by the reset clock b is connected in parallel to the feedback capacitor 4.
[0075]
The output signal level of the charge detection circuit 1 is input to a sample and hold circuit 6 controlled based on a sample and hold clock c, sampled and held by the sample and hold circuit 6, and the sample and hold circuit 6 output signal level is The signal is input to the oversampling AD converter 7 controlled based on the oversampling clock d and is oversampled. Then, the oversampling AD converter 7 outputs the result of the AD conversion process as an AD converter output signal level.
[0076]
The charge read clock a, reset clock b, sample hold clock c, and oversampling clock d shown in FIG. 1A are set so as to be independently controllable.
[0077]
Next, the operation of the AD converter 9 will be described in detail with reference to the timing chart shown in FIG.
[0078]
In a period T1, which is a reset period shown in FIG. 1B, the charge read clock a of the charge generation circuit 8 is off, and the read switch 2 is turned off by the charge read clock a. In the A / D converter 9, in the charge detection circuit 10, the reset switch 3 is turned on by the reset clock b being on, and the inverting input terminal and the output terminal of the operational amplifier 5 are short-circuited. As a result, the data line connecting the read switch 2 of the charge generation circuit 8 and the inverting input terminal of the operational amplifier 5, the inverting input terminal, the non-inverting input terminal and the output terminal of the operational amplifier 5 are all reset to the reference voltage Vr. Preparation for charge reading is performed. At this time, by turning off the oversampling clock d of the oversampling AD converter 7 and stopping it, it is possible to prevent substrate noise from being mixed in the reference voltage Vr which is the reset voltage of the charge detection circuit 10.
[0079]
Subsequently, in a period T2, the reset clock b is turned off, the reset switch 3 of the charge detection circuit 10 is turned off by the reset clock b, and the operation of the charge detection circuit 10 starts.
[0080]
If the oversampling clock d is on (operating) when the reset switch 3 is turned off and the substrate noise enters the charge detection circuit 10, the read switch 2 of the charge generation circuit 8 is connected. Due to the large parasitic resistance and parasitic capacitance of the data line, the potential difference between the output voltage and the input voltage of the operational amplifier 5 of the charge detection circuit 10 via the ON resistance of the reset switch 3 (the ON resistance of the TFT). Is generated, and the potential difference is held by the feedback capacitor 4 of the operational amplifier 5 of the charge detection circuit 10 to cause noise. As described above, when noise is added to the reference voltage Vr, which is the reset voltage, the charge readout by the charge detection circuit 10, the sample and hold by the sample and hold circuit 6, and the AD conversion operation by the oversampling AD converter 7 are correctly performed. Even if it is performed, a different random offset appears in each AD conversion cycle (read cycle) as a noise component. Therefore, in the period T1, the data line to which the readout switch 2 of the charge generation circuit 8 is connected and the charge detection circuit 10 are sufficiently reset, and the oversampling clock input to the oversampling AD converter 7 during the period T1 to T2. It is very important that d is turned off and stopped.
[0081]
Next, in the period T3, the charge read clock a input to the charge generation circuit 8 is turned on, and the read switch 2 of the charge generation circuit 8 is turned on by the charge read clock a, and is stored in the charge holding capacitor 1. The read signal charge is read out to the charge detection circuit 10 via the readout switch 2 and the data line. The same voltage as the reference voltage Vr supplied to the charge detection circuit 10 is supplied to the lower electrode of the charge storage capacitor 1. Here, assuming that the charge amount of the charge storage capacitor 1 is Qd and the capacitance value of the feedback capacitor 4 of the operational amplifier 5 of the charge detection circuit 10 is Cf, the output voltage (charge detection circuit output signal level) of the charge detection circuit 10 is , Vr + (Qd / Cf). Further, as described above, it takes time to read the signal charge stored in the charge storage capacitor 1 due to the influence of the parasitic resistance and the parasitic capacitance of the data line to which the readout switch 2 of the charge generation circuit 8 is connected. It needs to be set long.
[0082]
As shown in FIG. 1B, the period T3 needs to be very long compared with the period T1 which is a reset period of the charge detection circuit 10 and the period T6 which is a sampling period of the sample and hold circuit 6, and therefore, one cycle is required. Occupies most of the signal readout period. Further, as described in the oversampling AD converter 70 shown in FIG. 8, when the quantization resolution is 1 bit and the order of noise shaping is 2nd order, it is theoretically necessary to secure an accuracy of 14 bits or more in signal reading. Oversampling of the upper 256 times is required. Therefore, during the signal reading period of one cycle, the oversampling AD converter 7 needs to perform an AD conversion process on the output signal of the sample and hold circuit of the sample and hold circuit 6 with a clock for 256 cycles. In the present embodiment, it is necessary to input a clock for 256 cycles to the oversampling AD converter 7 during the period T3.
[0083]
In this case, even if the oversampling clock d for 256 cycles is operated only in the period T3, the ratio of the period T3 to the one-cycle signal read period is large. In comparison with the case where the oversampling clock d is operated, the number of clocks for 256 cycles can be maintained only by slightly increasing the frequency of the oversampling clock d. Therefore, the signal reading period of one cycle can be maintained as it is, and high-speed reading of signals is possible.
[0084]
In the period T3 in the charge readout period, the circuit is affected by the substrate noise. However, as shown in the timing chart of FIG. 1B, the readout of the signal charge from the charge generation circuit 8 is completed, and the charge readout clock a is generated. If the oversampling clock d is turned off and stopped before the end of the period T4 in which the readout switch 2 is turned off by the charge readout clock a, the charge detection circuit 10 is stabilized without the influence of substrate noise. The reading of the signal charges can be completed in the operation state, and the influence of the substrate noise can be removed. That is, in the operation period of the oversampling clock d in the period T3, the reading of the signal charges from the charge generation circuit 8 via the data line is almost completed, and the oversampling clock 7 is stopped in the next stable reading period T4. Because of this state, a stable reading state without substrate noise is obtained.
[0085]
The period in which the periods T3 and T4 are combined is a charge readout period. At the start time of the next period T5, the charge readout clock a is turned off, and the readout switch 2 is turned off by the charge readout clock a.
[0086]
The period T5 is a period necessary for removing and stabilizing feedthrough noise from the charge read clock a for controlling the on / off operation of the read switch 2 of the charge generation circuit 8. The feedthrough noise is noise generated when the potential on the input side is transmitted to the output side through the capacitance between the electrodes of the readout switch 2 when the readout switch 2 is off.
[0087]
Next, in a period T6, the sample hold clock c is turned on, and the sample hold circuit 6 is controlled based on the sample hold clock c. Then, a stable output signal from the charge detection circuit 10 is output to the sample-and-hold circuit 6, and the output signal is sampled by the sample-and-hold circuit 6, and held as a sample-and-hold circuit output signal level until the next signal charge read cycle. Is done. At this time, since the oversampling clock d is stopped, the sample and hold circuit 6 samples the output signal from the charge detection circuit 10 in a stable state without substrate noise, and holds the signal until the next signal reading period. Become. On the other hand, the oversampling A / D converter 7 receives the oversampling clock d for 256 periods in the above-mentioned T3 period, and oversamples the output voltage of the sample and hold circuit 6.
[0088]
Then, in the period T7, the oversampling AD converter 7 outputs the result of the AD conversion process as an AD output signal.
[0089]
As described above, the AD converter 9 of the present invention shown in FIG. 1 (a) uses the oversampling clock d for controlling the oversampling AD converter 7 for a predetermined period excluding the stable reading period T4 from the end of the charge reading period. By operating the over-sampling AD converter 7 in the ON state in T3, it is possible to prevent the substrate noise from being mixed into the input portion of the charge detection circuit 10, which is most affected by the substrate noise, and to obtain a highly accurate signal charge. Reading is realized, and high-speed reading is also possible.
[0090]
FIG. 2A is a block diagram showing a configuration of an X-ray sensor signal conversion circuit using the AD converter of the present invention and an X-ray sensor that outputs signal charges to the X-ray sensor signal conversion circuit, and FIG. 4) is a timing chart of each signal in the X-ray sensor signal conversion circuit at the time of signal reading. Here, the timing chart shown in FIG. 2B is different from the timing chart shown in FIG. 10B in that an operation period (period T3) of the oversampling clock d and a period T4 after the end of the period T3 are provided. Are different, and others are the same.
[0091]
The X-ray sensor signal conversion circuit 37 shown in FIG. 2A has a multi-series AD conversion device including the charge detection circuit 10, the amplification circuit 11 including the low-pass filter circuit, the sample-and-hold circuit 6, and the oversampling AD converter 7. A latch circuit 12 that is arranged on the same semiconductor substrate and latches an output signal that has been subjected to AD conversion processing by the oversampling AD converter 7, and a multi-series AD output processing signal that has been latched by the latch circuit 12. And a multi-channel AD converter provided with a multiplexer 13 for switching and outputting the data in a time division manner and a buffer 14 for output data.
[0092]
The signal charge generated by the X-ray sensor 36 is input to the charge detection circuit 10 of the AD converter of each channel of the X-ray sensor signal conversion circuit 37. Here, in the X-ray sensor 36, the charge generation circuit 8 having the TFT and the X-ray conversion element shown in the X-ray sensor pixel unit 18 in FIG. 7 is arranged in a matrix like the sensor screen 16 shown in FIG. .
[0093]
The first reset clock b for controlling the charge detection circuit 10, the sample and hold clock c for controlling the sample and hold circuit 6, and the oversampling clock d for controlling the oversampling AD converter 7 are supplied from independent terminals. It has become.
[0094]
A basic timing chart of each signal such as the first reset clock b, the sample hold clock c, and the oversampling clock d is as shown in FIG. That is, the TFT gate clock a, which is the charge read clock of the charge generation circuit 8 in the X-ray sensor 36, is turned on, and the TFT gate clock a turns the TFT on during the periods T3 and T3 in the period T4. As in the timing chart shown in FIG. 1B, the operation is performed with the oversampling clock d turned on. Since the first reset clock b, the sample hold clock c, and the oversampling clock d are supplied from independent terminals, the timing of each clock pulse can be adjusted. As an X-ray sensor system, signal charge conversion is performed. The optimum timing of high precision and high speed processing can be determined while evaluating the image in terms of precision, conversion speed, and the like.
[0095]
Specifically, an FPGA (Field Programmable Gate Array) chip (not shown) is arranged for generating a control clock of the X-ray sensor module having the X-ray sensor 36 and the X-ray sensor signal conversion circuit 37, and these chips are programmably arranged. The timing of clock pulses such as 1 reset clock b, sample hold clock c, and oversampling clock d is adjusted. The TFT gate clock a, the first reset clock b, the sample and hold clock c, and the oversampling clock d are set so that they can be controlled independently.
[0096]
Next, an amplifier circuit 11 including a low-pass filter circuit for removing noise is arranged between the charge detection circuit 10 and the sample-and-hold circuit 6. The amplifier circuit 11 may be provided with an operational amplifier 133, a feedback capacitor 132, and a reset switch 131 (not shown) as in the amplifier circuit 110 shown in FIG. The amplifier circuit 11 is reset at the time of the operation of the second reset clock f, similarly to the amplifier circuit 110. The second reset clock f is controlled independently similarly to other clock signals. The amplifying circuit 11 effectively increases the dynamic range of the oversampling clock AD converter 7 when the amount of signal charge from the charge generation circuit 8 of the X-ray sensor 36 is extremely small, and thus the output voltage of the charge detection circuit 10 is small. It is provided to amplify the signal voltage up to a usable voltage range. The low-pass filter included in the amplifier circuit 11 can remove low-frequency noise from the X-ray sensor 36 by the correlated double sampling method and can remove thermal noise from the X-ray sensor 36, and can read signal charges. High accuracy can be achieved. This operation is the same as that described with reference to FIG.
[0097]
An A / D converter having a charge detection circuit 10, an amplifying circuit 11 including a low-pass filter circuit, a sample-and-hold circuit 6, and an oversampling A / D converter 7 is arranged in multiple lines on the same semiconductor substrate. 7, a latch circuit 12 for latching the output signal subjected to the AD conversion processing, a multiplexer 13 for switching and outputting the multi-series AD converted output signal latched by the latch circuit 12 in a time division manner, and output data. The provision of the buffer 14 constitutes the above-described multi-channel AD converter.
[0098]
Such a multi-channel A / D converter of the present invention receives output charges (signal charges) from a 9-inch panel of an X-ray sensor having a high number of pixels (2880 × 2880) through each data line, and outputs each output charge. In this case, high-precision AD conversion processing can be simultaneously performed by using 24 chips. That is, in this embodiment, it is assumed that 128 channels are built in one chip.
[0099]
Next, the AD output read clock g, which is a read clock obtained as a result of the AD conversion processing supplied to the output multiplexer 13 and the output data buffer 14, is also used for the charge read period of the charge generation circuit 8 of the external X-ray sensor 36. Is turned on only during the period T3 included in the operation. The buffer 14 for outputting the A / D converted data subjected to the A / D conversion processing by the oversampling A / D converter 7 to the outside of the chip needs to be transferred to another signal processing chip (not shown). High performance transistors are used.
[0100]
In this case, as in the A / D digital section 35 of the oversampling AD converter 70 shown in FIG. Therefore, the AD output read clock g is also operated only during the period T3 included in the charge read period of the external charge generation circuit 8, so that the frequency of the AD output read clock g is slightly increased, and one cycle of signal read is performed. The period can be maintained as it is, and high-precision and high-speed reading of signal charges can be performed.
[0101]
In the flat X-ray image sensor module having the X-ray sensor signal conversion circuit 37 and the X-ray sensor 36 provided with the above-described multi-channel AD conversion device of the present invention, the multi-channel signals are AD-converted at high speed and with high accuracy. Therefore, highly accurate moving image shooting can be realized. Specifically, as shown in FIG. 5, a sensor screen 16 of an X-ray sensor panel of 2880 × 2880 pixels, a signal conversion circuit unit 17 provided with 24 multi-channel AD converters each having 128 channels, The gate driver circuit unit 15 and the control unit (FPGA) that generates the control clock as described above enable high-precision moving image shooting at 30 frames / sec.
[0102]
FIG. 3 is a flowchart of the AD conversion device, the multi-channel AD conversion device, and the AD conversion control method of the X-ray sensor module of the present invention.
[0103]
First, the read switch 2 is turned off by the charge read clock a (or the TFT gate clock a) in the off state, and the reset switch b of the charge detection circuit 10 is turned on by turning on the reset clock b (first reset clock b). 3 is turned on, and the output signal level of the charge detection circuit 10 is reset. That is, the inverting input terminal, the non-inverting input terminal, and the output terminal of the operational amplifier circuit 5 of the charge detection circuit 10 and the data line connected to the charge generation circuit 8 (or the X-ray sensor 36) are all reset to the reference voltage Vr. (Initialization) (Step S1). Here, when the amplifier circuit 11 is provided between the charge detection circuit 10 and the sample hold circuit 6, the reset switch of the amplifier circuit 11 is turned on by the second reset clock f which is on in step S1. To initialize as in the case of the charge detection circuit 10. In step S1, the oversampling clock d for controlling the oversampling A / D converter 7 is stopped.
[0104]
Next, the charge read clock a (or the TFT gate clock a) is turned on, the read switch 2 is turned on by the charge read clock a (or the TFT gate clock a), and the charge generation circuit 8 (or the X-ray sensor 36) The signal charges stored in the memory are read out to the sample and hold circuit via the data line, the charge detection circuit 10, and the like (step S2). In this case, the reset clocks (or the first reset clock 1 and the second reset clock) are in an off state, and the charge detection circuit 10 and the amplification circuit 11 start operating from the time when the read switch 2 is turned on. , The oversampling clock d is activated, and the oversampling AD converter 7 performs an AD conversion process.
[0105]
Next, when the AD conversion processing for the number of clocks within the predetermined period of the predetermined oversampling clock d is completed, the oversampling clock d is stopped, the AD conversion processing result is determined, and the AD converter output signal is output. (Step S3).
[0106]
Next, after the charge generation circuit 8 (or the X-ray sensor 36) secures a feed-through noise removal period after the predetermined charge read clock a (or the TFT gate clock a) is turned off (step S4). Then, the sample hold clock c is turned on, and the output signal from the charge detection circuit 10 is held in the sample hold circuit 6 by the sample hold clock c (step S5). At this time, the sample and hold circuit 6 samples the output signal level of the sample and hold circuit by the sample and hold clock c for a signal to be A / D converted during the next signal read period, and outputs the signal level of the sample and hold circuit until the next signal read cycle. Hold.
[0107]
Further, in the multi-channel A / D converter and the X-ray sensor module using the same, the A / D output signal of the multi-series oversampling A / D converter 7 latched by the latch circuit 12 by the sample and hold clock c is converted to an A / D output read clock g. Is input to the multiplexer 13 that operates based on the data, and the data is converted by the multiplexer 13 into data selected in a time-division manner. Then, the data selected in a time-division manner is sequentially output to an external circuit via the buffer 14 operating based on the AD output read clock g, for example, AD output m-1, AD output m, and AD output m + 1. (Step S6). The steps S1 to S6 are repeated according to the required number of data.
[0108]
As is apparent from the above description, the AD converter according to the present invention is an AD converter in which a charge detection circuit, a sample hold circuit, and an oversampling AD converter are mounted on the same semiconductor substrate. By operating the oversampling clock of the oversampling AD converter only in the reading period, the influence of substrate noise on the charge detection circuit can be eliminated, and high-speed reading operation can be maintained while operating with high accuracy.
[0109]
Further, the AD converter and the multi-channel AD converter of the present invention are configured such that the reset clock of the charge detection circuit, the sampling clock of the sample and hold circuit, and the oversampling clock of the oversampling AD converter can be supplied from independent terminals. Thus, the timing of each clock can be adjusted, and a high-precision, high-speed optimal timing can be determined while evaluating an image in terms of conversion accuracy and conversion speed as a sensor system.
[0110]
Further, the AD converter and the multi-channel AD converter according to the present invention include a low-pass filter circuit for removing noise and a voltage amplifier circuit between the charge detection circuit and the sample-and-hold circuit, so that the oversampling clock can be reduced. When the influence of the substrate noise is removed by the stop state and the charge signal from the sensor is extremely small, the voltage can be amplified according to the dynamic range of the oversampling clock AD converter, and the low frequency noise from the sensor is correlated. It can be removed by the double sampling method, and the thermal noise from the sensor can be removed by a low-pass filter, and the accuracy can be improved.
[0111]
Further, the AD converter and the multi-channel AD converter according to the present invention include a charge detection circuit, a low-pass filter, an amplifier circuit, a sample-and-hold circuit, and an oversampling AD converter, which are arranged in a plurality of series on the same semiconductor substrate. By providing a multi-channel A / D converter having a multiplexer and an output data buffer for switching and outputting the output of the series A / D converter in time series, the output charge to each data line from a sensor having a large number of pixels can be increased. A / D conversion processing can be performed simultaneously with high accuracy by several chips.
[0112]
Further, according to one embodiment, the multi-channel A / D converter of the present invention provides a read clock of an A / D conversion result supplied to an output multiplexer and an output data buffer only in a charge read period of an external charge generation circuit. In this case, the effect of substrate noise can be eliminated and the accuracy can be improved.
[0113]
Furthermore, since the X-ray sensor module of the present invention uses a multi-channel AD converter capable of high-speed, high-precision AD conversion of multi-channel signals, high-precision moving image shooting can be realized.
[0114]
【The invention's effect】
An AD converter according to the present invention includes a sampling and holding circuit for sampling an output signal level from a charge detection circuit, and an AD conversion circuit for sampling and sampling the output signal level of the sampled sampling and holding circuit for AD conversion within a predetermined period. With this configuration, the effect of substrate noise can be suppressed, and a highly accurate and high-speed signal reading operation can be performed.
[Brief description of the drawings]
FIG. 1A is a block diagram showing a configuration of a main part of an AD converter according to an embodiment of the present invention and a charge generation circuit, and FIG. 1B is a block diagram of the AD converter according to the present invention at the time of signal reading. 6 is a timing chart of each signal.
FIG. 2 is a block diagram showing a configuration of an X-ray sensor signal conversion circuit and an X-ray sensor using the AD converter of the present invention, and FIG. 2 (b) is a timing of each signal in the X-ray sensor signal conversion circuit at the time of signal reading. It is a chart.
FIG. 3 is a flowchart of an AD converter, a multi-channel AD converter, and an AD conversion control method of an X-ray sensor module according to the present invention.
FIG. 4 is a block diagram showing a configuration of a conventional multi-channel AD converter.
FIG. 5 is a block diagram showing a configuration of an X-ray sensor module using a conventional multi-channel AD converter.
FIG. 6 is a circuit diagram showing a part of an X-ray conversion element constituting a sensor screen.
FIG. 7 is a circuit diagram of a signal reading section of a conventional multi-channel AD converter and an X-ray sensor pixel section of an X-ray sensor module.
FIG. 8 is a block diagram showing a configuration of an oversampling AD converter 70.
FIG. 9 is a block diagram of a reading section of output data subjected to AD conversion processing of a conventional multi-channel AD converter.
FIG. 10 is a timing chart of each signal when the conventional multi-channel AD converter operates.
[Explanation of symbols]
1 Charge retention capacity
2 Readout switch
3 Reset switch
4 Return capacity
5 Operational amplifier
6 Sample hold circuit
7 Oversampling AD converter
8 Charge generation circuit
9 AD converter
10. Charge detection circuit
11 Amplifier circuit
12 Latch
13 Multiplexer
14 buffers
36 X-ray sensor
37 X-ray sensor signal conversion circuit
a Charge read clock or TFT gate clock
b reset clock or first reset clock
c Sample hold clock
d Oversampling clock
f Second reset clock
g AD output read clock

Claims (11)

A sampling and holding circuit for sampling an output signal level from the charge detection circuit; and an AD conversion circuit for sampling and AD converting the output signal level of the sampled sampling and holding circuit for AD conversion within a predetermined period. A / D converter. The charge detection circuit is reset by a reset clock, the sample and hold circuit is controlled in sampling operation by a sampling and holding clock, and the A / D conversion circuit is controlled in an A / D conversion operation by an oversampling clock.
The oversampling clock is controlled so that the charge detection circuit performs a sampling operation within the predetermined period excluding a stable readout period from a terminal end of a charge readout period for reading out signal charges from an external charge generation circuit. 2. The AD converter according to claim 1, wherein AD conversion is performed on the output signal level of the sampling and holding circuit sampled by the clock. The AD converter according to claim 2, wherein the reset clock, the sampling hold clock, and the oversampling clock can be independently controlled. 3. The A / D converter according to claim 2, wherein an amplification circuit including a low-pass filter is provided between the charge detection circuit and the sample hold circuit, and the amplification circuit is reset by a reset clock, and the reset clock is independently controllable. apparatus. 5. The AD converter according to claim 1, which is arranged for each channel, each AD converter, each latch circuit for latching an AD output signal of each AD converter, A multi-channel AD converter in which a multiplexer for selectively outputting each output signal from each latch circuit in a time-division manner and a buffer for driving the output signal of the multiplexer are provided on the same semiconductor substrate. An X-ray sensor module provided with an X-ray sensor and the multi-channel AD converter according to claim 6, wherein an output signal of the X-ray sensor is input to the charge detection circuit. The X-ray sensor includes an X-ray conversion element, a charge storage capacitor for holding the charge generated by the X-ray conversion element, and a switch circuit for controlling the output of the charge stored in the charge storage capacitor. The X-ray sensor module according to claim 6, wherein a plurality of pixel units are arranged. The X-ray sensor module according to claim 7, wherein a charge readout clock for controlling on / off operation of the switch circuit can be independently controlled. A first step of resetting an output signal level of the charge detection circuit by a reset signal;
A second step of reading the signal charge from the external charge generation circuit to the sample and hold circuit after the reset, turning on an oversampling clock, and performing an A / D conversion on the output signal level of the sample and hold circuit;
A third step of outputting an output signal of the AD conversion circuit after the completion of the operation of the AD conversion processing within a predetermined period of the oversampling clock;
A fourth step of providing a predetermined noise removal period in the charge generation circuit;
A fifth step of sampling the output signal level of the sample and hold circuit to be A / D-converted in the next signal readout period by the sampling and holding clock, and holding the output signal level of the sample and hold circuit until the next signal readout period;
A method for controlling an AD converter having at least one cycle of each of a series of steps including: A first step of resetting an output signal level of the charge detection circuit by a reset signal;
A second step of reading the signal charge from the external charge generation circuit to the sample and hold circuit after the reset, turning on an oversampling clock, and performing an A / D conversion on the output signal level of the sample and hold circuit;
A third step of outputting an output signal of the AD conversion circuit after the completion of the operation of the AD conversion processing within a predetermined period of the oversampling clock;
A fourth step of providing a predetermined noise removal period in the charge generation circuit;
The sampling and holding clock samples the output signal level of the sample and hold circuit to be A / D-converted in the next signal readout period, holds the output signal level of the sample and hold circuit until the next signal readout period, and causes the latch circuit to perform the AD conversion. A fifth step of latching the output signal of the circuit;
A sixth step of selecting an A / D conversion circuit output signal of the A / D conversion circuit latched by the latch circuit in a time division manner by a multiplexer controlled by an A / D output read clock, and outputting the selected signal to an external circuit via a buffer;
A method for controlling a multi-channel AD converter having at least one cycle of each series of steps including: A first step of resetting an output signal level of the charge detection circuit by a reset signal;
A second step of reading signal charges from the X-ray sensor to the sample and hold circuit after the reset, turning on an oversampling clock, and performing an AD conversion process on an output signal level of the sample and hold circuit;
A third step of outputting an output signal of the AD conversion circuit after the completion of the operation of the AD conversion processing within a predetermined period of the oversampling clock;
A fourth step of providing the X sensor with a predetermined noise removal period;
The sampling and holding clock samples the output signal level of the sample and hold circuit to be A / D-converted in the next signal readout period, holds the output signal level of the sample and hold circuit until the next signal readout period, and causes the latch circuit to perform the AD conversion. A fifth step of latching the output signal of the circuit;
A sixth step of selecting an A / D conversion circuit output signal of the A / D conversion circuit latched by the latch circuit in a time division manner by a multiplexer controlled by an A / D output read clock, and outputting the selected signal to an external circuit via a buffer;
A method for controlling an X-ray sensor module having at least one cycle of a series of steps including:

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