JP2004118419A - Semiconductor device, microcomputer, electronic device, control method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication control circuit capable of fetching a status in a communication control circuit for receiving data having a frame configuration of HDLC (High-level Data Link Control) procedure and transferring them in DMA method, a communication control device, a microcomputer, and electronic equipment. <P>SOLUTION: This communication control circuit 100 has a received data buffer 110 for storing received data 160 by first-in, first-out; a status generation circuit 140 for generating the status of the received data; a status buffer 120 for synchronously performing input and output with the same stage number as the received data buffer 110; a status retaining register 190; a control circuit 180 for outputting a DMA request signal, an interruption signal, and a switching control signal after final data reading; and a selector circuit 130 for accepting the output from the received data buffer and the output from the status buffer and selectively outputting either one of these data based on the switching control signal. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a communication control circuit, a communication control device, a microcomputer, and an electronic device.
[0002]
[Background Art]
The communication control device performs bit error detection on the received data in accordance with the HDLC procedure, and generates a status for each byte based on the detection result. The side that processes the received data (for example, the CPU) can determine whether the data is correctly transferred by checking this status.
[0003]
Here, the status generated corresponding to the final data of the flag check sequence of the received data is a status that can determine whether the entire received data is correctly transferred.
[0004]
However, in the conventional hardware configuration, since the DMA transfer is given priority over the data end interrupt processing for notifying the end of data reception, a data end interrupt is performed after reading the last data. In such a case, it is difficult to retrieve the status corresponding to the final data because the status is not guaranteed.
[0005]
[Patent Document 1] Japanese Patent Application Laid-Open No. 01-73944 [Patent Document 2] Japanese Patent No. 2766309 [Patent Document 3] Japanese Patent Application Laid-Open No. 03-11848 [0006]
[Problems to be solved by the invention]
As the processing of such status, the following method has been conventionally proposed.
[0007]
Japanese Patent Application Publication No. 0520905 and Japanese Patent Application Laid-Open No. 01-73944 propose a method of DMA-transmitting the status together with the received data at the time of data reception. However, since the status is read every time, there is a problem that the bus occupation time of the DMA transfer every time becomes long and the capacity of the buffer of the DMA transfer destination also becomes large.
[0008]
Japanese Patent Application Publication No. 02763009 proposes a method in which when the end of a frame is recognized, DMA transfer is masked by a final data interrupt signal, interrupt processing is performed first, and status is read. However, in order to read the status in the interrupt processing, if there is another interrupt with a higher priority, the processing is delayed, and there is a possibility that the received data overrun occurs. If the frame size cannot be specified, it is necessary to read not only the status but also the final data, and to set the DMA controller by judging whether the flag sequence is shared with the subsequent frame. If it is assumed that other interrupts occur at the same time, it is considered that the influence on the received data overrun is great.
[0009]
Both JP-A-02-224542 and JP-A-03-11848 incorporate a DMA function in a communication control unit. The former sets the transfer data number + 1 in the transfer data number setting register, and the latter sets the maximum number that can be set in the transfer data number setting register, corresponding to an arbitrary data length. In both cases, the status is added at the end and transferred. The DMA trigger for the status transfer is the former when the set value of the transfer data number setting register becomes “1”, and the latter when the end interrupt is generated by detecting the end flag. The status is read out by the DMA operation. However, since the communication control device itself has a DMA, if a plurality of channels are provided, arbitration of the right to use the bus for the number of channels occurs, and in some cases, this load affects the bus cycle. There is a problem that there is a possibility. Also, since there is no buffer to save the status, if the data of the next frame is received after the transfer of the received data and before the transfer of the status, the status to be transferred will be lost. There is a problem that the probability of an error increases.
[0010]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a communication control circuit that receives data having a frame configuration of an HDLC procedure and transfers the data in a DMA system. An object of the present invention is to provide a communication control circuit, a communication control device, a microcomputer, and an electronic device that can be taken out.
[0011]
[Means for Solving the Problems]
(1) The present invention is a communication control circuit that receives data having a frame configuration of an HDLC procedure and transfers the data by a DMA method.
A reception data buffer for storing reception data on a first-in first-out basis;
A status generation circuit that performs a bit error detection on the received data for each predetermined bit and generates a status;
A status buffer that has the same number of stages as the reception data buffer and is controlled so that input / output is performed in synchronization with the reception data buffer, and stores the output from the status generation circuit on a first-in first-out basis;
A status holding register for holding one stage of output from the status buffer;
A control circuit that outputs a switching control signal to the selector circuit after the end of the final data read, and that outputs a DAM request signal for transferring the output of the selector circuit by the DMA method;
A selector circuit that receives an output from the reception data buffer and an output from the status buffer, and selects and outputs any data based on the switching control signal;
It is characterized by including.
[0012]
The HDLC procedure means a high level data link control procedure. The transfer data size of the received data may be a fixed length or a variable length.
[0013]
The end of the final data reading may be detected by, for example, a reception end interrupt generated in the process of the data reception end processing of the communication control circuit, or, for example, when the reception data has a fixed length, the fixed data length and the reception The end of the final data reading may be detected by comparing the data count values.
[0014]
According to the present invention, the reception data buffer and the status buffer have the same number of stages, and input and output are performed synchronously. Therefore, when the final data of the frame is output from the reception data buffer, the reception data buffer and the status buffer correspond to the final data of the frame. The status is output from the status buffer to the status holding register. Thereafter, the output of the value of the status holding register is selected by the selector circuit, the DMA request signal is output, and the status is transferred.
[0015]
As described above, according to the present invention, since the status corresponding to the final data can be DMA-transferred after the reading of the final data, the communication control circuit which receives the data having the frame structure of the HDLC procedure and transfers the data by the DMA method is used. Even in a hardware configuration in which DMA transfer is prioritized over data end interrupt processing for notifying the end of data reception, a status corresponding to final data can be obtained.
[0016]
The present invention is applicable even when the frame size is unknown.
[0017]
Further, according to the present invention, the status corresponding to the final data can be obtained without increasing the bus occupancy or the DMA transfer area, and without requiring extra program control.
[0018]
(2) The communication control device of the present invention
The control circuit includes:
A circuit for asserting the generated reception end interrupt after reading the last data,
A DAM request signal for generating a DAM request signal based on at least one of a reception data enable interrupt and an asserted reception end interrupt, and
Before the end of the reading of the final data, a DAM request signal is generated based on the reception data enable interrupt, and after the end of the reading of the final data, the DAM request signal is generated based on the asserted reception end interrupt.
[0019]
(3) The communication control device of the present invention
The control circuit includes:
A termination interrupt signal is output after a DMA request for status register transfer is generated.
[0020]
The output interrupt signal is input to, for example, an interrupt controller.
[0021]
(4) A communication control device according to the present invention includes any one of the communication control circuits described above.
[0022]
(5) A microcomputer according to the present invention includes any one of the communication control circuits described above.
[0023]
(6) The electronic device of the present invention includes the microcomputer described above,
Input means for data to be processed by the microcomputer,
Output means for outputting data processed by the microcomputer.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
1. Communication Control Circuit Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the drawings.
[0025]
The present embodiment relates to a communication control circuit that receives data having a frame configuration of the HDLC procedure and transfers the data using a DMA method.
[0026]
The frames of the HDLC procedure include an information (I) frame that is a frame for transmitting information, a monitoring (S) frame that is a frame for monitoring and controlling a data link, and a request and a response for mode setting. There is an unnumbered (U) frame, which is a frame for reporting the number.
[0027]
FIG. 1 is a diagram for describing a frame configuration (information (I) frame) of the HDLC procedure.
[0028]
The information (I) frame 10 includes a flag sequence (F) 11, an address field (A) 12, a control field (C) 13, an information data part (I) 14, a frame check sequence (FCS) 15, and a flag sequence 16. Including.
[0029]
The flag sequence (F) 11 indicates the start of a frame, and stores a start flag '7E' (hexadecimal).
[0030]
The address field (A) 12 is an identification code of the secondary station (composite station). In the case of a command, the identification code of the station to be received is stored. In the case of a response, the identification code of the transmitting station is stored. .
[0031]
The control field (C) 13 stores data indicating the type of frame (whether the frame is an information frame (I), a monitoring (S) frame, or an unnumbered (U) frame).
[0032]
The information data section (I) 14 is a section where user data is placed, and there is no limitation on the bit configuration and bit length, but agreement between the transmitting and receiving stations is required.
[0033]
The frame check sequence (FCS) 15 is a field for error control, and stores a 16-bit sequence.
[0034]
The flag sequence (F) 16 indicates the end of the frame, and stores an end flag '7E' (hexadecimal).
[0035]
FIG. 2 is a diagram for describing the configuration of the communication control circuit according to the present embodiment.
[0036]
The communication control circuit 100 is a communication control circuit that receives the serial data 160 having the frame configuration of the HDLC procedure and transfers the parallel data 151 converted by the serial-parallel conversion unit 150 by the DMA method. , A status generation circuit 140, a status buffer 120, a status holding register 190, a control circuit 180, and a selector circuit 130.
[0037]
The reception data buffer 110 stores the parallel data 151 on a first-in first-out basis.
[0038]
The status generation circuit 140 performs a bit error detection on the parallel data 151 for each predetermined bit, and generates a status.
[0039]
The status holding register 190 has the same number of stages as the reception data buffer 110 and is controlled so that input / output is performed in synchronization with the reception data buffer 110, and stores the output from the status generation circuit 140 on a first-in first-out basis.
[0040]
The status holding register 190 holds one stage of output from the status buffer 120.
[0041]
The control circuit 180 includes a reception end interrupt assertion circuit 182, a DMA request signal generation circuit 184, a switching control signal generation circuit 186, and an interrupt signal generation circuit 188. The switching control signal generation circuit 186 outputs a switching control signal 187 to the selector circuit 130 after the end of the final data reading. The DMA request signal generation circuit 184 outputs a DAM request signal 185 for transferring the output of the selector circuit 140 by the DMA method.
[0042]
Further, the reception end interrupt asserting circuit 182 asserts the generated reception end interrupt after reading the final data, and the DMA request signal generation circuit 184 generates a DAM request based on at least one of the reception data enable interrupt and the asserted reception end interrupt. A DAM request signal for generating the signal 185 is generated. Before the final data reading is completed, a DAM request signal 185 is generated based on the reception data enable interrupt. After the final data reading is completed, the asserted reception end interrupt is generated. A DAM request signal 185 is generated based on this.
[0043]
Further, the interrupt signal generation circuit 188 may output the interrupt signal 189 after the transfer of the value of the status holding register 190 is completed. The output interrupt signal goes to, for example, an interrupt controller.
[0044]
The selector circuit 130 receives the output from the reception data buffer 110 and the output from the status buffer 120, selects one of the data based on the switching control signal 186, and outputs it to the bus 170.
[0045]
Further, the reception data buffer 110 is configured as a FIFO that can be input and output on a first-in first-out basis, for example, for each byte.
[0046]
The status generation circuit 140 performs a CRC check using a frame check sequence (FCS) (see 15 in FIG. 1) as bit error detection.
[0047]
The end of the final data reading may be detected by, for example, a reception end interrupt generated in the process of the data reception end processing of the communication control circuit, or, for example, when the reception data has a fixed length, the fixed data length and the reception The end of the final data reading may be detected by comparing the data count values.
[0048]
According to the present invention, since the reception data buffer 110 and the status buffer 120 have the same number of stages and perform input / output in synchronization, when the final data of the frame is output from the reception data buffer 110, the final data of the frame is output. Is output from the status buffer 120 to the status holding register 190. Thereafter, the output of the value of the status holding register 120 is selected by the selector circuit 130 and output to the bus, and the DMA request signal 185 is output.
[0049]
As described above, according to the present invention, since the status corresponding to the final data can be DMA-transferred after the reading of the final data, the communication control circuit which receives the data having the frame structure of the HDLC procedure and transfers the data by the DMA method is used. Even in a hardware configuration in which DMA transfer is prioritized over data end interrupt processing for notifying the end of data reception, a status corresponding to final data can be obtained.
[0050]
The present invention is applicable even when the frame size is unknown.
[0051]
Further, according to the present invention, the status corresponding to the final data can be obtained without increasing the bus occupancy or the DMA transfer area, and without requiring extra program control.
[0052]
FIG. 3 is an example of the configuration of the DMA request signal generation circuit.
[0053]
As shown in the figure, the DMA request generation circuit 184 can be configured as an OR circuit that inputs the reception data enable interrupt 212 and the reception end interrupt 214 and outputs the DMA request signal 184. The reception data enable interrupt 212 is generated in the communication control circuit, for example, as one of data reception processing, and the reception end interrupt 214 is generated in the communication control circuit, for example, as one of data reception end processing. Can be used.
[0054]
This makes it possible to generate a DMA request with a simple configuration using an interrupt signal.
[0055]
FIG. 4 is a diagram for explaining the relationship between the function and operation of the interrupt signal in the communication control circuit.
[0056]
In the reception operation of the communication control device according to the present embodiment, three types of interrupts, that is, a reception data enable, a reception data overrun error, and a reception end interrupt occur. The reception data enable is an interrupt notifying that data has been received. A receive data overrun error is an interrupt that indicates that data has been overwritten, and occurs when the next data is received without reading data even when the receive buffer is full. At this time, the operation fails. The reception end interrupt is an interrupt notifying the end of reception.
[0057]
In this communication control circuit, the received data enable is used as a request signal to the DMA controller, and the received data is read out using the DMA. In this case, it is preferable to design the hardware such that the reception data enable is temporarily released together with the reading of the reception data.
[0058]
That is, when data is received as shown in S1 to S8 of FIG. 4, a reception data enable occurs. With this as a DMA request, the output from the reception data buffer is selected by the selector circuit, and the reception data is transferred by DMA.
[0059]
When the last data is received (S9), a reception data enable interrupt and a reception end interrupt are generated (S10). Here, the reception end interrupt is masked until the last received data is transferred by the DAM, and becomes an asserted state after the end of reading the last data.
[0060]
Here, the control circuit outputs the switching control signal to the selector circuit after the end of the final data reading and outputs the DAM request signal for transferring the output of the selector circuit by the DMA method. The output is selected, and the status is transferred by the DMA (S11).
[0061]
FIG. 5 is an example of a semiconductor integrated circuit device (IC) including the present communication control circuit.
[0062]
The semiconductor integrated circuit device (IC) 300 includes a communication control circuit 310, an interrupt controller 320, a DMA controller 330, and a CPU 350, which are connected via an internal bus 360. The communication control circuit 310 receives the data 370 having the frame configuration of the HDLC procedure, and outputs a DMA request 312 to the DMA controller 330.
[0063]
The received data 316 read by the DMA controller 330 may be temporarily stored in the memory 340 and used by the CPU 350 or the like.
[0064]
The reception end interrupt detected by the communication control circuit 310 is output to the interrupt controller 320, and the interrupt controller issues a reception end interrupt 322 to the CPU 350.
[0065]
Although FIG. 5 illustrates the case where the communication control circuit is integrated on a single IC chip together with the CPU 350, the DMA controller 330, and the interrupt controller 320, the present invention is not limited to this. For example, the communication control circuit may be integrated on a chip for a communication control device separately from the CPU 350, the DMA controller 330, and the interrupt controller 320.
[0066]
FIG. 6 is an example of a board including the communication control device.
[0067]
The board 400 includes a communication control device 410, an interrupt controller 420, a DMA controller 430, and a CPU 450, which are connected via an external bus 460. As described above, the communication control device 410, the interrupt controller 420, the DMA controller 430, and the CPU 450 may be configured to connect separately integrated chips on a board.
[0068]
2. FIG. 7 is an example of a hardware block diagram of the microcomputer according to the present embodiment.
[0069]
The microcomputer 700 includes a CPU 510, a cache memory 520, a memory management unit (MMU) 730, an LCD controller 530, a reset circuit 540, a programmable timer 550, a real-time clock (RTC) 560, a DMA controller F570, an interrupt controller 580, and a communication control circuit. 590, a bus controller 600, an A / D converter 610, a D / A converter 620, an input port 630, an output port 640, an I / O port 650, a clock generator 560, a prescaler 570, and various buses 680 connecting them. , Various pins 690 and the like.
[0070]
Here, the communication control circuit 590 has, for example, the configuration described with reference to FIG. 2 or FIG.
[0071]
3. Electronic Device FIG. 8 shows an example of a block diagram of an electronic device of the present embodiment. The electronic device 800 includes a microcomputer (or ASIC) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, and a sound output unit 860.
[0072]
Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power supply generation unit 840 is for generating various power supplies used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, and the like) displayed by the electronic device. The sound output unit 860 is for outputting various sounds (sounds, game sounds, etc.) output from the electronic device 800, and its function can be realized by hardware such as a speaker.
[0073]
Here, the microcomputer (or ASIC) 810 has, for example, the configuration described with reference to FIG.
[0074]
FIG. 9A illustrates an example of an external view of a mobile phone 950 which is one of electronic devices. The mobile phone 950 includes a dial button 952 functioning as an input unit, an LCD 954 displaying a telephone number, a name, an icon, and the like, and a speaker 956 functioning as a sound output unit and outputting sound.
[0075]
FIG. 9B illustrates an example of an external view of a portable game device 960 which is one of the electronic devices. The portable game device 960 includes an operation button 962 functioning as an input unit, a cross key 964, an LCD 966 displaying a game image, and a speaker 968 functioning as a sound output unit and outputting game sounds.
[0076]
FIG. 9C illustrates an example of an external view of a personal computer 970 which is one of electronic devices. The personal computer 970 includes a keyboard 972 functioning as an input unit, an LCD 974 for displaying characters, numbers, graphics, and the like, and a sound output unit 976.
[0077]
Note that, as electronic devices that can use the present embodiment, in addition to those shown in FIGS. 9A, 9B, and 9C, devices including a portable information terminal, a pager, an electronic desk calculator, and a touch panel, Various electronic devices using an LCD, such as a projector, a word processor, a viewfinder type or a monitor direct-view type video tape recorder, and a car navigation device can be considered.
[0078]
The present invention is not limited to the present embodiment, and various modifications can be made within the scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a diagram for describing a frame configuration (information (I) frame) of an HDLC procedure.
FIG. 2 is a diagram for describing a configuration of a first example of the communication control circuit according to the present embodiment;
FIG. 3 is an example of a configuration of a DMA request signal generation circuit.
FIG. 4 is a diagram for explaining the relationship between the function and operation of an interrupt signal in a communication control circuit.
FIG. 5 is an example of a semiconductor integrated circuit device (IC) including the communication control circuit.
FIG. 6 is an example of a board including the communication control device.
FIG. 7 is an example of a hardware block diagram of a microcomputer of the present embodiment.
FIG. 8 illustrates an example of a block diagram of an electronic device including a microcomputer.
FIGS. 9A, 9B, and 9C are examples of external views of various electronic devices.
[Explanation of symbols]
Reference Signs List 100 communication control circuit, 110 reception data buffer, 120 status buffer, 130 selector circuit, 140 status generation circuit, 150 serial-parallel conversion unit, 151 parallel data, 160 reception data, 170 data bus, 180 control circuit, 182 reception end interrupt Assert circuit, 184 DMA request signal generation circuit, 185 DMA request signal, 186 switching control signal generation circuit, 187 switching control signal, 188 interrupt signal generation circuit, 189 interrupt signal, 190 status holding register, 210 OR circuit, 212 received data Enable interrupt, 214 reception end interrupt, 300 semiconductor integrated circuit device, 310 communication control circuit, 320 interrupt controller, 330 DMA controller 340 memory, 350 CPU, 510 CPU,
520 cache memory, 530 LCD controller, 540 reset circuit, 550 programmable timer, 560 real-time clock (RTC), 570 DMA controller, 580 interrupt controller, 590 communication control circuit, 600 bus controller, 610 A / D converter, 620 D / A converter, 630 input port, 640 output port, 650 I / O port, 660 clock generator (PLL), 670 prescaler, 680 various buses, 690 various pins, 700 microcomputer, 710 ROM, 720 RAM, 730 MMU,
800 Electronic equipment

Claims (6)

A communication control circuit for receiving data having a frame configuration of an HDLC procedure and transferring the data by a DMA method,
A reception data buffer for storing reception data on a first-in first-out basis;
A status generation circuit that performs a bit error detection on the received data for each predetermined bit, and generates a status.
A status buffer that has the same number of stages as the reception data buffer and is controlled so that input / output is performed in synchronization with the reception data buffer, and stores the output from the status generation circuit on a first-in first-out basis;
A status holding register for holding one stage of output from the status buffer;
A control circuit that outputs a switching control signal to the selector circuit after the end of the final data read, and outputs a DAM request signal for transferring the output of the selector circuit by the DMA method;
A selector circuit that receives an output from the reception data buffer and an output from the status buffer, and selects and outputs any data based on the switching control signal;
A communication control circuit characterized by including: In claim 1,
The control circuit includes:
A circuit for asserting the generated reception end interrupt after reading the last data,
A DAM request signal for generating a DAM request signal based on at least one of a reception data enable interrupt and an asserted reception end interrupt, and
A communication control device for generating a DAM request signal based on a reception data enable interrupt before the end of the reading of the final data, and generating a DAM request signal based on the asserted reception end interrupt after the completion of the reading of the final data . In any one of claims 1 and 2,
The control circuit includes:
A communication control device for outputting an interrupt signal after completion of transfer of a value of a status holding register. A communication control device comprising the communication control circuit according to claim 1. A microcomputer including the communication control circuit according to claim 1. A microcomputer according to claim 5,
Input means for data to be processed by the microcomputer,
Output means for outputting data processed by the microcomputer.

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