JP2004119659A - Method for manufacturing semiconductor device - Google Patents

Abstract

Provided is a method for manufacturing a semiconductor device having a through conductor, in which a photolithography process is reduced.
A method of manufacturing a semiconductor device includes: (a) grinding a back surface of a semiconductor substrate having an element layer including a large number of semiconductor elements formed on a main surface of a semiconductor support substrate to reduce the thickness to 100 μm or less; b) positioning and supporting the thinned semiconductor substrate on a support having a smooth surface, and forming a via hole penetrating the semiconductor substrate; and (c) on a first support having a smooth surface. Forming a via hole that penetrates the semiconductor support substrate by positioning and supporting the same, and (d) forming a metal layer in the via hole on which the insulating film is deposited.
[Selection diagram] FIG.

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a through conductor suitable for forming a three-dimensional stack by stacking a plurality of semiconductor devices.
[0002]
[Prior art]
By stacking semiconductor chips on which a large-scale integrated circuit (LSI) is formed, the number of elements in the same occupied area can be dramatically increased. In order to realize the electrical connection between the stacked semiconductor chips without passing through the wiring on the circuit board, it is desirable to form a through conductor penetrating the semiconductor substrate.
[0003]
When a wiring layer is formed on a semiconductor substrate, the wiring layer may extend in a lateral direction. Such a case is also called a through conductor. That is, in this specification, a through conductor refers to a conductor that is connected from one surface of a semiconductor substrate to another surface without passing through wiring outside the semiconductor substrate.
[0004]
To form a through conductor in an LSI chip, a via hole is formed by wet etching, reactive ion etching (RIE) or laser, and the via hole is insulated, and then the via hole is filled with metal. If necessary, in-plane wiring and solder bumps are also formed.
[0005]
The semiconductor substrate usually has a thickness of 600 to 700 μm. However, the region constituting the semiconductor element is often a region having a thickness of only 2 to 3 μm near the main surface, and the other thickness portions only function as a physical support substrate. When it is desired to reduce the volume of a semiconductor chip, particularly when a plurality of semiconductor chips are stacked, it is desired that the semiconductor substrate be ground and thinned.
[0006]
When a through conductor is formed in an LSI chip, a via hole is formed, an inner surface of the via hole is insulated, a metal is filled in the via hole by plating or the like, and then a silicon substrate is ground from the back surface of the wafer to form a damaged layer on the surface. A method of removing the metal by dry etching to expose the metal at the tip of the via to form a through via is often used.
[0007]
However, it is not easy to grind the substrate thinly after filling the via holes with metal. Further, when the grinding step is performed, the back surface of the substrate is directly exposed, so that it is necessary to prevent a short circuit between the conductor in the via hole and the back surface of the substrate. For this purpose, an insulating layer must be formed on the back surface of the silicon substrate, and an opening for exposing the via conductor must be provided. Because of these steps, a plurality of resist processes were required to form a via conductor.
[0008]
[Patent Document 1]
JP-A-59-4174
[0009]
[Problems to be solved by the invention]
As described above, it is not easy to form a through conductor on an LSI chip.
[0010]
An object of the present invention is to provide a method of manufacturing a semiconductor device having a through conductor with reduced complexity and difficulty in the manufacturing process.
It is another object of the present invention to provide a method of manufacturing a semiconductor device having a through conductor, in which a photolithography process is reduced.
[0011]
Still another object of the present invention is to provide a method of manufacturing a semiconductor device which can be easily and reliably implemented.
[0012]
[Means for Solving the Problems]
According to one aspect of the present invention, a) a step of grinding the back surface of a semiconductor substrate in which an element layer including a large number of semiconductor elements is formed on a main surface of a semiconductor support substrate to reduce the thickness, and (b) the thinned semiconductor A step of positioning and supporting the substrate on a first support having a smooth surface and forming a via hole penetrating the semiconductor support substrate; and (c) forming a via hole on the second support having a smooth surface. Positioning and supporting an element layer of the semiconductor substrate in which the via hole is formed, and depositing an insulating film on the inner surface of the via hole and around the via hole on the back surface of the semiconductor substrate; and (d) depositing the insulating film. Forming a metal layer in the formed via hole.
[0013]
Instead of grinding the silicon substrate after forming the via conductor, the via conductor is formed after grinding the silicon substrate.
Many processes can be performed collectively at the wafer level, and a semiconductor device having a through conductor can be manufactured efficiently.
[0014]
Once the wafer is thinned, the self-preservation ability of the wafer is lost, but by using an appropriate support, the wafer can be properly handled.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
[0016]
FIG. 1A shows a plan view of the wafer. Wafer WF defines a plurality of chip regions CH in its main surface. A large number of semiconductor elements are formed in each chip area CH to constitute an LSI circuit. The wafer WF has a diameter of, for example, 10 inches to 12 inches, and the chip CH has a size of several mm to a few cm, for example, about 1 cm × 1 cm.
[0017]
FIG. 1B schematically shows a configuration of a semiconductor chip on which an LSI structure is formed. For example, a trench is formed in a surface layer of a p-type silicon substrate 1, an insulating film is buried, and a shallow trench isolation (STI) 2 is formed. The STI is an element isolation region and defines an active region. An impurity is added to the surface layer of the silicon substrate 1 to form an n-type well 3n and p-type wells 3p and 4p.
[0018]
The illustrated configuration is an LSI including a memory, in which a memory element is formed in a p-type well 4p in a memory area, and a CMOS circuit is formed in an n-type well 3n and a p-type well 3p in a peripheral area.
[0019]
An insulated gate electrode 5 is formed on the silicon substrate surface in the active region defined by STI2. Source / drain regions 6 are formed on both sides of the insulated gate electrode 5. In the peripheral circuit region, after the insulated gate electrode 5 is formed, the extension region is ion-implanted, the side wall spacer is formed, and the high concentration source / drain region is formed. Is formed.
[0020]
In the memory region, the source / drain regions 6 are formed only by low-concentration ion implantation without performing high-concentration ion implantation in order to improve retention characteristics.
[0021]
A first interlayer insulating film 7 is formed to cover gate electrode 5. The first interlayer insulating film 7 is formed of, for example, a single-layer silicon oxide layer or an insulating laminate of a silicon nitride layer / a silicon oxide layer / a silicon nitride layer. A contact hole penetrating the first interlayer insulating film 7 and reaching the source / drain region 6 in the peripheral circuit region is formed, a conductor such as tungsten is buried, and a conductor plug 8 is formed.
[0022]
A first wiring layer 10 is formed on the first interlayer insulating film 7, and necessary wiring for the conductor plug 8 is provided. A second interlayer insulating film 11 is formed so as to fill the first wiring layer 10. A wiring 12 having a damascene structure is formed in the second interlayer insulating film 11. Further, a contact hole penetrating the second interlayer insulating film 11 and the first interlayer insulating film 7 is formed, a contact hole reaching one of the source / drain regions of the memory cell is formed, and the conductor plug 13 is buried. .
[0023]
In the memory area, a capacitor 15 including a lower electrode, a dielectric layer, and an upper electrode is formed on the surface of the second interlayer insulating film 11. When the dielectric layer is formed of a ferroelectric, a ferroelectric capacitor 15 is formed.
[0024]
A third interlayer insulating film 17 including a cap layer is formed by burying the capacitor 15. Second wiring layers 18 and 19 having a damascene structure are formed in the third interlayer insulating film 17. The number of wiring layers can be increased or decreased as necessary. Other circuit elements such as resistors and inductors can be made.
[0025]
As described above, in each of the LSI chips CH, a semiconductor element such as a MOS transistor and a passive element such as a capacitor are formed above a region near the main surface of the semiconductor substrate 1.
[0026]
A layer above the STI 2 and the well 3 formed in the semiconductor substrate 1 is called an element layer because circuit elements are formed, and a layer 9 below these layers is used to support the element layer. It is referred to as a support substrate 9 because it is only used for The thickness of the supporting substrate 9 is arbitrary as long as the supporting substrate 9 can function to support the element layer 20.
[0027]
FIG. 1C schematically shows a cross-sectional configuration of a silicon wafer. The element layer 20 is formed above the surface region of the silicon wafer, and the support substrate 9 is disposed below the element layer 20. No semiconductor element such as a transistor is formed on the support substrate 9 and functions as a physical support member. The element layer 20 includes circuit elements such as a MOS transistor, a capacitor, an inductor, a resistor, and a wiring.
[0028]
As shown in FIG. 2D, a glass substrate 31 having a smooth surface is bonded to the upper surface of the semiconductor wafer WF on which the element layer 20 is formed, via a UV (ultraviolet) tape 32. The UV tape 32 is an organic material layer that has adhesive strength and loses adhesive strength when irradiated with ultraviolet (UV) light.
[0029]
As shown in FIG. 2E, the wafer WF having the UV tape 32 and the glass plate 31 bonded on the main surface is ground from the back surface. For example, a silicon substrate having a thickness of 600 to 700 mm is ground to a thickness of 100 μm or less. A silicon substrate polished to a thickness of about 100 μm or less loses its self-holding ability.
[0030]
As shown in FIG. 2F, another glass substrate 35 having a smooth surface is bonded to the ground surface of the silicon substrate WF via a UV tape 36. The silicon wafer WF is sandwiched between the glass substrates 31 and 35 having high physical strength. Note that a support made of a material other than a glass plate may be used as long as it can function as a support having a smooth surface.
[0031]
As shown in FIG. 2G, the UV tape 32 is irradiated with ultraviolet rays through the glass substrate 31 to reduce the adhesive strength. The silicon substrate 9t shields ultraviolet rays. Therefore, the UV tape 36 between the semiconductor support substrate 9t and the glass substrate 35 is not irradiated with ultraviolet light, and the adhesive strength does not decrease. The UV tape 32 and the glass substrate 31 on the main surface of the silicon substrate WF are removed.
[0032]
As shown in FIG. 2H, while a silicon substrate WF is supported on a glass substrate 35 via a UV tape 36, a resist layer 38 is applied to the surface of the element layer 20 and cured.
[0033]
A pattern of a via hole for disposing a conductor penetrating the silicon substrate is exposed, transferred, and developed on the resist layer 38. Via patterns are formed in the resist layer 38.
[0034]
As shown in FIG. 2I, using the remaining resist pattern 38 as a mask, the element layer 20 and the semiconductor supporting substrate 9t are subjected to reactive ion etching (RIE) to form via holes. By RIE, an opening according to the opening pattern of the resist pattern 38 is formed through the element layer 20 and the semiconductor support substrate 9t.
[0035]
For example, for an inorganic insulating layer, CF ₄ -CHF ₃ SF for an etching gas containing, for example, a conductive layer such as silicon or metal. ₆ , Cl ₂ Reactive ion etching is performed using an etching gas containing the above. C ₄ F ₈ And SF ₆ Bosch method to switch between and etch, SF ₆ + O ₂ May be performed.
[0036]
The taper etching may be performed by controlling the RIE process parameters. When the taper etching is performed, a via hole whose diameter decreases with the depth is formed.
[0037]
FIG. 3J shows the silicon substrate WF with the resist pattern 38 removed. A through hole is formed in the silicon substrate WF. Note that this state is fictitious, and in reality, a support structure S such as a glass plate and a UV tape is left on the upper or lower surface of the silicon substrate WF.
[0038]
As shown in FIG. 3K, a support 40 having a smooth surface made of a magnetic metal plate such as Fe, Ni, or Co is disposed on the surface of the silicon substrate WF supported by the support structure S. After disposing the support base 40, the support structure S is removed, and instead, a magnet 41 such as an alnico-based or samarium-based magnet is disposed. These magnets retain their magnetic properties up to relatively high temperatures. When the magnet 41 is attracted to the magnetic support 40, the silicon substrate WF is brought into close contact with the support substrate 40.
[0039]
In this state, an insulating layer is formed from below in the figure by chemical vapor deposition (CVD) or the like. The insulating layer is formed using an inorganic material or an organic material. Silicon oxide, silicon nitride, or the like can be used as the inorganic material. As the organic material, polyimide, polynaphthalene, parylene, or the like can be used.
[0040]
The CVD of silicon oxide can be performed by, for example, plasma CVD using TEOS or ozone. The CVD of silicon nitride can be performed, for example, by plasma CVD using ammonia and silane. Parylene is one type of fluorinated polymer and can be grown by vapor phase. Polyimide can be vapor-deposited and polymerized without dissolving the liquid, and vapor-deposited polyimide can be obtained.
[0041]
As shown in FIG. 3 (L), an insulating layer 44 is deposited on the silicon substrate WF and the magnet 41 pressed on the support 40. The insulating layer 44 also enters the gap between the silicon support substrate 9t and the support 40, and forms an insulating layer filling the gap.
[0042]
In the hole forming step in FIG. 2I, when taper etching is performed so that the opening diameter gradually narrows in the depth direction, the insulating layer 44 deposited as shown in FIG. A configuration in which an intermediate reduced-diameter portion is sandwiched between a portion expanding on the back surface and a large-diameter portion above the via hole is firmly fixed to the semiconductor substrate WF.
[0043]
After forming the insulating layer 44, the magnet 41 is removed. The insulating layer on the magnet 41 is also removed at the same time. The insulating layer deposited on the back surface of the support substrate 9t around the via hole remains, and shields the underlying silicon substrate.
[0044]
As shown in FIG. 3 (M), a support 45 having a smooth surface is prepared instead of the magnet 41, and is arranged on the lower surface of the silicon substrate WF. After supporting the silicon substrate on the support 45, the support 40 is removed.
[0045]
On the main surface of the silicon substrate WF, a stencil mask 46 having an opening pattern that conforms to the pattern of the via hole and exposes the via hole and its periphery is arranged. The stencil mask is formed of, for example, glass, plastic, or the like. The stencil mask 46 and the support table 45 are defined at desired relative positions by the jig J. In this state, a conductor such as a metal is sputtered from above the stencil mask 46. A conductor layer (metal layer) 48 is deposited on the surface of the silicon substrate WF by sputtering. The conductive (metal) material can be selected from Au, Cu, Ag, Pt, Pd, combinations thereof, and the like.
[0046]
FIG. 3 (O) shows a state of the silicon substrate after sputtering. The stencil mask 46 and the support 45 are not shown. An insulating layer 44 is formed on the inner wall of a via hole passing through the silicon support substrate 9t and the element layer 20, and a metal layer 48 is formed on the surface thereof. The metal layer 48 is exposed to the lower surface of the support substrate 9t in the via hole, and contacts the electrode region of the element layer 20.
[0047]
After the state shown in FIG. 3 (O), a resist mask may be formed as necessary, and a plating step may be performed to form a plating layer that fills a void portion of the conductor layer 48 in the through hole. In this case, the metal layer 48 functions as a seed layer for plating.
[0048]
In the embodiment described above, RIE was performed using a resist pattern formed by photolithography to form a through-hole in a silicon substrate. The through-hole may be formed by another process.
[0049]
FIG. 4A shows a case where a through hole is formed by laser irradiation. The element layer 20 is formed on the semiconductor substrate 9t. The semiconductor substrate 9t is bonded to the glass substrate 35 via the UV tape 36. The laser beam L is focused and irradiated to a desired position on the silicon substrate WF. The silicon substrate WF irradiated with the laser beam L escapes by evaporation, ablation, or the like, and a contact hole is formed.
[0050]
As a laser, a YAG laser (wavelength 532 nm, 355 nm) can be used. In addition, a Raman laser or a UV laser can be used. Laser irradiation can be performed in a CF-based gas atmosphere to prevent the deposition of flying matter.
[0051]
In the above embodiment, after the semiconductor substrate was ground, another support substrate was bonded to the ground surface, and the original support substrate was removed. The same process can be performed using the same support substrate.
[0052]
As shown in FIG. 4B, a resist pattern 38 is formed on the back surface of the silicon substrate WF supported on the glass plate 31 via the UV tape 32, and the silicon substrate 9t is etched using the resist pattern 38 as a mask. .
[0053]
As shown in FIG. 4C, after the etching of the silicon substrate WF is completed, the resist pattern 38 is isotropically etched. The resist pattern 38 recedes by isotropic etching, and recedes from the opening position of the silicon support substrate 9t. That is, the back surface of the silicon substrate 9t is exposed around the via hole.
[0054]
In this state, the insulating layer 44 is deposited from above the rear surface of the silicon substrate WF. Since the resist pattern 38 has receded, the insulating layer 44 is also extended and deposited on the back surface of the silicon substrate 9t around the opening.
[0055]
FIG. 4D is a cross-sectional view schematically showing the shape of the deposited insulating layer 44. Parts other than the silicon substrate are not shown. An insulating layer 44 is formed extending from the inner wall of the opening to the back surface of the silicon substrate 9t. After that, by performing steps as shown in FIGS. 3M and 3O, a metal wiring layer connected to the element layer 20 can be formed.
[0056]
FIG. 4E shows a state in which the conductive paste is filled into the openings by squeezing instead of sputtering in the step of FIG. 3M. Using the stencil mask 46 as a guide, the opening is filled with the conductive paste 63 using a knife edge 65 or the like. Thereafter, a conductor layer in which the openings are buried is obtained by performing curing or the like. Hereinafter, a method of manufacturing a semiconductor device according to another embodiment of the present invention will be described.
[0057]
As shown in FIG. 5A, a semiconductor substrate WF is placed on a support 50 with the element layer 20 facing down, and a stencil mask 52 made of a magnetic metal such as Fe, Co, or Ni is placed thereon. Place. A magnet 54 such as an alnico magnet or a samarium magnet is disposed below the support 50 so that the semiconductor substrate WF is in close contact with the stencil mask 53. The support base 50 is formed of a material having good heat conductivity, includes a refrigerant pipe, and can cool the semiconductor substrate WF to a desired temperature.
[0058]
As shown in FIG. 5B, the resist layer 52 is exposed through a stencil mask 53. The resist layer 52 is exposed to the same pattern as the stencil mask 53. After that, the exposed region is removed by developing the resist layer 52. The stencil mask 53 and the resist mask 52 form a laminated mask.
[0059]
As shown in FIG. 5C, the stencil mask 53 and the resist mask 52 are used as a composite mask, and the underlying silicon substrate WF is etched. For example, plasma etching using inductively coupled plasma (ICP) is performed. The flow of the coolant prevents the temperature of the substrate from rising. For example, keeping the substrate at −5 ° C. ₄ F ₈ And SF ₆ Bosch method to switch between and etch, SF ₆ + O ₂ Deep RIE is performed. The silicon substrate WF is etched to form an opening exposing the electrode (pad) P in the element layer 20.
[0060]
As shown in FIG. 5D, after the etching step is completed, the stencil mask 53 and the resist pattern 52 are removed, and the shielding area is narrower than that of the stencil mask 53 and the element layer is exposed in a wider area. The mask 55 is arranged. The insulating layer 56 is deposited via the mask 55. The insulating layer 56 is deposited on the surface of the underlying semiconductor support substrate and on the surface of the mask 55.
[0061]
FIG. 5E is a cross-sectional view near the opening. An opening is formed in the semiconductor support substrate 9t and the element layer 20, and the wiring (pad) P including the metal layer M1, the via metal V1, and the metal layer M2 is exposed in the opening. The insulating layer 56 covers the inner surface of the opening, and also covers the surface of the support substrate 9t around the opening.
[0062]
As shown in FIG. 6F, a new metal mask 58 is arranged on the back surface of the semiconductor substrate WF. The mask 58 has an opening region (window) smaller than the opening of the semiconductor substrate WF, and is arranged in alignment with the already formed opening. That is, the opening of the mask 58 has an opening at a position corresponding to the center of the previously formed opening. Anisotropic etching such as RIE is performed via the mask 58 to locally remove the insulating layer 56.
[0063]
As shown in FIG. 6G, the center of the bottom surface of the insulating layer 56 is removed by RIE through the narrow opening region, exposing the wiring P disposed in the lower layer. The opening side wall is kept covered with the insulating layer.
[0064]
Subsequently, as shown in FIG. 6H, a seed metal layer 60 is deposited. The electrode P exposed in the opening and the deposited seed metal layer 60 are electrically connected. The material for the seed metal layer is selected to be compatible with the metal to be subsequently plated. For example, the same material as the plating layer is used.
[0065]
As shown in FIG. 6I, by subsequently forming the resist layer PR, forming the plating layer 61, and the like, the plating layer 61 electrically connected to the pad P exposed in the opening is formed. .
[0066]
FIG. 7J schematically shows the configuration of the conductor stack after removing unnecessary portions of the resist mask PR and the seed layer 60 and the like.
Note that a seed metal layer was formed, a plating layer was formed, and the like in order to form a connection portion of the through conductor. The connection portion of the through conductor can be formed by another method.
[0067]
FIG. 7K shows a modification. After the step shown in FIG. 6G, the photoresist layer PR is patterned, and the opening is filled with the conductive paste layer 63 by squeezing. By removing the photoresist layer PR and performing an annealing process on the applied conductive paste layer 63, a pad layer connected to the electrode layer of the LSI circuit can be formed.
[0068]
The semiconductor device having the through conductor formed as described above can be used for various applications.
FIG. 8A shows a state in which the element layer 20 is formed on the semiconductor supporting substrate 9t, and the wiring layer 60 is formed thereon. The wiring layer 60 includes a portion of the multilayer capacitor 62 and a portion of the multilayer wiring 64, and constitutes a wiring layer together. By stacking a semiconductor chip having such a wiring layer on another semiconductor chip, a higher-performance semiconductor composite system is formed.
[0069]
FIG. 8B shows a structure in which semiconductor chips 71 to 74 constituting a memory are stacked. The circuit board 70 has a wiring layer for the semiconductor chips 71 to 74. Solder bumps 78 are formed on the lower surface of the circuit board 70, and constitute connection terminals to the outside. In the stacked semiconductor chips 71 to 74, through conductors 76 are formed, and electrical conduction between the stacked layers is formed.
[0070]
FIG. 8C illustrates a configuration example of a composite semiconductor device. For example, the imaging device 82 and the image signal processing device 84 are stacked to form a fingerprint detection circuit. This composite device is stacked on a circuit board 80 and connected to the outside by solder bumps 88. Wire bonding has also been used.
[0071]
Note that, instead of the fingerprint detection device, a normal image detection device, an image transmission device, or the like can be realized.
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, it will be apparent to those skilled in the art that various modifications, improvements, and combinations are possible.
[0072]
Hereinafter, the features of the present invention will be additionally described.
(Supplementary Note 1) (1) (a) grinding the back surface of a semiconductor substrate in which an element layer including a large number of semiconductor elements is formed on the main surface of the semiconductor support substrate to reduce the thickness;
(B) positioning and supporting the thinned semiconductor substrate on a first support having a smooth surface, and forming a via hole penetrating the semiconductor support substrate;
(C) positioning and supporting the element layer of the semiconductor substrate in which the via hole is formed on a second support having a smooth surface, and insulating the element layer on the inner surface of the via hole and around the via hole on the back surface of the semiconductor substrate; Depositing a film;
(D) forming a metal layer in the via hole on which the insulating film is deposited;
A method for manufacturing a semiconductor device including:
[0073]
(Supplementary Note 2) The manufacturing of the semiconductor device according to claim 1, wherein in the step (b), the back surface of the semiconductor substrate is arranged on the first support, and a via hole is formed from the element layer side. Method.
[0074]
(Supplementary Note 3) The method of Supplementary Note 2, wherein the step (b) forms a via hole having a tapered side surface having a large diameter on the element layer side.
(Supplementary Note 4) The method for manufacturing a semiconductor device according to Supplementary Note 1, wherein the insulating film includes an inorganic material.
[0075]
(Supplementary Note 5) The method of Supplementary Note 1, wherein the insulating film includes an organic material.
(Supplementary Note 6) The method of Supplementary Note 5, wherein the organic material includes one of polyimide, polynaphthalene, and parylene.
[0076]
(Supplementary Note 7) (3) In the step (b),
(B-1) forming a resist pattern on the element layer;
(B-2) using the resist pattern as a mask, etching the element layer and the semiconductor support substrate by reactive ion etching;
4. The method for manufacturing a semiconductor device according to supplementary note 2 or 3, further comprising:
[0077]
(Supplementary Note 8) (4) The method according to Supplementary Note 1, wherein the step (b) includes arranging the element layer on the first support base and forming a via hole from the back side of the semiconductor substrate.
[0078]
(Supplementary Note 9) (5) The step (b) is
(B-4) forming a resist pattern on the back surface of the semiconductor substrate;
(B-5) using the resist pattern as a mask, performing reactive ion etching through the semiconductor support substrate to expose an electrode layer in the element layer;
9. The method for manufacturing a semiconductor device according to supplementary note 8, comprising:
[0079]
(Supplementary Note 10) (6) In the step (b),
(B-3) a step of irradiating a laser beam to form a via hole in the semiconductor support substrate
2. The method for manufacturing a semiconductor device according to supplementary note 1, comprising:
[0080]
(Supplementary Note 11) (7) In the step (c), the second support includes a magnetic metal material, a magnet is disposed on a back surface of the semiconductor substrate, and the semiconductor substrate is connected to the second support. 11. The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 10, wherein the semiconductor device is adhered on the semiconductor device.
[0081]
(Supplementary Note 12) (8) The step (b) includes a step of forming a resist pattern on the back surface of the semiconductor substrate,
9. The method of manufacturing a semiconductor device according to claim 8, wherein in the step (c), an insulating layer is deposited by sputtering with the resist pattern left on the back surface of the semiconductor substrate, and then lift-off is performed.
[0082]
(Supplementary Note 13) (9) In the step (d),
(D-1) disposing the element layer on a third support having a smooth surface, and disposing a stencil mask on the back surface of the semiconductor substrate;
(D-2) depositing a metal layer in the opening and a part of the element layer from above the stencil mask;
13. The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 12, further comprising:
[0083]
(Supplementary note 14) The method for manufacturing a semiconductor device according to supplementary note 13, wherein the stencil mask is formed of glass or plastic.
(Supplementary Note 15) The method for manufacturing a semiconductor device according to supplementary note 13, wherein the stencil mask is formed of a magnetic metal.
[0084]
(Supplementary note 16) The method for manufacturing a semiconductor device according to supplementary note 15, wherein the magnetic metal includes any of iron, nickel, and cobalt.
(Supplementary Note 17) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 16, wherein the metal layer is formed of any one of Au, Cu, Ag, Pt, Pd, and a combination thereof.
[0085]
(Supplementary Note 18) The step (d) further comprises:
(D-4) The method for manufacturing a semiconductor device according to supplementary note 13, including a step of forming a plating layer on the metal layer.
[0086]
(Supplementary Note 19) (10) In the step (d),
(D-3) forming the metal layer by squeezing using the stencil mask as a guide;
13. The method for manufacturing a semiconductor device according to supplementary notes 1 to 12, further comprising:
[0087]
(Supplementary Note 20) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 19, further comprising a step of connecting the metal layer to an electrode of another semiconductor chip.
[0088]
【The invention's effect】
As described above, according to the present invention, there is provided a method of manufacturing a semiconductor device having a through conductor, in which steps by photolithography are reduced.
[Brief description of the drawings]
FIGS. 1A and 1B are a plan view and a sectional view showing main steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a sectional view showing main steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a sectional view showing main steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 4 is a sectional view showing a modification of the first embodiment.
FIG. 5 is a sectional view showing main steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
FIG. 6 is a sectional view showing main steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
FIG. 7 is a cross-sectional view showing main steps and a modification of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
FIG. 8 is a cross-sectional view illustrating an example of a device using a semiconductor device.
[Explanation of symbols]
1 Silicon substrate
2 Shallow trench isolation (STI)
3 wells
4 wells
5 Insulated gate electrode
6 Source / drain regions
7, 11, 17 interlayer insulating film
8, 13 Conductor plug
15 (ferroelectric) capacitors
18, 19 (dual damascene) wiring
9 Semiconductor support substrate
20 element layers
WF wafer
CH chip
31, 35 glass plate (support base)
32, 36 UV tape
38 Resist layer
40 (magnetic metal) support base
41 magnet
44 Insulation layer
48 metal layer
46 Stencil mask
63 Conductor paste
53 stencil mask
52 resist layer
54 magnet
56 insulating layer
58 Stencil Mask
60 Seed metal layer
61 plating layer

Claims (10)

(A) grinding the back surface of a semiconductor substrate in which an element layer including a large number of semiconductor elements is formed on a main surface of a semiconductor support substrate to reduce the thickness;
(B) positioning and supporting the thinned semiconductor substrate on a first support having a smooth surface, and forming a via hole penetrating the semiconductor support substrate;
(C) positioning and supporting the element layer of the semiconductor substrate in which the via hole is formed on a second support having a smooth surface, and insulating the element layer on the inner surface of the via hole and around the via hole on the back surface of the semiconductor substrate; Depositing a film;
(D) forming a metal layer in the via hole on which the insulating film is deposited;
A method for manufacturing a semiconductor device including: 2. The method according to claim 1, wherein in the step (b), a back surface of the semiconductor substrate is arranged on the first support, and a via hole is formed from the element layer side. 3. The step (b) comprises:
(B-1) forming a resist pattern on the element layer;
(B-2) using the resist pattern as a mask, etching the element layer and the semiconductor support substrate by reactive ion etching;
3. The method for manufacturing a semiconductor device according to claim 2, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (b), the element layer is arranged on the first support, and a via hole is formed from the back side of the semiconductor substrate. The step (b) comprises:
(B-4) forming a resist pattern on the back surface of the semiconductor substrate;
(B-5) using the resist pattern as a mask, performing reactive ion etching through the semiconductor support substrate to expose an electrode layer in the element layer;
5. The method for manufacturing a semiconductor device according to claim 4, comprising: The step (b) comprises:
2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of: (b-3) irradiating a laser beam to form a via hole in said semiconductor substrate. 2. The method according to claim 1, wherein in the step (c), the second support includes a magnetic metal material, a magnet is arranged on a back surface of the semiconductor substrate, and the semiconductor substrate is brought into close contact with the second support. 7. The method for manufacturing a semiconductor device according to claim 1. The step (b) includes a step of forming a resist pattern on the back surface of the semiconductor substrate,
5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step (c), an insulating layer is deposited by sputtering with a resist pattern left on the back surface of the semiconductor substrate, and then lift-off is performed. The step (d) includes:
(D-1) disposing the element layer on a third support having a smooth surface, and disposing a stencil mask on the back surface of the semiconductor substrate;
(D-2) depositing a metal layer in the opening and a part of the element layer from above the stencil mask;
The method for manufacturing a semiconductor device according to claim 1, further comprising: The step (d) includes:
(D-3) forming the metal layer by squeezing using the stencil mask as a guide;
The method for manufacturing a semiconductor device according to claim 9, comprising:

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