JP2004134047A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory which adequately restrains complication in circuit configuration and enlargement in circuit scale while having an access structure for accessing a memory cell by using a prescribed voltage obtained by boosting a supply voltage. <P>SOLUTION: Access to each memory cell of a memory array 110 is made by an boosted voltage obtained by boosting the supply voltage of a battery 195 through a boosting circuit 190. The power supply for a memory block 100 including the memory array 110 is the boosting circuit 190. Level shifters 115, 157 and 185 are provided, which convert to a voltage with the boosted voltage boosted by the boosting circuit 190 a signal (a signal whose voltage level is the voltage level of the battery 195) inputted to the memory block 100 from the outside of the memory block 100. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory having an access structure for accessing a memory cell with a predetermined boosted voltage.
[0002]
[Prior art]
FIG. 7 shows an example of this type of semiconductor memory. As shown in FIG. 7, this semiconductor memory includes a memory cell array 310 in which a plurality of memory cells are regularly arranged two-dimensionally. This memory cell array is configured as a flash memory. This flash memory is a kind of electrically rewritable nonvolatile memory (Electrically Erasable and Programmable Read Only Memory: EEPROM), and has a configuration in which data stored in a plurality of predetermined memory cells is collectively erased. It has become. FIG. 8 shows an equivalent circuit of each memory cell.
[0003]
As shown in FIG. 8, this flash memory is configured as a split gate type described in, for example, Patent Document 1 below. Each memory cell MC includes a transistor MT having a control gate cg and a floating gate fg formed between the control gate cg and the channel c via an insulator. This transistor MT holds (stores) logic "H" or "L" data depending on the manner in which electrons are stored in floating gate fg, that is, whether electrons are stored in floating gate fg or not. It is.
[0004]
The control gate cg of the transistor MT is connected to the word line WL, the drain d is connected to the bit line BL, and the source s is connected to the source line SL. Then, by applying the voltages shown in FIG. 9 to the word lines WL, the bit lines BL, and the source lines SL, data is read from the memory cell MC, data is written to the memory cell MC, and the memory cell MC is read. Erasing the data held in each of them.
[0005]
Next, data read, write, and erase access operations to and from the memory cell MC will be described in further detail with reference to FIG. Incidentally, in this semiconductor memory, the memory block 300 surrounded by a broken line in the figure basically uses the battery 395 as a power supply source.
[0006]
First, when reading data stored and held in the memory cell MC, the voltage of the battery 395 (for example, 1.5 V) is boosted to a boosted voltage for reading (for example, 3.0 V) in the booster circuit 390. Further, row address data and column address data of the memory cell MC to be accessed from the outside are input to the column address decoder 320 and the row address decoder 330, respectively.
[0007]
Then, the column address decoder 320 outputs a signal for accessing a predetermined memory cell MC of the memory cell array 310 to the bit line selector 325 based on the column address data. In contrast, the bit line selector 325 selectively precharges the bit line BL of the memory cell MC to be accessed with the voltage of the battery 395.
[0008]
While such precharge is performed, the row address decoder 330 outputs a signal for accessing a predetermined memory cell MC of the memory cell array 310 to the level shifter 335 based on the row address data. On the other hand, the level shifter 335 converts the output of the row address decoder 330 with the boosted voltage of the boosting circuit 390. That is, the output of the row address decoder 330 that sets the high voltage side (for example, 1.5 V) of the battery 395 to logic “H”, and sets the ground to logic “L”, for example, and the output voltage of the booster circuit 390 (for example, 3 V) The voltage is converted to data that is set to “H” and, for example, the ground side is set to logic “L”. Then, the voltage-converted signal is taken into the word line driver 340, and the driver corresponding to the word line WL of the memory cell MC to be accessed is selectively driven. That is, the boosted voltage is applied from the selected driver to the corresponding word line WL. FIG. 10 shows, for reference, an equivalent circuit of a portion connected to a predetermined word line WL among the row address decoder 330, the level shifter 335, and the word line driver 340.
[0009]
Thus, data can be read in accordance with a change in the potential of the precharged bit line BL. That is, when electrons are held in the floating gate fg of the transistor MT (FIG. 8) of the memory cell MC to be accessed, the potential of the bit line BL does not change, but when electrons are not held. The potential of the bit line BL changes. Therefore, the change in the potential of the bit line BL can be amplified by the read amplifier 350 and taken out as read data.
[0010]
When writing data to the memory cell MC (accumulating electrons in the floating gate fg), the voltage of the battery 395 is boosted by the booster circuit 390 to a boosted voltage for writing (for example, 9.0 V). Further, row address data and column address data of the memory cell MC to be accessed from the outside are input to the column address decoder 320 and the row address decoder 330, respectively.
[0011]
Then, the column address decoder 320 outputs a signal for accessing a predetermined memory cell MC of the memory cell array 310 to the bit line selector 325 based on the column address data. On the other hand, the bit line selector 325 applies a predetermined voltage (for example, 0.6 V) generated by the write amplifier 355 to the bit line BL of the memory cell MC to be accessed.
[0012]
On the other hand, row address decoder 330 outputs a signal for accessing predetermined memory cell MC of memory cell array 310 based on the row address data. On the other hand, the level shifter 335 converts the output of the row address decoder 330 with the voltage of the 2.0 V generator 360. Then, the voltage-converted signal is taken into the word line driver 340, and the driver corresponding to the word line WL of the memory cell MC to be accessed is selectively driven. That is, the boosted voltage is applied from the selected driver to the corresponding word line.
[0013]
The level shifter 365 converts the output of the row address decoder 330 by the voltage of the booster circuit 390. Then, the voltage-converted signal is captured by the source line driver 370, and the driver corresponding to the source line SL of the memory cell MC to be accessed is selectively driven. That is, the boosted voltage of the booster circuit 390 is applied to the corresponding source line SL from the selected driver. Thus, data is written to the memory cell to be accessed.
[0014]
Further, when erasing data stored in the memory cell MC, the voltage of the battery 395 is boosted to a boosted voltage for erasing (for example, 9.0 V) through the boosting circuit 390. Further, the row address data of the memory cell MC to be accessed from the outside is input to the row address decoder 330, and the column address data is input to the column address decoder 320.
[0015]
Then, the bit line selector 325 sets the voltage of the bit line BL and the source line SL of the memory cell MC to be accessed (plural) to “0 V” based on the column address data.
[0016]
Further, the row address decoder 330 outputs a signal for accessing a predetermined word line WL of the memory cell array 310 based on the row address data. On the other hand, the level shifter 335 converts the output of the row address decoder 330 with the boosted voltage of the boosting circuit 390. Then, the voltage-converted signal is taken into the word line driver 340, and the driver corresponding to the word line WL is selectively driven by the boosted voltage. That is, the boosted voltage is applied from the selected driver to the corresponding word line. Thereby, the data of the memory cell MC connected to the word line WL is erased.
[0017]
Incidentally, the access timing and the like of such a series of memory cells are controlled by the control circuit 380 based on signals (read enable, write enable, erase enable) instructing an external access mode.
[0018]
As publications describing such a semiconductor memory, there are Patent Document 2 below in addition to Patent Document 1 described above.
[0019]
[Patent Document 1]
JP-A-9-213086
[Patent Document 2]
JP-A-2001-102553
[0020]
[Problems to be solved by the invention]
According to the semiconductor memory described above, since the semiconductor memory is basically driven by the power from the battery 395 and includes the booster circuit 390, it is possible to accurately access the memory cell MC. However, such a semiconductor memory, on the other hand, requires a dedicated circuit for applying the boosted voltage by the booster circuit 390 to the memory cell MC when accessing the memory cell MC, and it is inevitable that the entire memory cell becomes complicated. In fact. Further, the level shifters 335 and 365 need to be provided between the row address decoder 330 and the word line driver 340 and between the row address decoder 330 and the source line driver 370.
[0021]
It should be noted that not only the flash memory but also a semiconductor memory that accesses a memory cell using a voltage obtained by boosting a power supply voltage in a predetermined manner, such a situation is generally common.
[0022]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an access structure for accessing a memory cell using a voltage obtained by boosting a power supply voltage to a predetermined level, while complicating the circuit configuration and increasing the circuit scale. It is an object of the present invention to provide a semiconductor memory capable of suitably suppressing an increase in the number.
[0023]
[Means for Solving the Problems]
Hereinafter, the means for achieving the above object and the effects thereof will be described.
According to a first aspect of the present invention, in a semiconductor memory in which a memory cell is accessed by a driver driven by a boosted voltage obtained by boosting a power supply voltage to a predetermined value, data related to an address designating the memory cell to be accessed is stored. The gist of the present invention is to include a level shifter that performs voltage conversion by the boosted voltage and an address decoder that selectively drives a driver corresponding to the data related to the address based on an output of the level shifter.
[0024]
In the above configuration, the address decoder that selectively drives the driver corresponding to the data related to the address operates based on the output of the level shifter. Therefore, the operating voltage of the address decoder and the driver can be set to a common boosted voltage. Therefore, it is possible to eliminate the necessity of providing a level shifter between the address decoder and the driver, and it is possible to preferably suppress an increase in the circuit scale of the semiconductor memory. That is, in the case where the level shifters are provided between the address decoder and the driver, the number of level shifters required is equal to the number of drivers to be driven. However, the above configuration requires only the level shifter having the number of bits capable of describing the number of drivers. Yes, an increase in circuit scale is suppressed.
[0025]
The semiconductor memory having such a configuration is particularly effective when the ratio of the area of the memory cell to the integrated circuit on which the semiconductor memory is mounted is equal to or less than a predetermined value or when the required design period is equal to or less than a predetermined value. is there.
[0026]
According to a second aspect of the present invention, a row address of a memory cell to be accessed is specified by applying a boosted voltage obtained by boosting a power supply voltage to a word line selected by a driver, and a bit line is selected. In the semiconductor memory for specifying the column address of the memory cell to be accessed in the same manner, when data related to a row address that specifies a word line corresponding to the memory cell to be accessed is input, It comprises a level shifter for converting a voltage by a boosted voltage, and a row address decoder for selectively driving a driver for applying the boosted voltage to a word line of the memory cell to be accessed based on an output of the level shifter. And
[0027]
In the above configuration, the row address decoder that selectively drives the driver corresponding to the data related to the row address operates based on the output of the level shifter. Therefore, the operating voltage of the row address decoder and the driver can be set to a common boosted voltage. Therefore, it is possible to eliminate the necessity of providing a level shifter between the row address decoder and the driver, and it is possible to suitably suppress an increase in the circuit scale of the semiconductor memory. That is, in the case where the level shifters are provided between the row address decoder and the driver, the number of level shifters required is equal to the number of drivers to be driven. However, in the above configuration, only the level shifter having the number of bits capable of describing the number of drivers is required. Thus, an increase in the circuit scale is suppressed.
[0028]
Note that the semiconductor memory having such a configuration is particularly effective when the ratio of the area of the memory cell to the integrated circuit on which the semiconductor memory is mounted is equal to or less than a predetermined value or when the required design period is equal to or less than a predetermined value. .
[0029]
According to a third aspect of the present invention, in the second aspect, a bit line selector for selecting a bit line of the memory cell to be accessed and a bit line corresponding to the memory cell to be accessed are specified. When data related to a column address is input, a level shifter that voltage-converts the data related to the column address by the boosted voltage, and a column address that drives the bit line selector based on an output of the level shifter to which the data related to the column address is input The gist is to further include a decoder.
[0030]
In the above configuration, since the row address decoder and the column address decoder can be transistors having the same characteristics, they can be controlled by signals of the same voltage level, so that control can be performed easily. Become. Further, since the bit line selector, the column address decoder, the row address decoder, and the word line driver can be transistors having the same characteristics, their manufacture can be performed easily.
[0031]
Further, in the above configuration, the column address decoder that drives the bit line selector operates based on the output of the level shifter. Therefore, the operating voltage of the column address decoder and the driver can be set to a common boosted voltage. Therefore, even when the bit line selector is driven by the boosted voltage, it is possible to eliminate the necessity of providing a level shifter between the column address decoder and the driver, and appropriately suppress an increase in the circuit scale of the semiconductor memory. Will be able to
[0032]
According to a fourth aspect of the present invention, in the second or third aspect, a level shifter that converts a command signal for commanding an access mode to the memory cell by the boosted voltage, and a level shifter to which the command signal is input And a control circuit for controlling access timing to the memory cell based on the output of the control circuit.
[0033]
In the above configuration, the control circuit that controls the access timing to the memory cell operates based on the output of the level shifter. Therefore, the operating voltage of the memory cell, the row address decoder, the driver, etc., and the control circuit can be set to the common boosted voltage, and the control circuit can easily perform these controls.
[0034]
According to a fifth aspect of the present invention, there is provided a booster circuit for boosting a power supply voltage to a predetermined boosted voltage, a memory cell as a memory block, a driver driven by the boosted voltage to access the memory cell, and an external address. In a semiconductor memory including at least an address decoder for selectively driving a driver corresponding to the address data based on data related to the data, the memory block uses the booster circuit as a power supply source, and receives an input signal by the boosted voltage. The point is to provide a level shifter for performing voltage conversion.
[0035]
In the above configuration, since the memory block uses the booster circuit as a power supply source, peripheral circuits of the memory cells in the memory block such as a driver and an address decoder that access the memory cell can be operated at a common boosted voltage. Thus, the circuit can be simplified.
[0036]
In addition, since the input signal is voltage-converted by the boosted voltage by the level shifter, the transmission and reception of the signal between the memory block and the outside can be performed accurately. Further, since the signal input to the memory block is voltage-converted by the level shifter, at least the address decoder can directly drive the driver based on the voltage-converted signal, which is compared with the case where the level shifter is provided immediately before the driver. As a result, the circuit scale can be reduced.
[0037]
Note that the semiconductor memory having such a configuration is particularly effective when the ratio of the area of the memory cell to the integrated circuit on which the semiconductor memory is mounted is equal to or less than a predetermined value or when the required design period is equal to or less than a predetermined value. .
[0038]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
Hereinafter, a first embodiment of a semiconductor memory according to the present invention will be described with reference to the drawings.
[0039]
FIG. 1 is a block diagram showing the overall configuration of the semiconductor memory according to the present embodiment. This semiconductor memory is mounted on a semiconductor integrated circuit together with a logic circuit and the like. This semiconductor memory includes a memory block 100 and a booster circuit 190 that boosts a power supply voltage (for example, 1.5 V) of a battery 195 to a predetermined voltage. Then, as shown in FIG. 1, the memory block 100 uses the booster circuit 190 as a power supply source.
[0040]
As described above, in the present embodiment, the booster circuit 190 is used as the power supply source of the memory block 100, and all the transistors in the memory block 100 have the same characteristics (such as withstand voltage characteristics), thereby simplifying the configuration. Aim. In addition, by applying the boosted voltage to the memory block 100 in a lump as described above, the power supply path is simplified as compared with the case where the memory block has a plurality of power supply paths.
[0041]
The memory block 100 includes a memory cell array 110 similar to the memory cell array 310 shown in FIG. Each memory cell MC of the memory cell array 110 is the same as that shown in FIG. When accessing the memory cell MC, a voltage is applied to the word line WL, bit line BL, and source line SL of each memory cell in basically the same manner as in the semiconductor memory shown in FIG. I do.
[0042]
Then, in the present embodiment, such a memory cell and peripheral circuits of the memory cell in the memory block 100 are operated by a common boosted voltage. Therefore, a level shifter 115 for converting a signal (assuming the voltage level of the battery 195 as the voltage level) input from the outside of the memory block 100 to the same memory block 100 by the boosted voltage boosted by the booster circuit 190, 157 and 185 are provided. Therefore, the logic level signal binarized between the high voltage side of the battery 195 and the ground by each of the level shifters 115, 157, and 185 is replaced with the output voltage of the booster circuit 190 and the logic level signal binarized between the ground and the ground. Will be converted to
[0043]
As described above, in the memory block 100, the signals taken in from the respective input terminals are voltage-converted by the level shifters, so that the circuits in the memory block 100 can be accurately determined based on the operating voltage level signal external to the memory block 100. It can be operated.
[0044]
Further, a level shifter 152 for converting a signal output to the outside of the memory block 100 into a voltage by the voltage of the battery 195 is provided. Thus, it is possible to accurately process the output signal of the memory block 100 outside the memory block 100.
[0045]
Here, when row address data designating the word line WL corresponding to the memory cell MC to be accessed is input, the level shifter 115 converts the voltage of the row address data by the boosted voltage of the booster circuit 190, and the row address decoder 130 Is output to Further, the same level shifter 115 receives the column address data specifying the bit line BL corresponding to the memory cell MC to be accessed, and converts the column address data by the boosted voltage of the booster circuit 190.
[0046]
On the other hand, the row address decoder 130 is a circuit that selectively drives a driver in the word line driver 140 that applies a boosted voltage to the word line WL of the memory cell MC to be accessed based on the output of the level shifter 115. That is, a driver that applies a boosted voltage to the word line WL of the memory cell MC to be accessed is selected in the word line driver 140 based on the row address data subjected to the voltage conversion by the level shifter 115. FIG. 2 illustrates a configuration of a portion connected to a predetermined word line WL in the row address decoder 130 and the word line driver 140.
[0047]
As shown in FIG. 2, the row address decoder 130 inputs a logic "H" signal to a predetermined driver 140d of the word line drivers 140 based on the row address data subjected to the voltage conversion. On the other hand, the driver 140d is driven using any one of the 2.0V generator 160 and the booster circuit 190 as a power supply source. When a logic "H" signal is input from the row address decoder 130, the driver 140d operates as described above. The voltage of the power supply is applied to the word line WL.
[0048]
Note that the 2.0 V generation unit 160 is a circuit that reduces the boosted power of the boost circuit 190 to generate a voltage of “2.0 V”.
On the other hand, the column address decoder 120 drives the bit line selector 125 based on the output of the level shifter to which the column address data is input. That is, the bit line selector 125 is controlled so as to select the bit line BL based on the column address data subjected to the voltage conversion by the level shifter 115. FIG. 3 illustrates a configuration of a portion connected to a predetermined bit line BL in the column address decoder 120, the bit line selector 125, and the like.
[0049]
As shown in FIG. 3, the column address decoder 120 outputs a signal of logic “H” to a predetermined selector circuit 125 c of the bit line selector 125 based on the converted column address data and the like. On the other hand, the read amplifier 150 or the write amplifier 155 is selectively connected to the selector circuit 125c. The read amplifier 150 and the write amplifier 155 are configured to be supplied with power from a circuit that reduces a boosted voltage to generate a predetermined voltage as shown in FIG. Has become.
[0050]
That is, the read amplifier 150 uses, as a power supply source, the 1.5 V generation unit 151 that generates a voltage of “1.5 V” in addition to the booster circuit 190. In addition, the write amplifier 155 uses, as a power supply source, a 0.6 V generation unit 156 that generates a voltage of “0.6 V” in addition to the booster circuit 190.
[0051]
The read amplifier 150 and the write amplifier 155 are connected to level shifters 152 and 157 for converting a voltage level between the inside and the outside of the memory block 100, respectively.
[0052]
When a signal (read enable, write enable, erase enable) for instructing an access mode to the memory cell is input from the outside, the control circuit 180 controls the access timing to the memory cell based on the signal. is there. Here, the command signal from the outside is voltage-converted by the boosted voltage of the boosting circuit 190 by the level shifter 185, and then is taken into the control circuit 180. This makes it possible to drive the control circuit 180 using the boosted voltage as the operating voltage.
[0053]
Next, each access operation of reading, writing, and erasing data between the memory cell MC and the semiconductor memory will be described in more detail.
First, when reading data stored and held in the memory cell MC, the voltage of the battery 195 (for example, 1.5 V) is boosted to a boosted voltage for reading (for example, 3.0 V) in the booster circuit 190. Also, a command signal (read enable) for performing reading from the outside is input to the level shifter 185. On the other hand, the level shifter 185 converts this command signal into a voltage using a boosted voltage and outputs the converted signal to the control circuit 180. Further, the row address data and the column address data of the memory cell MC to be accessed from the outside are voltage-converted by the level shifter 115, respectively, and then input to the column address decoder 120 and the row address decoder 130.
[0054]
Then, the column address decoder 120 outputs a signal for accessing a predetermined memory cell MC of the memory cell array 110 to the bit line selector 125 based on the column address data and the timing signal output from the control circuit 180. That is, when a control signal that becomes logic “H” is input at a predetermined timing from the control circuit 180 to the column address decoder 120 shown in FIG. 3, the same column address decoder 120 accesses a predetermined memory cell MC. A signal of logic “H” is output to the selector circuit 125c. On the other hand, the bit line selector 125 selectively precharges the bit line BL of the memory cell MC to be accessed with the voltage of the 1.5 V generation unit 151.
[0055]
While such precharge is performed, the row address decoder 130 outputs a signal for accessing a predetermined memory cell MC of the memory cell array 110 to the word line driver 140 based on the row address data and the timing signal output from the control circuit 180. Output to That is, when a control signal that becomes logic “H” is input at a predetermined timing from the control circuit 180 to the input terminal of the row address decoder 130 shown in FIG. A logic "H" signal is output to the driver 130d that accesses the MC. Then, the driver 130d corresponding to the word line WL of the memory cell MC to be accessed is selectively driven.
[0056]
As a result, data is read out in accordance with a change in the potential of the precharged bit line BL. That is, a change in the potential of the bit line BL is amplified by the read amplifier 150 to be read data, and then converted by the power supply voltage of the battery 195 by the level shifter 152 and output to the outside.
[0057]
Further, when writing data to the memory cell MC, the voltage of the battery 195 is boosted to a boosted voltage for writing (for example, 9.0 V) in the booster circuit 190. In addition, a command signal (write enable) for performing writing from outside is input to the level shifter 185. On the other hand, the level shifter 185 converts this command signal into a voltage using a boosted voltage and outputs the converted signal to the control circuit 180. Further, the row address data and the column address data of the memory cell MC to be accessed from the outside are respectively subjected to voltage conversion by the level shifter 115 and then input to the column address decoder 120 and the row address decoder 130. Further, data (write data) desired to be written from the outside is converted into a voltage by the boosted voltage by the level shifter 157, and is taken into the write amplifier 155. Hereinafter, a case will be described as an example where the write data corresponds to data in which electrons are accumulated in the floating gate fg.
[0058]
That is, the column address decoder 120 outputs a signal for accessing a predetermined memory cell MC of the memory cell array 110 to the bit line selector 125 based on the column address data subjected to the voltage conversion and the timing signal output from the control circuit 180. I do. On the other hand, the bit line selector 125 applies the “0.6 V” voltage generated by the 0.6 V generation unit 156 to the bit line BL of the memory cell MC to be accessed.
[0059]
On the other hand, the row address decoder 130 outputs a signal for accessing a predetermined memory cell MC of the memory cell array 110 based on the row address data subjected to the voltage conversion and the timing signal output from the control circuit 180. On the other hand, in the word line driver 140, the driver 140d (FIG. 2) corresponding to the word line WL of the memory cell MC to be accessed is selectively driven by the voltage of the 2.0V generation unit 160. Become.
[0060]
Further, based on the output of the row address decoder 130, the driver corresponding to the source line SL of the memory cell MC to be accessed is selectively driven by the boosted voltage in the source line driver 170. Thus, data is written to the memory cell to be accessed.
[0061]
Further, when erasing the data stored in the memory cell MC, the booster circuit 190 boosts the voltage of the battery 195 to a boosted voltage for erasing (for example, 9.0 V). In addition, a command signal (erase enable) for performing erasure is input to the level shifter 185 from the outside. On the other hand, the level shifter 185 converts this command signal into a voltage using a boosted voltage and outputs the converted signal to the control circuit 180. Further, the row address data and the column address data of the memory cell MC to be accessed from the outside are voltage-converted by the level shifter 115 and then input to the row address decoder 130 and the column address decoder 120.
[0062]
Then, in the bit line selector 125, based on the column address data, the voltage of the bit line BL and the source line SL of the memory cell MC to be accessed is set to “0 V”.
[0063]
Further, the row address decoder 130 outputs a signal for accessing a predetermined word line WL of the memory cell array 110 based on the row address data and the timing signal output from the control circuit 180. Then, the driver corresponding to the word line WL is selectively driven by the boosted voltage. Thereby, the data of the memory cell MC connected to the word line WL is erased.
[0064]
As described above, in the present embodiment, the row address decoder 130 is driven by the boosted voltage, and the level shifter 115 is provided so that the row address data is converted into a voltage by the boosted voltage and supplied to the row address decoder 130. Thereby, the circuit scale of the memory block 100 can be suitably reduced. That is, in the level shifter 115, as a circuit for converting the voltage of the row address data, when the row address of the memory cell is, for example, “1024”, at least “10” circuits (the preceding circuits) capable of expressing this in a binary number (The circuit illustrated in FIG. 10). On the other hand, in the configuration shown in FIG. 7, "1024" circuits illustrated in FIG. 10 are required in the level shifter 335.
[0065]
In the present embodiment, not only the row address decoder 130 but also the column address decoder 120 are driven by the boosted voltage, and the control circuit 180 is further driven by the boosted voltage. Thus, the command signal of the control circuit 180 can be directly output to the row address decoder and the column address decoder 120, and the circuit of the control system is simplified.
[0066]
Note that when the boosted voltage of the booster circuit 190 is used as the power supply source of the memory block 100, the power consumption may increase as compared with the memory block 300 shown in FIG. However, the semiconductor memory according to the present embodiment is particularly effective in the following situations where the disadvantages of the increase in power consumption are remarkably compensated.
[0067]
(A) When the area ratio of the semiconductor memory in the semiconductor integrated circuit on which the semiconductor memory is mounted is small.
(B) When the design time of the semiconductor integrated circuit on which the semiconductor memory is mounted is short.
[0068]
According to the embodiment described above, the following effects can be obtained.
(1) The row address decoder 130 that selectively drives the driver 140d in the word line driver 140 corresponding to the row address data operates based on the output of the level shifter 115, thereby suppressing an increase in circuit scale. Will be able to do it.
[0069]
(2) Since the row address decoder 130 and the column address decoder 120 are transistors having the same characteristics, they can be controlled by signals of the same voltage level, and control can be performed easily. .
[0070]
(3) The control circuit 180 that controls the access timing to the memory cell operates based on the output of the level shifter 185. Therefore, the operating voltage of the memory cell, the row address decoder 130, the word line driver 140, the source line driver 170, etc., and the control circuit 180 can be made a common boosted voltage, and the circuit of the control system is simplified. be able to.
[0071]
(4) The level shifter 152 converts the read data read from the memory cell with the power supply voltage of the battery 195. As a result, a circuit outside the memory block 100 can properly process the read data.
[0072]
(Second embodiment)
Hereinafter, a second embodiment of the semiconductor memory according to the present invention will be described with reference to the drawings, focusing on differences from the first embodiment.
[0073]
FIG. 4 is a block diagram illustrating the overall configuration of the semiconductor memory according to the present embodiment. This semiconductor memory is also mounted on a semiconductor integrated circuit together with a logic circuit and the like.
[0074]
However, the memory cell array 210 of the present embodiment is a two-dimensionally regularly arranged dynamic random access memory (DRAM) as a memory cell. More specifically, the memory cell MC according to the present embodiment includes one transistor T and one capacitor C, as shown in FIG. That is, the capacitor C whose one end is grounded is connected to the source s of the transistor T, and the drain d of the transistor T is connected to the bit line BL. Further, the gate g of the transistor T and the word line WL are connected.
[0075]
The node between the source s of the transistor T and the other end of the capacitor C is a node for holding data. Then, data is transferred between the bit line BL and the node by conducting between the source s and the drain d of the transistor T. The transmission and reception of the data is performed by applying a voltage to the word line WL and the bit line BL in a manner shown in FIG.
[0076]
As shown in FIG. 6, in the present embodiment, when accessing the memory cell MC irrespective of read / write, a predetermined boost higher than the voltage (for example, 1.5 V) of the battery 295 shown in FIG. A voltage (for example, 3.0 V) is used. For this reason, the semiconductor memory according to the present embodiment includes the memory block 200, the booster circuit 290 that boosts the power supply voltage (for example, 1.5 V) of the battery 295 to the predetermined voltage, and the power supply of the memory block 200. The source is a booster circuit 290.
[0077]
As described above, in the present embodiment, the booster circuit 290 is used as the power supply source of the memory block 200, so that all the transistors in the memory block 200 have the same characteristics (such as withstand voltage characteristics), thereby simplifying the configuration. Aim. Further, by applying the boosted voltage to the memory block 200 in a lump as described above, the power supply path is simplified as compared with the case where the memory block 200 has a plurality of power supply paths.
[0078]
Note that the memory block 200 includes a 0.75 V generation unit 251 and a 1.5 V generation unit 256 that generate a voltage applied to the bit line BL at the time of reading and writing by reducing the boosted voltage of the boosting circuit 290. I have. Then, at the time of reading, the read amplifier 250 outputs the voltage generated by the 0.75 V generation unit 251 to the bit line selector 225. Further, at the time of writing, the write amplifier 255 outputs the voltage generated by the 1.5 V generation unit 256 to the bit line selector 225.
[0079]
Next, the operation of reading data from and writing data to the memory cell MC will be further described with reference to FIG.
First, when reading data stored and held in the memory cell MC, a command signal (read enable) for reading data from the outside is input to the level shifter 285. On the other hand, the level shifter 285 converts the input command signal into a voltage using the boosted voltage of the boosting circuit 290 and outputs the converted signal to the control circuit 280. Further, the row address data and the column address data of the memory cell MC to be accessed from the outside are voltage-converted by the level shifter 215, respectively, and then input to the column address decoder 220 and the row address decoder 230.
[0080]
Then, the column address decoder 220 outputs a signal for accessing a predetermined memory cell MC of the memory cell array 210 to the bit line selector 225 based on the column address data and the timing signal output from the control circuit 180. Accordingly, the bit line selector 225 selectively precharges the bit line BL of the memory cell MC to be accessed with the voltage of the 0.75 V generation unit 251.
[0081]
While such precharge is performed, the row address decoder 230 outputs a signal for accessing a predetermined memory cell MC of the memory cell array 210 to the word line driver 240 based on the row address data and the timing signal output from the control circuit 280. Output to As a result, in the word line driver 240, a driver that applies a boosted voltage to the word line WL of the memory cell MC to be accessed is selectively driven.
[0082]
As a result, data is read out in accordance with a change in the potential of the precharged bit line BL. That is, after a change in the potential of the bit line BL is amplified by the read amplifier 250 to be read data, the level shifter 252 converts the voltage with the voltage of the battery 295 and outputs the converted data to the outside.
[0083]
When writing data to the memory cells MC, a command signal (write enable) for writing data from the outside is input to the level shifter 285. On the other hand, the level shifter 285 converts the input command signal into a voltage using the boosted voltage of the boosting circuit 290 and outputs the converted signal to the control circuit 280. Further, the row address data and the column address data of the memory cell MC to be accessed from the outside are respectively subjected to voltage conversion by the level shifter 215, and then input to the column address decoder 220 and the row address decoder 230.
[0084]
Then, the row address decoder 230 outputs a signal for accessing a predetermined memory cell MC of the memory cell array 210 based on the row address data subjected to the voltage conversion and the timing signal output from the control circuit 280. On the other hand, the word line driver 240 selectively applies the boosted voltage to the word line WL of the memory cell MC to be accessed.
[0085]
On the other hand, the column address decoder 220 outputs a signal for accessing a predetermined memory cell MC of the memory cell array 210 to the bit line selector 225 based on the converted column address data and the timing signal output from the control circuit 280. I do. On the other hand, the write data input from the outside of the memory block 200 to the level shifter 257 is subjected to voltage conversion by the boosted voltage of the booster circuit 290, and then is output to the write amplifier 255. Then, in the write amplifier 255, the voltage generated by the 1.5V generation unit 256 or the voltage of “0V” depends on whether the converted write data is logic “H” or logic “L”. Is output. Then, the bit line selector 225 applies the voltage output from the write amplifier 255 to the bit line BL of the memory cell MC to be accessed.
[0086]
According to the present embodiment described above, effects similar to the above (1) to (4) of the first embodiment can be obtained.
Note that each of the above embodiments can be modified and implemented as follows.
[0087]
In the first embodiment, the configuration of each memory cell of the flash memory is not limited to that illustrated in FIG. For example, in addition to the floating gate fg and the control gate cg, a device provided with a dedicated erase gate used for erasing stored data may be provided.
[0088]
In the first embodiment, the corresponding word line and source line are designated by the row address data, and the corresponding bit line is designated by the column address data. However, the present invention is not limited to this. For example, the configuration may be such that the corresponding word line is specified by the row address data, and the corresponding bit line and source line are specified by the column address data.
[0089]
The number of level shifters can be reduced by setting the drive voltage of the row address decoder 130 to the boosted voltage of the booster circuit 190 without using the booster circuit 190 as the power supply source of the memory block 100. At this time, if the drive voltage of the column address decoder 120 and the control circuit 180 is set to a boosted voltage, the effects (2) and (3) of the first embodiment can be obtained.
[0090]
In the first embodiment, the predetermined voltage applied to the bit line is not limited to the one exemplified in the first embodiment, and may be a predetermined voltage for writing and a predetermined voltage for reading, respectively. Just set it.
[0091]
In the first embodiment, the predetermined voltage applied to the word line at the time of writing is not limited to the voltage exemplified in the first embodiment, but may be set as appropriate.
In the first embodiment, a split gate flash memory is used. However, a stack gate flash memory may be used.
[0092]
In the first embodiment and its modifications, the invention is not limited to a flash memory, but may be any electrically rewritable nonvolatile memory (EEPROM).
In the second embodiment, the configuration of each memory cell of the DRAM is not limited to the configuration including one capacitor and one transistor as illustrated in FIG.
[0093]
Even if the power supply source of the memory block 200 is not the booster circuit 290, the number of level shifters can be reduced by setting the drive voltage of the row address decoder 230 to the boosted voltage of the booster circuit 290. At this time, if the drive voltage of the column address decoder 220 and the control circuit 280 is set to be a boosted voltage, it is possible to obtain the effects according to the above (2) and (3) of the first embodiment. it can.
[0094]
A row address of a memory cell to be accessed is specified by applying a predetermined boosted voltage to a word line selected by a driver, and a column address of the memory cell to be accessed by selecting a bit line. The specified semiconductor memory is not limited to the DRAM. For example, an SRAM may be used.
[0095]
In each of the above embodiments, instead of making all the transistor characteristics in the memory block the same, the transistor characteristics may be appropriately changed within a range having a withstand voltage characteristic that can withstand a boosted voltage.
[0096]
Further, the present invention is effective not only in the above-mentioned memory but also in the case where a memory cell is accessed using a boosted voltage.
The boosted voltage is not limited to the one that boosts the power supply voltage to a positive voltage value, and may be the one that boosts (steps down) a negative voltage value.
[0097]
The level shifter is not limited to the one that converts a logic level signal binarized between the power supply voltage and the ground potential into a logic level signal binarized between the output voltage of the boosted voltage and the ground potential. . The point is to convert a binarized logic level signal whose voltage range is defined based on the power supply voltage into a binarized logic level signal whose voltage range is defined based on the boosted voltage. I just need.
[0098]
In addition, as a technical idea which can be grasped from each of the above embodiments and its modifications, there are the following.
(1) In the semiconductor memory according to any one of claims 2 to 4, the memory cell has a control gate and a floating gate connected to the word line, and data is stored in the floating gate by means of holding electrons. Semiconductor memory, which is an electrically rewritable non-volatile memory including a transistor for storing data.
[0099]
(2) In the semiconductor memory according to the above (1), the semiconductor memory is configured as a flash memory, and is used for writing data to the memory cell and erasing data held in the memory cell. In any one of the above embodiments, a driver that applies a boosted voltage to one of a source and a drain of the transistor included in the memory cell, and the data related to the row address is generated by a boosted voltage applied to one of the source and the drain. A level shifter for performing voltage conversion, wherein the row address decoder includes a driver for applying a voltage to one of the source and the drain based on an output of the level shifter for performing voltage conversion on data related to the row address. Machine that selectively drives drivers that support The semiconductor memory further comprising a.
[0100]
(3) In the semiconductor memory according to the above (1), the semiconductor memory is configured as a flash memory, and is used for writing data to the memory cell and erasing data held in the memory cell. In any one of the memory cell, a driver that applies a boosted voltage to any one of a source and a drain of the transistor included in the memory cell, and the data related to the column address is generated by the boosted voltage applied to any of the source and the drain. A level shifter for performing voltage conversion, wherein the column address decoder is a driver that applies a voltage to one of the source and the drain based on an output of the level shifter that performs voltage conversion on the data related to the column address. Machine that selectively drives drivers that support The semiconductor memory further comprising a.
[0101]
(4) In the semiconductor memory according to any one of claims 2 to 4, the semiconductor memory conducts between a node of a corresponding memory cell and a bit line by applying a predetermined boosted voltage to a selected word line. Data is written by applying a predetermined voltage to the node via the bit line while the node is being connected to the bit line. A semiconductor memory for reading data by outputting to a line.
[0102]
(5) The semiconductor memory according to (3), wherein the semiconductor memory is configured as one of a dynamic random access memory and a static random access memory.
[0103]
(6) The semiconductor memory according to claim 5, wherein the memory block includes a level shifter that converts a signal to be output to the outside with a power supply voltage.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a first embodiment of a semiconductor memory according to the present invention.
FIG. 2 is a circuit diagram showing a circuit configuration of a word line drive system in the embodiment.
FIG. 3 is a circuit diagram showing a circuit configuration of a bit line drive system in the embodiment.
FIG. 4 is a block diagram showing an overall configuration of a second embodiment of the semiconductor memory according to the present invention;
FIG. 5 is a circuit diagram of the DRAM according to the embodiment;
FIG. 6 is a diagram showing a manner of applying a voltage to a memory cell in the same embodiment.
FIG. 7 is a block diagram showing the entire configuration of a conventional semiconductor memory.
FIG. 8 is a circuit diagram of a memory cell in the conventional semiconductor memory.
FIG. 9 is a diagram showing a manner of applying a voltage to a memory cell in the conventional semiconductor memory.
FIG. 10 is a circuit diagram showing a circuit configuration of a word line drive system in a conventional semiconductor memory.
[Explanation of symbols]
C: capacitor, d: drain, g: gate, s: source, T: transistor, BL: bit line, cg: control gate, fg: floating gate, MC: memory cell, MT: transistor, SL: source line, WL ... word lines, 195, 295, 395 ... batteries.

Claims (5)

In a semiconductor memory in which a memory cell is accessed by a driver driven by a boosted voltage obtained by boosting a power supply voltage,
A level shifter for voltage-converting data relating to an address designating the memory cell to be accessed by the boosted voltage; and an address decoder for selectively driving a driver corresponding to the data relating to the address based on an output of the level shifter. Semiconductor memory characterized by the above-mentioned. A row address of a memory cell to be accessed is specified by applying a boosted voltage obtained by boosting a power supply voltage to a word line selected by a driver, and a memory cell to be accessed by selecting a bit line. Semiconductor memory designating a column address of
When data related to a row address that specifies a word line corresponding to the memory cell to be accessed is input, a level shifter that performs voltage conversion of the data related to the row address by the boosted voltage, and the access based on an output of the level shifter A semiconductor memory, comprising: a row address decoder that selectively drives a driver that applies the boosted voltage to a word line of a target memory cell. The semiconductor memory according to claim 2,
When a bit line selector for selecting a bit line of the memory cell to be accessed and data relating to a column address designating a bit line corresponding to the memory cell to be accessed are input, the data relating to the column address is converted to the data. A semiconductor memory further comprising: a level shifter for performing voltage conversion by a boosted voltage; and a column address decoder for driving the bit line selector based on an output of the level shifter to which data relating to the column address is input. The semiconductor memory according to claim 2 or 3,
A level shifter for converting a command signal for commanding an access mode to the memory cell by the boosted voltage, and a control circuit for controlling access timing to the memory cell based on an output of the level shifter to which the command signal is input. A semiconductor memory further provided. A booster circuit for boosting a power supply voltage to a predetermined boosted voltage; a memory cell as a memory block; a driver driven by the boosted voltage to access the memory cell; and data related to the address based on data from an external address. A semiconductor memory comprising at least an address decoder for selectively driving a driver corresponding to
A semiconductor memory, wherein the memory block uses the booster circuit as a power supply source and includes a level shifter for converting an input signal into a voltage by the boosted voltage.

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