JP2004241045A - Nonvolatile semiconductor storage device - Google Patents

Abstract

Conventionally, a write / erase time (number of pulse applications) at which verification is completed differs for each nonvolatile semiconductor memory device. Therefore, when two or more nonvolatile semiconductor memory devices are measured simultaneously, hardware outside the device is required. -The software configuration becomes complicated.
A gate 21 and a gate control circuit 22 are provided for an operation such as a write / erase / reverse operation for changing a threshold value of a memory cell accompanied by a verify operation. The pulse P1 is applied to the memory cell at the corresponding address in the memory cell array 1. When the write completion determination unit 23 detects a successful verification, the gate 21 is closed in response to the write completion signal P3, and the pulse to the memory cell is output. Prohibit application.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device having a memory cell structure including a floating gate and a control gate, and capable of changing a threshold voltage of a memory cell according to an amount of charge stored in the floating gate.
[0002]
[Prior art]
A memory cell in a non-volatile semiconductor memory device includes a floating gate that stores charge on a semiconductor substrate via a first insulating film, a control gate disposed on the floating gate via a second insulating film, and a floating gate. It has source / drain regions formed on the semiconductor substrate on both sides of the gate, and can be electrically written / erased. In a nonvolatile semiconductor memory device in which such memory cells are arranged in a matrix, at the time of each operation of changing the threshold voltage of a memory cell such as writing and erasing, the writing and erasing operations are performed for a reference time (number of times). After the execution, the verify determination means detects whether the threshold voltage of the memory cell has reached a preset threshold voltage. If the threshold voltage has not been reached, the write / erase operation is executed again and the verify determination means The write / erase operation is completed by executing a series of operations of detecting a predetermined number of times.
[0003]
FIG. 8 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to the related art. The memory cell array 1 is configured by arranging memory cells each having a control gate and a floating gate in a matrix. The control gate of the memory cell is connected to a word line in the row direction, and is selected by the row decoder 2. The drain of the memory cell is connected to a bit line, and is connected to a Y gate 4 that performs a switching operation according to a selection signal of the column decoder 3. The Y gate 4 is connected to a data input / output buffer 7 via a sense amplifier 5 or a data latch 6 according to a selection signal, and further connected to an input / output port 51. When the sense amplifier 5 driven by the command decoder 9 is driven, the output of the sense amplifier 5 is stored in the output status 8 via the data input / output buffer 7 and output to the verify output port 52. The source of the memory cell is connected to the source line, and the source line is selected by the source selector 10. The row decoder 2, the column decoder 3, and the source selector 10 are controlled by an address decoder 11 that decodes an address signal input from an address input port 53. The power supply Vdd is connected to the boost generator 12, and the high voltage generated by the boost generator 12 is applied to the source line of the memory cell via the source selector 10 and to the word line of the memory cell via the row decoder 2. Supplied to The signals of the write pulse input port 54, the reset port 55, and the mode setting port 56 are transmitted to the command decoder 9, and the main internal control signal is generated by the command decoder 9.
[0004]
At the time of a write operation, data provided from the input / output port 51 to the data input / output buffer 7 is temporarily stored in the data latch 6, and further selects a bit line of a memory cell to be written via the Y gate 4. The word line and the source line of the memory cell to be written are selected by the row decoder 2 and the source selector 10, respectively, and the electron is applied to the floating gate of the memory cell for the time during which the write pulse P1 from the write pulse input port 54 becomes active. Is injected to perform a write operation.
[0005]
The completion of the write operation is determined by a write verify operation after the write operation. In this case, the cell current of the memory cell selected by the row decoder 2 and the source selector 10 flows through the bit line, and is determined by the sense amplifier 5 via the Y gate 4. The determination result is transmitted to the input / output port 51 via the data input / output buffer 7 and is compared with the stored value of the data latch 6 by the output status 8. If the results match, the write is completed. The signal P2 becomes "1", and the writing is completed. If the results do not match, the write completion signal P2 remains "0", and the write is not completed. If the writing has not been completed, the writing operation is performed again.
[0006]
The write operation and the write verify operation are repeated a predetermined number of times. If the write operation is not completed even after the maximum number of write operations, it is determined that the write operation is not possible.
[0007]
Generally, the erase operation is performed by applying an electric field for emitting electrons from the floating gate of the memory cell selected by the source selector 10 and the row decoder 2, and the end of the erase operation is determined by the erase verify. It is performed by operation. The erase verify operation is similar to the write verify operation except that the voltage applied to the word line, the load circuit connected to the sense amplifier 5, and the data in the data latch 6 are initialized to "1". different. The relationship between the erase operation and the erase verify operation is the same as the relationship between the write operation and the write verify operation described above.
[0008]
In the case of erasing a memory cell, there is a case where the threshold voltage of the memory cell becomes negative at the completion of erasing due to manufacturing conditions. When such a memory cell exists, the current of the memory cell always flows through the bit line in a read operation or the like. Therefore, the current of the memory cell in the “0” data state existing on the same bit line is sensed. It cannot be distinguished by the amplifier 5 and causes an error in data reading. Therefore, a reverse operation of performing weak writing and shifting the threshold voltage of the memory cell from a negative state to a positive state is required. The reverse operation is performed only on memory cells having a negative threshold value, so that the potential of the word line and the bit line is set lower than that in the write operation. In this case, since a constant potential is applied to all the memory cells connected to the selected word line and bit line, the threshold voltage of the memory cell may slightly change. Therefore, the reverse operation is performed for the minimum necessary time. The determination of the completion of the reverse operation is performed by a reverse verify operation similar to the write verify operation. However, the voltage applied to the word line, the load circuit connected to the sense amplifier 5, and the data in the data latch 6 are initialized to "0".
[0009]
FIG. 9 is a flowchart showing an operation at the time of writing in the conventional nonvolatile semiconductor memory device. In FIG. 9, the determination as to whether or not the writing has been completed is performed in the verification. The sum of the write pulse widths required until the writing is actually completed is greatly affected by the manufacturing conditions when manufacturing the nonvolatile semiconductor memory device, and differs for each memory cell. Further, when writing is performed with the minimum pulse width or more, the threshold value of the memory cell is changed more than necessary. As a result, adverse effects on memory retention, such as an increase in the internal electric field beyond a specified level, occur. Therefore, in the prior art, conditional branch processing in verification has been realized using hardware and software outside the apparatus.
[0010]
[Patent Document 1]
JP-A-10-125092 (pages 4 to 5, FIG. 1)
[0011]
[Problems to be solved by the invention]
As a first problem, in the conventional nonvolatile semiconductor memory device, the write / erase time for completing the verification differs for each nonvolatile semiconductor memory device for the above-described reason, but when two or more nonvolatile semiconductor memory devices are measured simultaneously. However, there is a problem that the hardware / software configuration outside the device becomes complicated. Therefore, it is a first object of the present invention to easily realize a write / erase operation for simultaneous measurement of a plurality of nonvolatile semiconductor memory devices by a circuit configuration inside the device.
[0012]
As a second problem, in the conventional nonvolatile semiconductor memory device, there is a problem that the number of times of writing / erasing cannot be determined for each device due to a difference in manufacturing conditions. Accordingly, a second object of the present invention is to realize acquisition of the number of times of writing / erasing for each nonvolatile semiconductor memory device even in simultaneous measurement of a plurality of devices.
[0013]
The third problem is that, despite the fact that the number of times of writing / erasing differs for each device, writing / erasing is performed at the maximum number of times determined by the product specifications. There is a problem that the writing / erasing time is longer than the writing / erasing time determined by the characteristics. Accordingly, a third object of the present invention is to shorten the write / erase time.
[0014]
[Means for Solving the Problems]
In order to solve the above problems, the present invention takes the following measures.
[0015]
As a first solution, a nonvolatile semiconductor memory device according to the present invention applies a pulse to each memory cell of a memory cell array, performs a verify determination based on detection of a current flowing through the memory cell, A non-volatile semiconductor memory device that outputs a completion signal, wherein the gate is inserted into an input path of the pulse to the memory cell array, the gate is turned on at an initial stage of pulse application, and the gate is controlled based on the completion signal. And a gate control circuit that closes the gate. Here, the pulse may be a write pulse or an erase pulse.
[0016]
The operation of this configuration is as follows. The gate control circuit conducts verification at the beginning of the pulse application by applying a pulse for writing or erasing to the memory cell by conducting the gate. If it is determined that the writing or erasing has been completed even once, a completion signal is output, and the gate control circuit closes the gate according to the completion signal. Therefore, even after that, even if a pulse is generated, it is not transmitted to the memory cell. At the beginning of writing or erasing the next address, the gate is turned on again to start the writing or erasing operation.
[0017]
The gate and the gate control circuit described above are provided inside the nonvolatile semiconductor memory device, and are commonly used when two or more nonvolatile semiconductor memory devices having different write / erase times at which verification is completed are simultaneously measured. Even if the simultaneous measurement is performed by the software described above, the application of the pulse is stopped to the recording device that has been successfully verified, and the verification operation is continued as it is for the recording device that has not been successfully verified. Therefore, the actual number of times of pulse application to the memory cell is minimized, and both software and hardware can be simplified. The same applies to the reverse / reverse verify operation.
[0018]
As a second solution, the nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to the first solution, further comprising: counting a pulse passing through the gate; resetting the counter by the completion signal; It is provided with a register that is reset by the initial application and holds the maximum count value of the counter, and an output unit that outputs the maximum count value held in the register to the outside.
[0019]
The operation of this configuration is as follows. The pulse passing through the gate is a pulse for performing an effective operation on the memory cell. The valid pulse passing through the gate is counted by a counter, and the maximum count value is held in a register. The counter is reset in address units, but the register holds the maximum count value.
[0020]
The maximum count value is as follows. Each one of the memory cells has the number of pulses until the verification is successful. In the process of updating the address and applying pulses to successive memory cells, the number of pulses until the verification succeeds in each memory cell becomes n ₁ , N ₂ , N ₃ When it changes like…, n ₁ , N ₂ , N ₃ ... is held in the register. Therefore, even after reaching the last address of the memory cell array, the register holds the maximum count value. This maximum count value can be taken out. The maximum count value at the end of the measurement is usually smaller than the maximum number determined by the product specifications.
[0021]
When simultaneously measuring a plurality of nonvolatile semiconductor memory devices, the counting operation and the maximum count value holding operation are performed independently of each other by a plurality of devices. Therefore, the maximum count value at the end of measurement reflects a state unique to each device. By using this solution, the number of times of writing / erasing for each nonvolatile semiconductor memory device can be correctly obtained.
[0022]
As a third solution, in the nonvolatile semiconductor memory device according to the present invention, in the second solution, the memory cell array is divided into a normal sector and an information sector, and After the number of times of writing is stored in the information sector, when the next pulse is applied, the maximum number of times of writing stored in the information sector is read out and set as the maximum value of the number of loops of the write pulse.
[0023]
The operation of this configuration is as follows. As the maximum number of times of writing, the maximum number of times of writing in the history stored in the information sector of the memory cell array is read and used. The maximum number of times of writing is the minimum number of times of writing obtained by actual measurement, which is It is smaller than the maximum number of times of writing determined by the product specification. Therefore, the number of write loops can be further reduced, and as a result, the write operation can be performed at higher speed.
[0024]
Then, at the time of simultaneous measurement of a plurality of nonvolatile semiconductor memory devices, the largest maximum number of times of each of the maximum number of times of writing is set as the maximum number of times of loop. As a result, measurement can be performed with a minimum number of necessary writing times in a plurality of devices.
[0025]
As a fourth solution, in the nonvolatile semiconductor memory device according to the present invention, in the above second solution, the memory cell array is divided into a normal sector and an information sector. An address register that holds the address of the memory cell corresponding to the maximum number of erases, stores the maximum number of erases held in the register in the information sector after the final address, and the address register indicates After the address corresponding to the maximum number of erasures is stored in the sector, when the next erasure pulse is applied, the maximum number of erasures stored in the information sector is read out and set as the maximum number of erasure pulse application loops. At the same time, the address corresponding to the maximum number of erasures stored in the information sector is read out and verified. It is set as the representative address Lee determination.
[0026]
The operation of this configuration is as follows. As the maximum number of erasures, the maximum number of erasures in the history stored in the information sector of the memory cell array is read and used. The maximum number of erasures is the minimum number of erasures required by actual measurement. It is smaller than the maximum number of erasures determined by the product specifications. Therefore, the number of erase loops can be further reduced, and as a result, the erase operation can be performed at higher speed. In addition, by performing the verify determination on the memory cell at the representative address, accurate and high-speed verify determination can be performed.
[0027]
Then, at the time of simultaneous measurement of a plurality of nonvolatile semiconductor memory devices, the largest maximum number of erasures among the maximum number of erasures is set as the maximum number of loop times. As a result, measurement can be performed with a minimum number of necessary erasures in a plurality of devices.
[0028]
That is, the erasing operation can be significantly simplified, and the erasing time can be shortened.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the drawings.
[0030]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. In FIG. 1, a is a circuit main part, 20 is a control circuit, 21 is a gate, and 22 is a gate control circuit. The circuit main part a is common to the circuit in FIG. 8 of the prior art. Therefore, the same reference numerals are given to the same portions, and the detailed description is omitted. The control circuit 20 includes a gate 21 and a gate control circuit 22. The gate 21 of the control circuit 20 is inserted in the path for inputting the write pulse P1 to the command decoder 9 in the circuit main part a. The gate control circuit 22 receives the write pulse P1 and the write completion signal P3 from the write completion determination unit 23, and controls opening and closing of the gate 21. The write completion determining section 23 corresponds to the output status 8.
[0031]
When the write pulse P1 is input, the gate control circuit 22 becomes active and sets the gate 21 to the conductive state. The write pulse P1 becomes the write pulse P1a through the gate 21, and is transmitted to the command decoder 9 of the circuit main part a. Given. As a result, writing to the memory cell at the current address in the memory cell array 1 is performed, and then write verification is performed. If the writing to the memory cell is not successful, the state of the write completion determination unit 23 is not inverted, so that the gate control circuit 22 keeps the same state and the gate 21 keeps the conduction state. Since the gate 21 is conducting, the next write pulse P1 is given to the command decoder 9. On the other hand, when the writing to the memory cell is successful, the state of the write completion determination unit 23 is inverted, and the gate control circuit 22 is inverted by the write completion signal P3, so that the gate 21 is switched to the non-conductive state. Therefore, even if the next write pulse P1 is input, it is not supplied to the command decoder 9, and no further write / write verify operation is performed on the memory cell at the current address.
[0032]
FIG. 2 shows a case where the first nonvolatile semiconductor memory device 100 and the second nonvolatile semiconductor memory device 200 are measured at the same time. It is assumed that the first nonvolatile semiconductor memory device 100 and the second nonvolatile semiconductor memory device 200 are performing write / write verify operations on memory cells at the same address. That is, the write pulse P1 is commonly applied to the same address.
[0033]
It is assumed that the first non-volatile semiconductor storage device 100 of the two storage devices 100 and 200 has succeeded in writing first. In this case, in the first non-volatile semiconductor storage device 100, the gate 21 is switched to non-conduction, whereas in the second non-volatile semiconductor storage device 200, the writing has not been successful yet. Keeps the conductive state, and the write pulse P1 is continuously applied to the memory cell. In the second nonvolatile semiconductor memory device 200, when the writing of the above-mentioned address to the memory cell is successful, the write completion determining section 23 is inverted, and the gate 21 is switched to the non-conductive state via the gate control circuit 22.
[0034]
When the number of write / write verify operations for one address reaches the maximum number determined in advance by the product specification, switching to the next address is performed. As a result, the gate control circuits 22, 22 of both storage devices 100, 200 are both reset, and the gates 21, 21 both return to the conductive state.
[0035]
FIG. 3 is a flowchart of software for controlling the write / write verify operation. In step S1, an initial address in the memory cell array 1 is set, and in step S2, write data is set in the data latch 6. In step S3, a variable of the number of times of writing is initialized, and in step S4, a writing pulse P1 is generated. Next, in step S5, the variable of the number of times of writing is incremented, and in step S6, it is determined whether or not the number of times of writing has reached the maximum number of times of writing. If the number has not reached, the process returns to step S4 to repeat the same processing. However, when the maximum number of times of writing has been reached, the process proceeds to step S7, the address is incremented, and the process proceeds to the next address. Then, in step S8, it is determined whether or not the final address has been reached. If not, the process returns to step S2, but if the final address has been reached, the process proceeds to step S9. In step S9, a write verify is executed. As a result, when the writing is successful, the process proceeds to step S10, and the process of the normal end of the writing operation is performed. On the other hand, when the writing is not successful, the process proceeds to step S11. Then, a process of abnormal termination of the write operation is executed.
[0036]
In the above description, steps S2 to S9 mean that the write / write verify operation is performed up to the maximum number of times for each address, the address is incremented to the last address, and the write verify is performed last. The difference from the prior art is that the write verification is performed at the final stage. Regardless of the success or failure of the writing, the writing pulse is transmitted to the same address up to the maximum number of times. However, whether the voltage is applied to the memory cell is different. The gate 21 is kept conductive until the writing is successful, but once the writing is successful, the gate 21 is switched to the non-conductive state, and the application of the write pulse to the memory cell is stopped.
[0037]
Even if the two storage devices 100 and 200 are measured simultaneously by common software, the application of the write pulse P1 is stopped to the recording device that has succeeded in writing, and the write / write operation is directly performed on the unsuccessful recording device. The write verify operation is continued. Therefore, the application of the write pulse to the memory cell is minimized, and the software and hardware can both be simplified.
[0038]
The erase / erase verify operation and the reverse / reverse verify operation can be controlled by the same operation and flow.
[0039]
(Embodiment 2)
FIG. 4 is a block diagram showing a configuration of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. In FIG. 4, 24 is a counter, 25 is a comparison circuit, 26 is a transfer circuit, 27 is a register, and 28 is a buffer. Other configurations are the same as those in FIG. 1 in the first embodiment, and therefore, the same portions are denoted by the same reference numerals and description thereof will be omitted.
[0040]
When the write / write verify operation for the memory cell at the initial address is started, the counter 24 and the register 27 are reset, and the counter 24 starts counting up the write pulse P1a passing through the gate 21. The count value of the counter 24 is given to the comparison circuit 25 and the transfer circuit 26. The comparison circuit 25 compares the count value from the counter 24 with the maximum count value from the register 27, and gives a transfer command to the transfer circuit 26 only when the former is larger. Upon receiving the transfer command, the transfer circuit 26 transfers the count value from the counter 24 to the register 27. Therefore, the register 27 holds the maximum value of the count value of the write pulse P1a passing through the gate 21 counted by the counter 24 until reaching the final address. The maximum count value of the register 27 is sent from the output port 57 to the external CPU via the buffer 28.
[0041]
The counter 24 stops counting up according to the write completion signal P3 from the write completion determination unit 23. That is, the counter 24 counts the number of times of writing until the writing is successfully completed. The counter 24 is reset by updating the next address, but the register 27 is not reset. Therefore, the register 27 holds the maximum count value until the measurement is completed. By reading the maximum count value of the register 27 after the measurement is completed, the maximum number of times of writing in the nonvolatile semiconductor memory device can be confirmed.
[0042]
The same applies to the erase / erase verify operation and the reverse / reverse verify operation.
[0043]
(Embodiment 3)
FIG. 5 is a block diagram showing a configuration of the nonvolatile semiconductor memory device according to the third embodiment of the present invention. In FIG. 5, reference numeral 29 denotes an address register. Further, the memory cell array 1 in the circuit main part a is logically divided into a plurality of areas, and is usually a sector 1a and an information sector 1b. Usually, there are a plurality of sectors 1a, and at least one information sector 1b is required. An address signal is input to the input side of the address register 29, the data input / output buffer 7 is connected to the output side, and a control signal for the address register 29 is output from the comparison circuit 25. Other configurations are the same as those in FIG.
[0044]
As described in the second embodiment, when performing the write operation, the maximum count value is held in the register 27. In the present embodiment, at the end of the first writing, the CPU writes the maximum count value output from the register 27 via the buffer 28 to the information sector 1b of the memory cell array 1. The operation is performed as follows.
[0045]
The address register 29 is cleared by the first write pulse P1a passing through the gate 21, and holds the address signal at that time in synchronization with a transfer command from the comparison circuit 25. The CPU controls the data input / output buffer 7 to write the maximum count value from the register 27 to the information sector 1b at the end of write / write verify to all addresses. Thus, the maximum count value can be stored in the information sector 1b in a nonvolatile manner. Further, the maximum count value can be read from the information sector 1b and used at any time after the power is turned on.
[0046]
FIG. 6 is a flowchart showing a write operation of the nonvolatile semiconductor memory device according to the third embodiment. In step S21, the maximum number of times of writing stored in the information sector 1b of the memory cell array 1 is read, and the variable w _max Substitute for In step S22, an initial address in the memory cell array 1 is set, and in step S23, write data is set in the data latch 6. In step S24, a variable of the number of times of writing is initialized, and in step S25, a writing pulse P1 is generated. Next, in step S26, the variable of the number of writes is incremented, and in step S27, the number of writes is equal to the maximum number of writes w set in step S21. _max It is determined whether or not has been reached. If the number has not reached, the process returns to step S25 to repeat the same processing. However, if the maximum number of times of writing has been reached, the process proceeds to step S28, the address is incremented, and the process proceeds to the next address. Then, it is determined in step S29 whether or not the last address has been reached. If not, the process returns to step S23, but if the last address has been reached, the process proceeds to step S30. In step S30, a write verify operation is performed. As a result, when the writing is successful, the process proceeds to step S31, and the process of the normal end of the writing operation is performed. When the writing is not successful, the process proceeds to step S32. Then, a process of abnormal termination of the write operation is executed.
[0047]
According to this control method, the maximum number of writes in the history stored in the information sector 1b of the memory cell array 1 is read and used as the maximum number of writes used in step S27, and the maximum number of writes is obtained by actual measurement. Is the minimum required number of times of writing, which is smaller than the maximum number of times of writing determined in advance by product specifications. Therefore, the number of loops in steps S25 to S27 can be reduced as compared with the first embodiment, and as a result, the write operation can be performed at higher speed.
[0048]
Then, at the time of simultaneous measurement of a plurality of nonvolatile semiconductor memory devices, the largest maximum number of times of each of the maximum number of times of writing is set as the maximum number of times of loop. As a result, measurement can be performed with a minimum number of necessary writing times in a plurality of devices.
[0049]
The method according to the present embodiment can be used for a reverse operation and a reverse verify operation. When the erasing operation is performed, the maximum number of erasures of the nonvolatile semiconductor memory device is stored in the register 27 as described above, and the address value requiring the maximum number of erasures is stored in the address register 29.
[0050]
Specifically, the address register 29 is cleared by the first erase pulse P1a passing through the gate 21, and holds the address signal at that time in synchronization with a transfer command from the comparison circuit 25. The CPU controls the address register 29 and the data input / output buffer 7 to write the address indicated by the address register 29 into the information sector 1b at the end of erasure / erase verification for all addresses. Also, the maximum count value from the register 27 is written. As a result, the maximum erase count and the address corresponding to the maximum erase count can be stored in the information sector 1b in a nonvolatile manner. Also, after power-on, the maximum number of times of erasure and the corresponding address can be read from the information sector 1b and used at any time.
[0051]
FIG. 7 is a flowchart showing an erasing operation of the nonvolatile semiconductor memory device according to the third embodiment. In step S41, the maximum number of erasures stored in the information sector 1b of the memory cell array 1 is read, and a variable e _max Substitute for In step S42, reading and setting of an erase address in the memory cell array 1 are performed. In step S43, a variable of the number of erases is initialized, and in step S44, an erase pulse is generated. Next, in step S45, the variable of the number of times of erasing is incremented. In step S46, the number of times of erasing is equal to the maximum number of times of erasing e set in step S41. _max It is determined whether or not has been reached. If the number has not reached, the process returns to step S44 to repeat the same processing. However, if the maximum number of erasures has been reached, the process proceeds to step S47 to execute erasure verification. Then, the process of terminating the erase operation normally is performed. If the erase operation has not been successful, the process proceeds to step S49 to execute the process of terminating the erase operation abnormally.
[0052]
According to this control method, the erasing operation can be significantly simplified, and the erasing time can be shortened.
[0053]
At the time of simultaneous measurement of a plurality of nonvolatile semiconductor memory devices, the same effect as described above can be expected by using the largest erase count value among the respective erase counts as a representative value.
[0054]
【The invention's effect】
According to the present invention, even when a plurality of nonvolatile semiconductor memory devices are simultaneously measured by common software, the application of the pulse is stopped to the recording device that has been successfully verified, and the pulse application is stopped for the recording device that has not been successfully verified. In other words, by continuing the verify operation as it is, there is no need to control the number of times of pulse application to the nonvolatile semiconductor memory device that succeeds in verifying relatively quickly. Optimum pulse application can be performed, and the hardware and software configuration for simultaneous measurement can be greatly simplified.
[0055]
In addition, it is possible to easily obtain different characteristic values for the number of times of writing and the number of times of erasing for each nonvolatile semiconductor memory device, which is useful for grasping a lot tendency and analyzing a yield.
[0056]
Further, since writing / erasing can be performed in a state where the number of times of writing / erasing different for each nonvolatile semiconductor memory device is individually optimized, rewriting time can be significantly reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a schematic configuration diagram showing a case where two non-volatile semiconductor storage devices are simultaneously measured in the first embodiment of the present invention;
FIG. 3 is a flowchart showing a write / write verify operation of the nonvolatile semiconductor memory device according to the first embodiment of the present invention;
FIG. 4 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention;
FIG. 5 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a third embodiment of the present invention.
FIG. 6 is a flowchart showing a write / write verify operation of the nonvolatile semiconductor memory device according to the third embodiment of the present invention;
FIG. 7 is a flowchart illustrating an erase / erase verify operation of the nonvolatile semiconductor memory device according to the third embodiment of the present invention;
FIG. 8 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to the related art.
FIG. 9 is a flowchart showing a write / write verify operation of a conventional nonvolatile semiconductor memory device;
[Explanation of symbols]
1 Memory cell array
1a Normal sector
1b Information sector
2 row decoder
3 column decoder
4 Y gate
5 sense amplifier
6 Data latch
7 Data input / output buffer
8 Output status
9 Command decoder
10. Source selector
11 Address decoder
12 Boost generator
20 control circuit
21 Gate
22 Gate control circuit
23 Write Completion Judgment Unit
24 counter
25 Comparison circuit
26 transfer circuit
27 registers
28 buffers
29 Address Register
51 I / O ports
52 Verify output port
53 Address input port
54 Write pulse input port
55 Reset port
56 Mode setting port
57 output port
100 First nonvolatile semiconductor memory device
200 Second nonvolatile semiconductor memory device
a Circuit main part
P1 write pulse
P1a Write pulse through gate
P2 write completion signal
P3 Write completion signal from write completion determination unit

Claims (4)

A non-volatile semiconductor memory device that applies a pulse to each memory cell of a memory cell array, performs a verify determination based on detection of a current flowing through the memory cell, and outputs a completion signal when the verification is successful; And a gate control circuit that conducts the gate at an initial stage of pulse application and closes the gate based on the completion signal. Semiconductor storage device. A counter that counts pulses passing through the gate and is reset by the completion signal;
A register that is reset by the initial application of the pulse and holds a maximum value of the count value of the counter;
2. The nonvolatile semiconductor memory device according to claim 1, further comprising: an output unit that outputs a maximum count value held in said register to outside. The memory cell array is divided into normal sectors and information sectors,
After the maximum number of write times stored in the register is stored in the information sector, at the time of the next pulse application, the maximum number of write times stored in the information sector is read out and set as the maximum number of write pulse loop times. 3. The nonvolatile semiconductor memory device according to claim 2, wherein: The memory cell array is divided into normal sectors and information sectors,
Furthermore, an address register that is reset by the initial application of the erase pulse and holds the address of the memory cell corresponding to the maximum erase count is provided.
After the last address, the maximum number of erasures held in the register is stored in the information sector, the address corresponding to the maximum number of erasures indicated by the address register is stored in the sector, and then the next erase pulse is applied. At this time, the maximum number of erases stored in the information sector is read and set as the maximum value of the number of loops of erase pulse application, and an address corresponding to the maximum number of erases stored in the information sector is read to perform a verify judgment. 3. The nonvolatile semiconductor memory device according to claim 2, wherein the non-volatile semiconductor memory device is set as a representative address.

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