JP2004247445A - Nonvolatile memory element and manufacturing method of semiconductor memory device as well as nonvolatile memory element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an MONOS type or an MNOS type nonvolatile memory element capable of arbitrarily setting the retaining characteristic of data with a high accuracy, and to provide the manufacturing method thereof. <P>SOLUTION: The nonvolatile memory element 3 is provided with a gate electrode 16 via an insulating film 15a in which a first potential barrier layer 12a, an electric charge accumulating layer 13 and a second potential barrier layer 14 are laminated sequentially on a semiconductor substrate 11 through a gate electrode 16. Nitrogen is contained in the potential barrier layer 12a and the data retaining time is arbitrarily set by the containing amount of the nitrogen. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile memory element and a method of manufacturing the same, and more particularly, to a nonvolatile memory element in which stored data is erased when a set retention time has elapsed, and a method of manufacturing the same.
[0002]
[Prior art]
A MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type or MNOS (Metal-Nitride-Oxide-Semiconductor) type nonvolatile memory element has a lower driving voltage than a nonvolatile memory element provided with a floating gate. Application to various electronic devices is expected.
[0003]
FIG. 8 shows a cross-sectional configuration diagram of a MONOS type nonvolatile memory element among such nonvolatile memory elements. As shown in this figure, a MONOS nonvolatile memory element 1 has a semiconductor substrate 11 made of silicon, a first potential barrier layer 12 made of silicon oxide (Oxide), and a charge storage layer made of silicon nitride (Nitride). An insulating film 15 is formed by laminating a second potential barrier layer 14 made of silicon oxide (Oxide) and a second potential barrier layer 13 in this order, and a gate electrode 16 is provided on the insulating film 15. The LDD diffusion layer 17 and the source / drain diffusion layer 18 are provided on the surface layer of the semiconductor substrate 11 below both sides of the gate electrode 16 from the gate electrode 16 side. Further, an insulating side wall 19 for determining the width of the LDD diffusion layer 17 is provided on the side wall of the gate electrode 16 and above the LDD diffusion layer 17 to constitute a MOS transistor.
[0004]
In the MONOS type nonvolatile memory element thus configured, the word line is connected to the gate electrode 16, the bit line is connected to the source / drain diffusion layer 18, and the second potential barrier layer of the charge storage layer 13 is formed. Charges are accumulated as data on the 14 side. Then, the threshold voltage is shifted according to the presence or absence of the charges existing in the charge storage layer 13, and the shifted threshold voltage value is made to correspond to the write and read signals.
[0005]
For example, when the transistor portion is an NMOS and electrons are stored in the charge storage layer 13, the threshold voltage has shifted in the positive direction. At the time of reading, a gate voltage is applied to the corresponding element. However, since electrons are stored in the charge storage layer 13 and the threshold voltage is increased, a current flows between the source and drain diffusion layers 18. Not flowing. Conversely, when holes are stored in the charge storage layer 13, the threshold voltage is shifted in the negative direction, so that a current flows between the source / drain diffusion layers 18 due to the gate voltage at the time of reading. Flows. It is the basic operation principle of the nonvolatile memory element that the current flows and does not flow correspond to "0" and "1". The MNOS nonvolatile memory element has a configuration in which a gate electrode 16 is provided directly on the charge storage layer 13 and charges are stored on the first potential barrier layer 12 side of the charge storage layer 13.
[0006]
In the nonvolatile memory element having such a configuration, a configuration in which a charge storage layer made of aluminum oxide is provided in place of the charge storage layer 13 made of silicon nitride for the purpose of improving the charge retention characteristics has been proposed (for example, See Patent Document 1 below).
[0007]
[Patent Document 1]
JP 2002-368142 A
[0008]
By the way, in the MONOS type or MNOS type nonvolatile memory element having the above configuration, the element performance such as the data holding time and the data erasing time is controlled by the thickness of each layer constituting the insulating film 15. . FIG. 9 shows, as an example, (a) data retention time (Retention time) with respect to the thickness (Tunnel Oxide thickness) of the first potential barrier layer made of silicon oxide in the MONOS type nonvolatile memory element. And (b) Erase time. As shown in these figures, it is understood that the data retention time and the data erase time increase as the thickness of the first potential barrier layer increases.
[0009]
[Problems to be solved by the invention]
However, as described above, the control of the performance of the MONOS-type or MNOS-type nonvolatile memory element by the thickness of each layer constituting the insulating film sandwiched between the semiconductor substrate and the gate electrode is extremely unstable. there were. That is, when such control is performed, it is necessary to control each layer constituting the insulating film with high accuracy in a thin range of several nm to several tens of nm, so that it is difficult to perform stable control.
[0010]
Further, changing the film thickness of each layer forming the insulating film involves changing the processing conditions of all the layers forming the insulating film. In addition, since the width of the sidewall that determines the width of the LDD diffusion layer changes with the change in the thickness of the insulating film, the design of the LDD diffusion layer also needs to be changed. For this reason, there is a problem that the design management corresponding to the performance of the nonvolatile memory element becomes complicated, and it is difficult to cope with it at the manufacturing site.
[0011]
Further, in the case of forming a semiconductor memory device in which nonvolatile memory elements having different performances are formed over the same substrate, the nonvolatile memory elements having different performances have different thicknesses of insulating films in the respective nonvolatile memory elements. It becomes necessary to separately form LDD diffusion layers for each case. For this reason, the number of manufacturing steps is increased, which is a factor of increasing the product cost.
[0012]
Therefore, the present invention provides a MONOS-type or MNOS-type nonvolatile memory element capable of arbitrarily setting data holding characteristics with high accuracy, a semiconductor memory device using the same, and a method of manufacturing the nonvolatile memory element. The purpose is to provide.
[0013]
[Means for Solving the Problems]
A non-volatile memory element according to the present invention for achieving the above object is a non-volatile memory element comprising a gate electrode provided on a semiconductor substrate via an insulating film in which a potential barrier layer and a charge storage layer are stacked in this order. An element, characterized in that nitrogen is contained in the potential barrier layer, and the data retention time is arbitrarily controlled by the nitrogen content.
[0014]
In the nonvolatile memory element having such a configuration, the data retention time is controlled by the content of nitrogen in the potential barrier layer. Here, the retention time of data in the nonvolatile memory element has a good dependence on the nitrogen content in the potential barrier layer, and the nitrogen content in the potential barrier layer has very good controllability. . Therefore, the data retention time is controlled with higher precision than in a nonvolatile memory element whose element performance is controlled by adjusting the thickness of each layer such as a potential barrier layer and a charge storage layer.
[0015]
Further, the present invention is a semiconductor memory device provided with a plurality of such nonvolatile memory elements, wherein at least one of the nonvolatile memory elements contains nitrogen in a potential barrier layer, and includes The data retention time of the nonvolatile memory element containing nitrogen is arbitrarily set according to the content of nitrogen.
[0016]
In the semiconductor memory device having such a configuration, the use of the above-mentioned nonvolatile memory element allows the nitrogen barrier in the potential barrier layer to be provided even when nonvolatile memory elements having various element performances are provided on the same substrate. Since the element performance (data retention time) is controlled by the content, the thickness of the insulating film including the potential barrier layer is kept constant regardless of the performance (data retention time) of the nonvolatile memory element. Dripping. Therefore, non-volatile elements having different performances while providing other design values other than the nitrogen content in common are provided on the same substrate.
[0017]
The present invention also relates to a method for manufacturing a nonvolatile memory element having the above-described configuration, wherein the content of nitrogen introduced into the potential barrier layer is determined based on a preset data retention time, Immediately after the formation, the step of introducing the required content of nitrogen into the potential barrier layer is performed.
[0018]
In the manufacturing method having such a configuration, the data retention time is controlled by the content of nitrogen in the potential barrier layer. Therefore, the thickness of the insulating film including the potential barrier layer depends on the performance ( (Data retention time) and is kept constant. Therefore, it is possible to obtain a nonvolatile memory element whose element performance (data retention time) is controlled only by adjusting the nitrogen content with good controllability without changing other design values.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the embodiment of the present invention will be described with reference to a MONOS type nonvolatile memory element as an example, the nonvolatile memory element, a semiconductor memory device using the nonvolatile memory element, and a method of manufacturing the nonvolatile memory element. The manufacturing method of the applied semiconductor memory device will be described in order.
[0020]
<Non-volatile memory element>
FIG. 1 is a schematic sectional view of the nonvolatile memory element according to the embodiment. The difference between the nonvolatile memory element 3 of the embodiment shown in this figure and the conventional nonvolatile memory element described with reference to FIG. 8 is that the first potential barrier layer 12a and the insulation including the first potential barrier layer 12a are provided. The structure of the film 15a is the same, and the other structures are the same. For this reason, the description that overlaps with the related art will be omitted below.
[0021]
That is, the nonvolatile memory element 3 is an insulating film 15a formed by stacking a first potential barrier layer 12a, a charge storage layer 13, and a second potential barrier layer 14 in this order on a semiconductor substrate 11 made of, for example, single crystal silicon. The gate electrode 16 is provided through the gate electrode.
[0022]
Among them, the first potential barrier layer 12a contains nitrogen at a predetermined content, and is, for example, a layer obtained by performing a nitrogen introduction process on a silicon oxide film formed in advance. . In particular, it is assumed that the content of nitrogen in the first potential barrier layer 12a is an amount set by the data retention time required for the nonvolatile memory element 3.
[0023]
The charge storage layer 13 is made of a silicon nitride-based material, specifically, is formed using at least one of silicon nitride, silicon nitride oxide, and silicon fluoronitride. It is configured as a single layer or these layers are appropriately laminated. When the charge storage layer 13 is made of silicon oxynitride and the first potential barrier layer 12a is formed by introducing nitrogen into a silicon oxide film, there is an interface between these layers, so that they are separated as different layers. Is done.
[0024]
The second potential barrier layer 14 is made of, for example, a silicon oxide film.
[0025]
Here, the content of nitrogen in the first potential barrier layer 12a is set as follows based on, for example, the graph of FIG. FIG. 2 shows the threshold voltage of each nonvolatile memory element in which only the content of nitrogen (atoms%, hereinafter simply indicated by%) in the first potential barrier layer 12a is set to each value. It is a graph which shows the time-dependent change of (Threshold Voltage). FIG. 2 shows an example in which the thickness of the first potential barrier layer 12a is 2.6 nm, the thickness of the charge localization layer 13 is 5 nm, and the thickness of the second potential barrier layer 14 is 4 nm.
[0026]
Each upper value in the graph indicates a time-dependent change in the threshold voltage from the time when the charge is stored in the charge storage layer 13, and the threshold voltage gradually decreases from 4 V with time. It is shown. When the threshold voltage is higher than the read voltage (Data Lsot) of 2.5 V, even if the read voltage is applied to the gate electrode, no current flows between the source and the drain. As a result, the data is held. However, after the threshold voltage has dropped to the read voltage (Data Lsot), a current flows between the source and the drain by applying the read voltage to the gate electrode, so that data is erased. .
[0027]
The time during which the data is held as described above, that is, the time during which the threshold voltage decreases to the read voltage (Data Lsot), becomes shorter as the content of nitrogen in the first potential barrier layer 12a increases. I understand.
[0028]
Therefore, for example, when a data retention time limited to 10 years is required for the nonvolatile memory element 3, the nitrogen content in the first potential barrier layer 12 is set to 12%. It shall be. Similarly, if it is limited to 4 months (144 days), it is set to 23%, and if it is limited to about 2 months (58 days), it is set to 26%. When a data retention time of 100 years or more is required, the content of nitrogen in the first potential barrier layer 12 is set to 10% or less. Note that the nitrogen content with respect to the data retention time is a value appropriately selected in the range of 10% to 26% depending on the thicknesses of the first potential barrier layer 12a, the charge storage layer 13, and the second potential barrier layer. .
[0029]
By setting the content of nitrogen in the potential barrier layer 12a to 10% to 26%, a limited time can be set as the data retention time of the nonvolatile memory element 3.
[0030]
According to the nonvolatile memory element 3 configured as described above, the data retention time is controlled by the nitrogen content in the potential barrier layer 12a. As shown in FIG. 2, the data retention time in the nonvolatile memory element 3 has a good dependence on the nitrogen content in the potential barrier layer 12a, and the nitrogen content in the potential barrier layer 12a. Has very good controllability. Therefore, as compared with a conventional nonvolatile memory element in which the element performance is controlled by adjusting the thickness of each layer such as a potential barrier layer and a charge storage layer, the data retention time is controlled with higher precision. The storage element 3 can be obtained.
[0031]
Moreover, the thickness of the insulating film 15a including the potential barrier layer 12a is kept constant irrespective of the data retention time set for the nonvolatile memory element 3. As described above, by keeping the thickness of the insulating film 15a constant, the width of the sidewall 19 provided in a self-aligned manner on the side wall of the insulating film 15a is also kept constant. This also keeps the width of the LDD diffusion layer 17 below the sidewall 19 constant. Therefore, the non-volatile memory element 3 can control the data retention time with high accuracy only by adjusting the nitrogen content with good controllability without changing other design values. Becomes easier.
[0032]
Since a limited time can be set with high precision as the data retention time, this semiconductor storage element can be used as an authentication means for a limited time. For example, an ID card or the like is provided with a plurality of semiconductor storage elements 3 configured with a predetermined limited time as a data holding time as an authentication unit. By storing the ID information in these semiconductor storage elements 3, it is also possible to provide a business model in which the ID card can be used only during the data holding time.
[0033]
FIG. 3 is a graph showing the relationship between the nitrogen content (Nitrogen Concentration) in the first potential barrier layer 12a and the data erase speed (Erase time) in the nonvolatile memory element 3 having the above-described configuration. . As shown in this graph, the data erasing speed increases as the nitrogen content increases, and the data erasing speed can be controlled by the nitrogen content. Therefore, the content of nitrogen in the first potential barrier layer 12a in the nonvolatile memory element 3 can be adjusted so that data is erased at an arbitrary speed.
[0034]
<Semiconductor storage device>
Next, a configuration of a semiconductor storage device using the nonvolatile storage element 3 having such a configuration will be described. The semiconductor memory device includes a plurality of nonvolatile memory elements 3 arranged in a memory area on a semiconductor substrate 11 and a memory for selecting, writing, erasing, and reading any one of the nonvolatile memory elements 3. It comprises a logic transistor circuit and a peripheral circuit such as a circuit for supplying a high voltage.
[0035]
FIG. 4 shows a schematic cross-sectional configuration diagram of such a semiconductor storage device 5.
[0036]
As shown in FIG. 4, in the memory area a in the semiconductor substrate 11, the nonvolatile memory element 3 having the above-described configuration is provided for each active area separated by the element isolation area 31. On the other hand, in the peripheral region b of the same semiconductor substrate 11, the MOS transistor 3b constituting the above-described peripheral circuit is arranged for each active region separated by the element isolation region 31.
[0037]
The MOS transistor 3b includes a gate electrode 16b provided on a semiconductor substrate 11 with a gate insulating film 15b interposed therebetween. On the surface layer of the semiconductor substrate 11 on both sides below the gate electrode 16b, an LDD diffusion layer 17b and a source / drain diffusion layer 18b are provided from the gate electrode 16b side. Further, an insulating sidewall 19b that determines the width of the LDD diffusion layer 17b is provided on the side wall of the gate electrode 16b and above the LDD diffusion layer 17b.
[0038]
The bit line 20 is connected to the source / drain diffusion layer 18 of the nonvolatile memory element 3, and the source / drain electrode 20b is connected to the source / drain diffusion layer 18b of the MOS transistor 3b. .
[0039]
In the semiconductor memory device 5 having such a configuration, the nonvolatile memory elements 3 have different contents according to the data retention time required for each of the plurality of nonvolatile memory elements 3 arranged in the memory area a. May introduce nitrogen.
[0040]
FIG. 5 is an equivalent circuit diagram of a memory cell array in which nonvolatile memory elements 3 arranged in a matrix in a memory area are operably connected in a NOR type in such a semiconductor memory device.
[0041]
As shown in this figure, the gate electrodes of the nonvolatile memory elements 3 arranged in the row direction are connected to the same word lines WL1, WL2,. In the nonvolatile memory element 3 arranged in the column direction, one source / drain diffusion layer is connected to the same bit line BL1a, BL2a,..., And the other source / drain diffusion layer is connected to the same BL1b. , BL2b,...
[0042]
Then, for example, when reading the data of the nonvolatile memory element 3-1, the word line WL1 is accessed and the current flowing between the bit lines BL1a and BL1b is detected to determine "1" or "0".
[0043]
In the semiconductor memory device 5 described with reference to FIG. 4 having such a configuration, by using the nonvolatile memory element 3 having the above-described configuration, various element performances (data retention time) can be provided on the same semiconductor substrate 11. Is provided, the thickness of the insulating film 15a in each nonvolatile memory element 3 is kept constant. Therefore, the non-volatile elements 3 having different element performances (data retention times) are provided on the same semiconductor substrate 11 while sharing other design values other than the nitrogen content, and the functions are enhanced. The manufacturing process of the semiconductor memory device can be simplified.
[0044]
In the above, the embodiment of the semiconductor memory device 5 has been described by exemplifying a NOR type circuit configuration. However, the semiconductor memory device 5 of the present invention can be applied to any circuit configuration such as an AND type, an SSL type, and a NAND type, and the same effects can be obtained.
[0045]
<Method for manufacturing nonvolatile memory element>
Next, a case where the above-described method for manufacturing a nonvolatile memory element is applied to a manufacturing process of a semiconductor memory device having the nonvolatile memory element will be described with reference to a cross-sectional process diagram of FIG.
[0046]
First, as shown in FIG. 6A, an element isolation layer 31 made of silicon oxide is formed on the surface side of a semiconductor substrate 11 made of single crystal silicon by, for example, the LOCOS method. Here, the left side in the drawing separated by the element isolation layer 31 is a memory region a for forming a nonvolatile memory element, and the right side in the drawing is a peripheral region b for forming a peripheral circuit transistor. Further, the element isolation layer 31 may be a trench element isolation.
[0047]
Next, as shown in FIG. 6B, a p-well 33 is formed only in the memory area a. At this time, an impurity is introduced only into the memory region a by a method such as ion implantation while the peripheral region b is protected by a resist film (not shown). Here, an impurity for adjusting the threshold voltage is introduced together with the formation of the p-well.
[0048]
Thereafter, as shown in FIG. 6C, silicon oxide is formed to a thickness of 0.5 to 8.0 nm on the entire surface of the semiconductor substrate 11 by, for example, a thermal oxidation method, and the first potential barrier layer 12 is formed. I do.
[0049]
Next, as shown in FIG. 6D, the first potential barrier layer 12 is subjected to a nitriding treatment to obtain a first potential barrier layer 12a containing nitrogen at a predetermined content. For this nitriding treatment, any treatment method such as heat treatment or plasma treatment may be used, but it is preferable to adopt a method with better controllability of the introduced amount of nitrogen.
[0050]
In addition, the nitrogen content of the first potential barrier layer 12a is obtained by performing preliminary experiments to obtain data as shown in FIG. 2 above, and to store this data and the nonvolatile memory element formed here. From the required data retention time, the nitrogen content is determined. Then, the conditions of the nitriding treatment are set so that the obtained content of nitrogen is introduced into the first potential barrier layer 12a.
[0051]
Next, as shown in FIG. 6E, a charge storage layer 13 made of, for example, silicon nitride is formed on the first potential barrier layer 12a to a thickness of 2 to 16 nm. The charge storage layer 13 can be formed by ordinary CVD or sputtering, but is preferably formed by an atomic layer deposition (ALD) method.
[0052]
Next, as shown in FIG. 7F, by thermally oxidizing the entire surface of the charge storage layer 13 by, for example, a thermal oxidation method, the second potential barrier layer 14 made of silicon oxide is reduced to, for example, about 3 nm to 5 nm. It is formed with a film thickness. Thus, an insulating film 15a composed of the first potential barrier film 12a, the charge storage layer 13 containing nitrogen, and the second potential barrier layer 14 is formed on the semiconductor substrate 11.
[0053]
Next, as shown in FIG. 7G, a gate electrode 16 is formed on the insulating film 15a in the memory area a. Here, first, a gate electrode 16 is formed by depositing a polysilicon film on the insulating film 15a by, for example, a CVD method, and etching the polysilicon film using a resist pattern formed by a photolithography process as a mask. I do. At this time, the insulating film 15a is also processed in the same pattern as the gate electrode 16. At the same time, the semiconductor substrate 11 may be exposed in the peripheral region b. The removal of the insulating film 15a in the peripheral region b may be performed in another step.
[0054]
After the above, as shown in FIG. 7H, a p-well 33b is formed in the peripheral region b. At this time, an impurity is introduced only into the peripheral region b by a method such as ion implantation while the memory region a is protected by a resist film (not shown). Here, an impurity for adjusting the threshold voltage is introduced together with the formation of the p-well 33b.
[0055]
Thereafter, a silicon oxide film is formed on the entire surface by, for example, a thermal oxidation method, and a gate insulating film 15b for a peripheral circuit transistor is formed. At this time, also in the memory region a, a silicon oxide film is formed on the surface of the gate electrode 16 and the surface of the p-well 33.
[0056]
Next, polysilicon is deposited by, for example, a CVD method, and is patterned by a photolithography process to form a gate electrode 16b for a MOS transistor in the peripheral region b.
[0057]
Then, as shown in FIG. 7I, ion implantation is performed using the gate electrodes 16 and 16b as masks to form LDD diffusion layers 17 and 17b containing n-type impurities at a low concentration. Next, silicon oxide is deposited by a CVD method and etched back to form insulating sidewalls 19 and 19b on the side portions of the gate electrodes 16 and 16b. By this etch back, the silicon oxide film on the semiconductor substrate 11 is removed, and the semiconductor substrate 11 is exposed.
[0058]
Thereafter, ion implantation is performed using the gate electrodes 16 and 16b and the side walls 19 and 19b as masks to form source / drain diffusion layers 18 and 18b containing n-type conductive impurities at a high concentration. Thus, the nonvolatile memory element 3 is formed in the memory area a, and the MOS transistor 3b for the peripheral circuit is formed in the peripheral area b.
[0059]
Thereafter, as shown in FIG. 4, the bit line 20 connected to the source / drain 18 of the nonvolatile memory element 3 and the source / drain electrode 20b connected to the source / drain 18b of the MOS transistor 3b are formed. I do. In this case, when the offset insulating films 35, 35b are previously provided on the gate electrodes 16, 16b, the offset insulating films 35, 35b and the side walls 19, 19b are self-aligned with the gate electrodes 16, 16b. A bit line 20 connected to the source / drain diffusion layers 18 and 18b and a source / drain electrode 20b are formed in a state of being electrically insulated. When the offset insulating films 35 and 35b are not provided, an interlayer insulating film made of silicon oxide is formed on the entire surface of the semiconductor substrate 11, and reaches the source / drain diffusion layers 18 and 18b in the interlayer insulating film. A contact hole is opened, and a bit line 20 and a source / drain electrode 20b connected to the source / drain diffusion layers 18 and 18b are formed in the contact hole.
[0060]
As described above, it is possible to obtain the semiconductor memory device 3 having the above-described configuration and the semiconductor memory device 5 including the MOS transistor 3b for the peripheral circuit provided on the same semiconductor substrate 11 together with the semiconductor memory device 3.
[0061]
According to such a manufacturing method, the element performance (data retention time) of the nonvolatile memory element is controlled only by adjusting the nitrogen content with good controllability without changing other design values. Therefore, a nonvolatile memory element whose element performance is controlled with high accuracy can be obtained. In addition, since the thickness of the insulating film 15a is kept constant, the width of the sidewall 19 provided in a self-aligned manner on the side wall of the insulating film 15a is also kept constant. This also keeps the width of the LDD diffusion layer 17 below the sidewall 19 constant.
[0062]
Therefore, the nonvolatile memory element 3 in which only the data retention time is controlled with high accuracy without changing other design values constituting the plurality of nonvolatile memory elements 3 and the MOS transistor 5 is formed. It is easy to respond to a change in the performance of the nonvolatile memory element 3 at the manufacturing site. Further, since it is not necessary to separately form an LDD diffusion layer for each of the nonvolatile memory elements having different performances, it is possible to suppress an increase in the number of manufacturing steps and manufacturing costs.
[0063]
In the above manufacturing method, when the nitriding process shown in FIG. 6D is performed by the thermal nitriding process, the content of nitrogen in the first potential barrier layer 12a of the nonvolatile memory element 3 is set to 20% or less. It is preferable to adjust within the range.
[0064]
This prevents the effect of the thermal nitridation process from affecting the surface of the semiconductor substrate 11 in the peripheral region b, and forms a MOS transistor for a peripheral circuit formed in a step after the formation of the first potential barrier layer 12a. 3b transistor performance can be ensured. That is, when the nitriding treatment shown in FIG. 6D is performed by a thermal nitriding treatment, the nitrogen concentration on the surface of the semiconductor substrate 11 is suppressed by setting the content of nitrogen to 20% or less, and in the subsequent oxidation treatment, Thus, the oxidation rate of the semiconductor substrate 11 is ensured, the thickness of the gate insulating film is easily ensured, and the mobility of carriers in the semiconductor substrate 11 is ensured, so that the performance of the MOS transistor 3b can be maintained.
[0065]
In each of the above embodiments, the case where the nonvolatile memory element 3 is of the MONOS type has been described. However, the same effect can be obtained even if this nonvolatile memory element 3 is of the MNOS type. it can.
[0066]
【The invention's effect】
As described above, according to the nonvolatile memory element of the present invention, the data retention time is controlled by the content of nitrogen in the potential barrier layer, so that the data retention time is controlled with high accuracy. It can be. In addition, since the thickness of the insulating film including the potential barrier layer is kept constant irrespective of the data retention time set for the nonvolatile memory element, it is possible to cope with a change in performance (data retention time). This makes it easy to change the design at the manufacturing site.
[0067]
Further, a semiconductor memory device of the present invention has a structure in which at least one of a plurality of nonvolatile memory elements is a nonvolatile memory element having the above structure, and a data retention time is arbitrarily set depending on a nitrogen content. By doing so, it is possible to provide non-volatile elements having different performances (data retention times) on the same substrate while sharing design values other than the nitrogen content. This facilitates the design of a highly functional semiconductor memory device.
[0068]
Further, the present invention is a method for manufacturing a nonvolatile memory element having the above-described configuration, wherein the content of nitrogen introduced into the potential barrier layer is determined based on a preset data retention time, and the potential barrier layer is formed. Immediately after the formation, the obtained content of nitrogen is introduced into the potential barrier layer, so that the element performance (data retention time) can be improved only by adjusting the nitrogen content with good controllability. It is possible to obtain a nonvolatile memory element controlled with high accuracy.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional configuration diagram of a nonvolatile memory element of the present invention.
FIG. 2 is a graph showing a change over time of a threshold voltage (Threshold Voltage) in a nonvolatile memory element.
FIG. 3 is a graph showing a relationship between a nitrogen concentration in a first potential barrier layer and data erasure in a nonvolatile memory element.
FIG. 4 is a schematic cross-sectional configuration diagram of a storage device using a nonvolatile storage element.
FIG. 5 is an equivalent circuit diagram of a memory area in a storage device using a nonvolatile storage element.
FIG. 6 is a manufacturing process diagram (part 1) of the storage device in the embodiment.
FIG. 7 is a manufacturing process diagram (part 2) of the storage device in the embodiment.
FIG. 8 is a schematic cross-sectional configuration diagram of a conventional nonvolatile memory element.
9A is a graph showing a relationship between a film thickness of a first potential barrier layer and a data retention time in the nonvolatile memory element, and FIG. 9B is a graph showing a film of the first potential barrier layer in the nonvolatile memory element. 9 is a graph showing a relationship between a thickness and a data erasing time.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 3 ... Nonvolatile memory element, 11 ... Semiconductor substrate, 12a ... 1st potential barrier layer, 13 ... Charge accumulation layer, 14 ... 2nd potential barrier layer, 15a ... Insulating film, 16 ... Gate electrode

Claims (6)

A nonvolatile memory element including a gate electrode provided on a semiconductor substrate via an insulating film in which a potential barrier layer and a charge storage layer are stacked in this order,
A nonvolatile memory element, wherein nitrogen is contained in the potential barrier layer, and a data retention time is arbitrarily set depending on the nitrogen content. The nonvolatile memory element according to claim 1,
2. The nonvolatile memory element according to claim 1, wherein a limited time is set as the data retention time. The nonvolatile memory element according to claim 2,
The nonvolatile memory element according to claim 1, wherein a nitrogen concentration in the potential barrier layer is 10% to 26%. The nonvolatile memory element according to claim 1,
The insulating film further includes a potential barrier layer laminated on the charge storage layer, and the predetermined amount of nitrogen is contained in the potential barrier layer on the semiconductor substrate side. Storage element. On a semiconductor substrate, a potential barrier layer and a charge storage layer have a plurality of nonvolatile memory elements provided with a gate electrode through an insulating film stacked in this order,
Nitrogen is contained in a potential barrier layer of at least one of the nonvolatile memory elements;
A semiconductor memory device, wherein a data retention time of a nonvolatile memory element containing nitrogen in the potential barrier layer is arbitrarily set depending on the nitrogen content. A method for manufacturing a nonvolatile memory element, wherein an insulating film in which a potential barrier layer and a charge storage layer are stacked in this order on a semiconductor substrate, and a gate electrode is formed on the insulating film,
The content of nitrogen to be introduced into the potential barrier layer is determined based on a preset data retention time, and the nitrogen having the content is introduced into the potential barrier layer immediately after forming the potential barrier layer. A method of manufacturing a nonvolatile memory element.

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