JP2004265983A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can specify whether failure occurred in which source position of a semiconductor substrate only by checking a semiconductor chip divided from the semiconductor substrate when failure occurs in the semiconductor chip, and to provide its manufacturing method. <P>SOLUTION: In the semiconductor device which can specify a failure occurrence position in a semiconductor substrate 1 after semiconductor chips 2 arranged in a matrix shape in the semiconductor substrate 1 are divided, the semiconductor chip 2 is provided with a circuit 3, a common mark 4 which is formed in a region except the circuit 3 and shows the whole lay out of the semiconductor chips 2 in the semiconductor substrate 1, and an individual mark 5 which is formed in the common mark 4 and shows position of the semiconductor chip 2 in the semiconductor substrate 1. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device that can identify a position on a semiconductor substrate where a defect has occurred when a defect occurs in a semiconductor element divided from the semiconductor substrate.
[0002]
[Prior art]
When a semiconductor chip is shipped to the market and a problem such as quality occurs, it is important to know the lot number and the chip position on the semiconductor substrate in performing a failure analysis and taking a countermeasure.
A semiconductor chip is manufactured by forming a plurality of circuit portions in a matrix on a semiconductor substrate and then dividing the semiconductor substrate along the plurality of circuit portions. Since these semiconductor chips are manufactured in the same pattern, after division, it was not possible to determine where the chip was located on the semiconductor substrate.
[0003]
As a countermeasure against this, Patent Document 1 discloses a pattern in which a plurality of circuit parts are arranged on a transparent glass substrate and identification patterns such as characters and figures different for each of the plurality of circuit parts are provided in a part other than the plurality of circuit parts. When a semiconductor chip is manufactured using a reticle formed in a matrix, the position of each semiconductor chip on the reticle can be identified even after the semiconductor chip is divided from the semiconductor substrate. It is disclosed that it is possible to easily analyze the cause of a defect occurring in a chip.
[0004]
[Patent Document]
JP-A-5-299318 (page 2-3, FIG. 1)
[0005]
[Problems to be solved by the invention]
However, since only the identification pattern indicating the chip position of the semiconductor substrate is formed on the semiconductor chip, if a defective semiconductor chip is found after dividing the semiconductor chip, the location where the semiconductor chip is located is determined by the location of the semiconductor chip. By comparing the defective semiconductor chips, the place where the defective semiconductor chip was arranged for the first time is specified, and the specification has been troublesome. That is, it was not possible to determine where the defective semiconductor chip was located on the semiconductor substrate by merely looking at the defective semiconductor chip.
[0006]
In view of the above, the present invention has been made in view of the above-described problem. When a defect occurs in a semiconductor chip, the defect occurs at any position on the semiconductor substrate just by looking at the semiconductor chip divided from the semiconductor substrate. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can identify the state of the semiconductor device.
[0007]
[Means for Solving the Problems]
According to a first aspect of the present invention, in a semiconductor device capable of specifying a defect occurrence position in the semiconductor substrate after a semiconductor chip arranged in a matrix on a semiconductor substrate is divided, the semiconductor chip includes a circuit unit; A common mark indicating an entire layout of the semiconductor chip in the semiconductor substrate formed in a region other than the circuit section; and an individual mark indicating a position of the semiconductor chip in the semiconductor substrate formed in the common mark. And a semiconductor device having the following.
A second invention is a process for forming a mark layer on a plurality of semiconductor chips formed in a matrix on a semiconductor substrate, and after applying a photoresist on the mark layer, the semiconductor chip in the semiconductor substrate Disposing a first photomask on which a common pattern showing the entire layout of the common pattern is formed above the photoresist, and exposing the first photomask to form a first latent image of the common pattern on the photoresist; A second photomask, which is formed and has an individual pattern indicating the position of the semiconductor chip in the entire layout, is disposed above the photoresist and exposed to light to expose a second latent image between the first latent images of the photoresist. Forming an image and developing the photoresist to form a photoresist pattern and exposing from the photoresist pattern To provide a method of manufacturing a semiconductor device characterized by consisting of a step of forming a separate mark the mark layer to the etched and common marks and the common mark within.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
A semiconductor device according to an embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS.
FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention. 2A and 2B show common marks formed on the semiconductor chip, wherein FIG. 2A is a plan view and FIG. 2B is an enlarged plan view of the common marks and the individual marks. 3A and 3B show a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 3A shows a (mark layer forming step), FIG. 3B shows a (common pattern exposure step), and FIG. (Exposure step), (D) is a sectional view showing (common mark and individual mark formation step). FIG. 4 is a plan view showing common marks and individual marks formed on the semiconductor chip of the first variation. FIG. 5 is a plan view showing a common mark formed on the semiconductor chip of the second variation. FIG. 6 is a plan view showing common marks and individual marks formed on a semiconductor chip of the third variation. FIG. 7 is a plan view showing common marks and individual marks formed on a semiconductor chip of the fourth variation. FIG. 8 is a plan view showing common marks and individual marks formed on a semiconductor chip of the fifth variation. 9A and 9B show a common mark and an individual mark formed on a semiconductor chip of a sixth variation, wherein FIG. 9A is a plan view and FIG. 9B is a cross-sectional view of the MM of FIG.
[0009]
First, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 1, on a semiconductor substrate 1, a plurality of semiconductor chips 2 are formed in a matrix. Then, as shown in FIGS. 2A and 2B, the semiconductor chip 2 has a circuit portion 3 in the center and an entirety of the semiconductor chip 2 formed on the semiconductor substrate 1 in a region other than the circuit portion 3. A common mark 4 indicating a layout and an individual mark 5 indicating a position of the semiconductor chip 2 in the semiconductor substrate 1 are formed in the common mark 4.
[0010]
In FIG. 1, numerals 1, 2,..., 9 are attached from left to right in the horizontal axis direction, and alphabets A, B,. The semiconductor chip 2 is specified by the coordinates of the intersection.
Here, a semiconductor chip specified by (5, A) coordinates is shown.
[0011]
As described above, according to the semiconductor device in the embodiment of the present invention, even if the semiconductor chip 2 is divided from the semiconductor substrate 1, the common mark 4 and the individual mark 5 formed on the semiconductor chip 2 By looking at the semiconductor chip 2, it is possible to specify from which position the semiconductor chip is divided. Therefore, even if a defect occurs in the semiconductor chip 2, the defect analysis can be easily performed, and the quality can be improved.
[0012]
Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. FIG. 3 is a cross-sectional view of only the common mark 4 region other than the circuit section 3 in the semiconductor chip 2 in FIG.
(Mark layer forming step)
As shown in FIG. 3A, a semiconductor substrate 1 on which a plurality of semiconductor chips 2 are formed in advance is prepared. As shown in FIG. 3A, a mark layer 7 made of Al or the like is formed on a lower layer 6 made of SiO _{2 of the} semiconductor substrate 1.
[0013]
(Common pattern exposure process)
Next, as shown in FIG. 3B, after a photoresist 8 is applied on the mark layer 7, a common pattern 9a showing a layout of a plurality of semiconductor chips 2 formed in a matrix on the semiconductor substrate 1 is formed. The formed first photomask 9 is disposed above the photoresist 8 and exposed to form a latent image 8a formed corresponding to the common pattern 9a. Here, the photoresist 8 is a positive photoresist. Therefore, a latent image 8a is formed on the exposed portion.
[0014]
(Individual pattern exposure process)
Subsequently, as shown in FIG. 3C, a second photomask 10 formed in the common pattern 4 and having the individual pattern 10 a indicating the position of the semiconductor chip 2 on the semiconductor substrate 1 is arranged above the photoresist 8. Then, a latent image 8b formed corresponding to the individual pattern 10a is formed between the latent images 8a.
At this time, the exposure of the individual pattern 10a is performed while shifting the second photomask 10 for each position where each semiconductor chip 2 is arranged. Actually, since the semiconductor substrate 1 is mounted on the exposure stage, the second photomask 10 is exposed while shifting the exposure stage at the pitch of the individual pattern 10a in a fixed state.
[0015]
(Common mark and individual mark formation process)
Next, as shown in FIG. 3D, the latent images 8a and 8b are developed to form a photoresist pattern, and the mark layer 7 exposed from the photoresist pattern is etched by a chemical etching method or the like. After forming the common mark 4 and the individual mark 5 in the common mark 4 on the mark layer 7, the semiconductor substrate 1 is divided to manufacture the semiconductor chip 2.
As described above, according to the method for manufacturing a semiconductor device in the embodiment of the present invention, the mark layer 7 is formed, and the common mark 4 and the individual marks 5 are formed in the common mark 4 on the mark layer 7. Therefore, the position of a chip where a defect occurs can be easily specified using a normal process, so that defect analysis and quality improvement can be achieved.
[0016]
In the above description, the (common pattern exposure step) and (individual pattern exposure step) may be performed in reverse order.
Further, the mark layer 7 is formed on the semiconductor substrate 1 in order to form the common mark 4 and the individual mark 5 in the common mark 4. For example, the wiring Al layer used in the process of forming the circuit section 3 is formed by a mark. It may be used instead of the layer 7. By doing so, the number of steps and the number of photomasks can be reduced. In this case, the individual marks 5 are formed using the second photomask 10 in the same manner as described above, but the common marks 4 are formed in the photomask for forming the Al pattern for wiring.
[0017]
Further, as described above, the second photomask 10 different from the first photomask 9 on which the common pattern 9a is formed is used to form the individual mark 5, but the first photomask 9 is different from the common pattern 9a. The individual pattern 10a may be formed at the position. In this case, the number of photomasks can be further reduced. In this case, when exposing the individual pattern 10a, exposure is performed while shielding the other portions from light. When exposing other than the individual pattern 10a, exposure is performed while shielding the individual pattern 10a from light.
[0018]
Next, first to sixth variations of the shape and display of the common mark 4 and the individual mark 5 will be described with reference to FIGS.
4 to 9 show one semiconductor chip 2 as a representative.
First, as a first variation, as shown in FIG. 4, the common marks 4 correspond to the coordinates of the positions of the semiconductor chips 2 in the semiconductor substrate 1 arranged in a line by a combination of alphabets and numerals. The individual marks 5 are formed of rectangular marks in the rectangular portion 11 indicating the position of the semiconductor chip 2 coordinates.
[0019]
As a second variation, as shown in FIG. 5, the common mark 4 is formed by locating the position of the semiconductor chip 2 in the semiconductor substrate 1 in a row by combining two numbers and corresponding to the coordinates. The individual marks 5 are formed of rectangular marks in the rectangular portion 11 indicating the coordinate position of the semiconductor chip 2 as in the case of the first variation. It becomes.
[0020]
Next, as a third variation, as shown in FIG. 6, the common mark 4 indicates the positions of the semiconductor chips 2 in the semiconductor substrate 1 arranged in a line by a combination of two numbers and the coordinates corresponding to the coordinates. The individual marks 5 are formed by triangular marks at the positions of the scales 12 indicating the coordinate positions of the semiconductor chip 2.
[0021]
Next, as a fourth variation, as shown in FIG. 7, the common mark 4 is composed of coordinates arranged in a line by combining two numbers of the positions of the semiconductor chips 2 in the semiconductor substrate 1. Is formed by a triangular mark at the coordinate position of the semiconductor chip 2.
[0022]
Next, as a fifth variation, as shown in FIG. 8, the common marks 4 arrange the positions of the semiconductor chips 2 in the semiconductor substrate 1 in a row by combining two numbers, as in the case of the fourth variation. The individual mark 5 is formed so as to fill the coordinate position of the semiconductor chip 2.
[0023]
Next, as shown in FIGS. 9A and 9B, the position of the semiconductor chip 2 in the semiconductor substrate 1 on the mark layer 7 is represented by two numbers, as shown in FIGS. 9A and 9B. To form a common mark 4 consisting of coordinates arranged in a line, further form an opaque layer 13 on the mark layer 7, form the mark layer 7 after covering the common mark 4, The individual marks 5 are formed in the mark layer 7 such that the coordinates indicating the coordinate position of the semiconductor chip 2 are opened.
[0024]
In the above description, the individual mark 5 is formed in the common mark 4 to specify the position of the semiconductor chip in the semiconductor substrate 1. However, if a lot identification mark for performing lot management is required, the individual mark is changed to the mark type. It can be done by changing. In addition, although an example in which a rectangular mark or a triangular mark is used as the mark indicating the individual mark 5 has been described, a polygonal mark, a circular mark, or an arrow mark may be used instead.
[0025]
【The invention's effect】
According to the present invention, in a semiconductor device capable of specifying a defect occurrence position in the semiconductor substrate after the semiconductor chips arranged in a matrix on the semiconductor substrate are divided, the semiconductor chip includes a circuit portion, and the circuit portion. A common mark indicating the entire layout of the semiconductor chip in the semiconductor substrate formed in a region other than the area, and an individual mark indicating the position of the semiconductor chip in the semiconductor substrate formed in the common mark. Therefore, it is possible to identify at which position on the semiconductor substrate a defect has occurred by merely looking at the semiconductor chip divided from the semiconductor substrate.
According to the method of manufacturing a semiconductor device in the embodiment of the present invention, a mark layer is formed, and the common mark 4 and the individual mark 5 are formed in the mark layer on the mark layer. Since the position of a chip where a defect occurs can be easily specified by using the method, defect analysis and quality improvement can be achieved.
[Brief description of the drawings]
FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.
2A and 2B show common marks formed on a semiconductor chip, wherein FIG. 2A is a plan view and FIG. 2B is an enlarged plan view of the common marks and individual marks.
3A to 3C show a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 3A shows a (mark layer forming step), FIG. 3B shows a (common pattern exposure step), and FIG. (Exposure step), (D) is a sectional view showing (common mark and individual mark formation step).
FIG. 4 is a plan view showing common marks and individual marks formed on a semiconductor chip of a first variation.
FIG. 5 is a plan view showing common marks and individual marks formed on a semiconductor chip of a second variation.
FIG. 6 is a plan view showing a common mark and an individual mark formed on a semiconductor chip of a third variation.
FIG. 7 is a plan view showing common marks and individual marks formed on a semiconductor chip of a fourth variation.
FIG. 8 is a plan view showing a common mark and an individual mark formed on a semiconductor chip of a fifth variation.
9A and 9B show a common mark and an individual mark formed on a semiconductor chip of a sixth variation, wherein FIG. 9A is a plan view and FIG. 9B is a cross-sectional view of the MM of FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Semiconductor chip, 3 ... Circuit part, 4 ... Common mark, 5 ... Individual mark, 6 ... Lower layer, 7 ... Mark layer, 8 ... Photoresist, 8a, 8b ... Latent image, 9 ... First Photomask, 9a: Common pattern, 10: Second photomask, 10a: Individual pattern, 11: Rectangular part, 12: Scale, 13: Opaque layer

Claims (2)

In a semiconductor device capable of specifying a defect occurrence position in the semiconductor substrate after the semiconductor chips arranged in a matrix on the semiconductor substrate are divided,
The semiconductor chip includes a circuit portion, a common mark indicating the entire layout of the semiconductor chip in the semiconductor substrate formed in a region other than the circuit portion, and a common mark in the semiconductor substrate formed in the common mark. And a separate mark indicating a position of the semiconductor chip. Forming a mark layer on a plurality of semiconductor chips formed in a matrix on the semiconductor substrate;
After applying a photoresist on the mark layer, a first photomask on which a common pattern indicating the entire layout of the semiconductor chip in the semiconductor substrate is formed is disposed above the photoresist, and the photoresist is exposed and the photomask is exposed. Forming a first latent image of the common pattern on a resist;
A second photomask, formed in the common pattern and formed with an individual pattern indicating the position of the semiconductor chip in the entire layout, is disposed above the photoresist and exposed to light to expose the first latent image of the photoresist. Forming a second latent image in between;
Forming a photoresist pattern by developing the photoresist, etching the mark layer exposed from the photoresist pattern to form a common mark and an individual mark in the common mark,
A method for manufacturing a semiconductor device, comprising:

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