JP2004295914A - Data processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for obtaining exception handling performance corresponding to needs while maintaining compatibility and moreover reducing a logical scale. <P>SOLUTION: A combination of a plurality of assignable registers out of general-purpose registers is fixed to a control means (a CPU) for controlling an execution means for carrying out instructions, to have save/return instructions (STM instruction and LDM instruction) of the plurality of registers. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data processing device, and more particularly to a technology effective when used in a high-speed and small-sized single-chip microcomputer constituted by a semiconductor integrated circuit device.

  2. Description of the Related Art With the advancement of the manufacturing technology of semiconductor integrated circuit devices, a central processing unit (hereinafter, simply referred to as a CPU) and a ROM (Read Only Memory) for storing programs on a single chip made of a semiconductor single crystal. 2. Description of the Related Art A small single-chip microcomputer (hereinafter simply referred to as a microcomputer) manufactured by integrating components including a RAM (Random Access Memory) for storing various data in a rewritable manner has become widespread. Have been used as data processing devices for various purposes. This microcomputer has different performance depending on the amount of information that can be simultaneously processed by the CPU, and is classified as, for example, a 4-bit, 8-bit, 16-bit, or 32-bit microcomputer.

  In such a microcomputer, an address space is expanded, an instruction set is expanded, a speed is increased, and the like. Further, since the performance of the CPU is defined by software, even in a microcomputer in which the address space is expanded, the instruction set is expanded, and the speed is increased as described above, the software resources of the existing microcomputer are used. It is desirable that it can be used effectively.

  For this reason, as an example of realizing expansion of an address space, expansion of an instruction set, speeding-up, etc. while maintaining compatibility at the object level, for example, Patent Document 1 proposed earlier by the present applicant or Non-Patent Document 1 Etc.

  The CPU executes a basic instruction in so-called two states, which are two periods of a system clock. On the other hand, as an example in which a basic instruction is executed in one state and a multiplier is built in independently of the CPU to increase the speed, for example, Non-Patent Document 2 or Non-Patent Document 3 There is. Such a multiplier is used for the product-sum operation and the multiplication.

  By increasing the speed in this way, it is possible to increase the speed and performance of various devices controlled by the microcomputer, or to combine components conventionally constituted by a plurality of semiconductor integrated circuit devices. Thereby, miniaturization can be achieved.

  In addition, high speed, high performance, and miniaturization of various devices as described above are also required for a CPU or a microcomputer having a relatively small address space and a relatively small instruction set. When there are a CPU having a large address space and a CPU having a small address space, it is desirable to speed up both of them.

  From such a viewpoint, it is convenient if the upper CPU can be developed and developed to the lower CPU based on this. Thereby, the development efficiency can be improved. Further, in addition to the CPU itself constituted by the semiconductor integrated circuit device, it is desirable that development of development tools such as a cross assembler, a C compiler, a simulator, a real-time OS, and the like be shared to improve development efficiency.

JP-A-6-51981

"H8 / 300H Series Programming Manual" issued by Hitachi, Ltd. in June 1993 Published by Nikkei BP, November 1992, "Nikkei Electronics No. 568", PP99-PP112 Published by Hitachi, Ltd. in March 1993, "SH7032, SH7034 Hardware Manual"

  In such a microcomputer, since the multiplier requires a dedicated resource, it is not advisable in terms of cost-effectiveness if the product-sum operation or the multiplication is not necessarily required to be performed at high speed. Further, for example, in Non-Patent Document 3, since the multiplication result is obtained in a dedicated register (MAC), if this is used, it must be transferred to a general-purpose register of the CPU by another instruction. Even if the multiplication itself is speeded up by incorporating a multiplier, there is no point in increasing the time required to use the multiplication result.

  On the other hand, in order to maintain compatibility with a conventional CPU, it is difficult to add instructions as described above, and the added instructions must be minimized. Further, it is necessary to maintain compatibility of flags such as operation results. As for the product-sum operation, the usability is improved if a flag such as an operation result can be referred to. This is because it is possible to easily determine the operation result using a so-called conditional branch instruction or the like that determines the state of the flag and branches, and changes the content of the processing. Such flags include overflow (V), zero (Z), and negative (N).

  An object of the present invention is to provide a technique capable of obtaining multiplication performance according to needs while maintaining compatibility and improving processing performance.

  Another object of the present invention is to provide a technique capable of increasing the speed of processing while maintaining compatibility by incorporating a multiplying means in a control means.

  Another object of the present invention is to provide a technique capable of reducing the manufacturing cost by providing the multiplying means independently of the control means and providing the control means with a multiplying function.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

  (1) A data processing device according to the present invention includes a control unit for controlling an execution unit for executing an instruction, and a multiplication unit. The multiplication unit operates together with a first instruction in which the control unit and the multiplication unit operate in parallel. And a multiplication means is built in the control means. The first instruction is a multiply-accumulate instruction, and the second instruction is a multiply instruction. The addressing mode of the product-sum instruction is so-called post-increment register indirect. The multiplication means is provided with a flag detection means for judging the result, and is provided with means for supplying the flag detection result to the control means at the time of a multiplication instruction and holding the result.

  (2) The data processing device of the present invention includes a control unit for controlling an execution unit for executing an instruction and a multiplication unit, and the multiplication unit operates together with a first instruction in which the control unit and the multiplication unit operate in parallel. And a multiplying means is provided independently of the control means. The control means has a multiplication function.

  (3) The data processing device of the present invention has a fixed combination of a plurality of registers that can be designated as a control unit that controls an execution unit that executes an instruction, and has a save / restore instruction for a plurality of registers.

  (4) The data processing device of the present invention has means for switching the validity / invalidity of the control register mounted on the control means for controlling the execution means for executing the instruction. When returning from exception processing, the control register is saved / restored. When the control register is invalid, the control register is not saved / restored at the transition of exception processing or when returning from exception processing.

  (5) The data processing device of the present invention is provided with a fixed stack register in which a control means for controlling an execution means for executing an instruction is provided, and the fixed stack register is provided at the time of transition to the emulation program and at the time of return from the emulation program. A means for designating whether to ignore or hold the stack pointer used by the user by using a general stack register.

  According to the above-mentioned means (1), by incorporating a multiplier (multiplication means), it is possible to minimize the increase in the addressing mode and to execute the product-sum operation without lowering the processing performance. Can be. In addition, the product-sum operation of a large number of data can be continuously processed by the post-increment register indirect. Further, since the result (product, flag) of the multiplication can be used immediately, the execution speed of the actual multiplication can be improved.

  The multiplier and the CPU (control means) are integrally configured to reduce the wiring between the multiplier and the CPU, thereby reducing the physical scale. In addition, it can contribute to speeding up.

  According to the above-mentioned means (2), the lower CPU can be easily realized by providing the multiplier detachably (independently) and not supporting the product-sum operation when the multiplier is removed. Further, another microcomputer having a reduced logical / physical scale and a reduced manufacturing cost can be easily developed. Further, even in the CPU from which the multiplier has been removed, by supporting a general-purpose multiplication instruction, it is possible to prevent a decrease in usability. Further, by giving and controlling a control signal (valid / invalid) for using or not using a multiplier, testability can be improved and an emulator can be shared. Furthermore, overall development efficiency can be improved.

  If the multiplier is omitted, the multiplication can be performed in the same sequence as the division. Since the product-sum operation is not supported and the special sequence of the product-sum operation is not supported, the logical scale can be further reduced. By supporting test instructions, testability can be improved with minimal increase in logic size.

  According to the above-mentioned means (3), a save / restore instruction for a plurality of registers is provided, and by fixing the combination, the logical scale can be reduced and the speed can be increased. . By supporting a plurality of instructions having different numbers of registers, it is possible to prevent a decrease in usability.

  Further, by providing a plurality of register selection circuits having different input / output timings corresponding to the pipeline of the internal operation, it is possible to substantially execute one instruction / one state of a basic instruction such as an inter-register operation instruction.

  According to the above-described means (4), by switching between valid and invalid of the control register, it is possible to contribute to saving of the stack and shortening of the interrupt response time. In addition, compatibility can be maintained.

  According to the above-mentioned means (5), the support of the emulator can be facilitated by having a fixed stack pointer dedicated to the emulator. Further, the design of the emulator can be facilitated by minimizing the increase in the logical scale. By giving a part of the address of the emulator-dedicated stack pointer from outside the CPU, the stack register can be made relocatable, and it is possible to easily cope with the address arrangement of the microcomputer.

The effects obtained by typical aspects of the invention disclosed in the subject will be briefly described as follows.

  (1) By incorporating the multiplier in the CPU, it is possible to minimize the increase in the addressing mode and execute the product-sum operation without lowering the processing performance. The result of the multiplication by the multiplier is reflected in the general-purpose register CCR, such a result can be immediately used, and the processing speed can be increased.

  (2) By providing the multiplier detachably (independently), when the multiplier is removed, the lower CPU can be easily realized by not supporting the product-sum operation, and the logical and physical scales can be reduced. This can contribute to a reduction in manufacturing cost.

  (3) By having a save / restore instruction for a plurality of registers and fixing this combination, the logical scale can be reduced, and the speed can be increased.

  (4) By switching between valid / invalid of the control register, it is possible to save the stack and to shorten the interrupt response time, and to maintain compatibility.

  (5) Emulators can be supported by having a fixed stack pointer dedicated to the emulator, an increase in logical scale can be minimized, the design of the emulator can be simplified, and a stack pointer dedicated to the emulator can be used. By giving a part of the address from outside the CPU, the stack register is made relocatable, and it is possible to easily cope with the address arrangement of the microcomputer.

  Hereinafter, the present invention will be described in detail along with embodiments with reference to the drawings.

  In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted.

  FIG. 1 shows a block diagram of a single-chip microcomputer (hereinafter simply referred to as a microcomputer) as an example of a data processing device to which the present invention is applied. The microcomputer includes a CPU 1, a multiplier 2, a system controller (SYSC) 3, an interrupt controller (INT) 4, a ROM 5, a RAM 6, a timer A7, a timer B8, a serial communication interface (SCI) 9, an A / D converter 10, It is composed of functional blocks or modules of first to ninth input / output ports (IOP1 to IOP9) 11A to 11I and a clock oscillator (CPG) 12, and is formed as a semiconductor integrated circuit device on one semiconductor substrate by a known semiconductor manufacturing technique. It is formed. The CPU 1 has a built-in multiplier 2. The system controller (SYSC) 3 includes a system control register (SYSCR) 13 and a control register (CPUCR) 14.

  Such a microcomputer has a ground level (Vss) and a power supply voltage level (Vcc) as power supply terminals, and reset (RES), standby (STBY), mode control (MD0 to 2), and clock input (EXTAL) as other dedicated control terminals. , XTAL) terminals. The microcomputer operates in synchronization with system clocks (φ1, φ2) generated by a clock oscillator based on a crystal oscillator (not shown) connected to clock input (EXTAL, XTAL) terminals. Alternatively, an external clock may be input to the EXTAL terminal. One cycle of the system clock is called one state.

  These functional blocks are interconnected by an internal bus. The internal bus includes a read signal and a write signal in addition to an internal address bus (PAB) and an internal data bus (PDB), and further includes a bus size signal or a system clock (φ1, φ2).

  The input / output port is also used as an external bus signal and an input / output signal of an input / output circuit. These functions are selected and used depending on the operation mode or software setting. IOPs 1 to 3 are used for address bus output, IOPs 4 and 5 are used for data bus input / output, and IOP 6 is also used for bus control signal input / output signals. Each of the external addresses is connected to an internal address bus via a buffer circuit included in these input / output ports.

  Both the internal bus and the external bus have a 16-bit bus width, and enable reading / writing of byte size (8 bits) and word size (16 bits). Note that both the internal bus and the external bus may have an 8-bit width. The bus control signal input / output signals include an address strobe signal AS, a read signal RD, a write signal HWR / LWR, a wait signal WAIT, an area 0 selection signal CS0, and the like. The interrupt signal is requested from the timer / SCI / IOP8, the interrupt controller (INT) arbitrates, and requests the CPU for an interrupt. At this time, an interrupt request signal and a vector number are given to the CPU.

  When a reset signal is applied to the RES terminal, the operation mode given by the mode terminals (MD0 to MD2) is fetched, and the microcomputer is reset. The operation mode set by the mode terminal selects single chip / extension, address space, enable / disable of built-in ROM, and the initial value of the data bus width from 8 bits or 16 bits.

  FIG. 2 shows the configuration of the system control register (SYSCR) 3. Tables 1 to 4 show the contents of each bit.

Bit 2, 1: Reserved bit
When read, "0" is always read. Light is invalid.

[Table 1]

[Table 2]

[Table 3]

[Table 4]

  Table 5 shows an instruction set of the CPU 1. There are a total of 71 instructions of the CPU 1 used in the present embodiment. Table 6 shows combinations of instructions and addressing modes. Table 7 shows the meaning of symbols (operation symbols) used in the following tables. Tables 8 to 15 show a list of each instruction by function.

[Table 5]

[Table 6]

[Table 7]

[Table 8]

[Table 9]

[Table 10]

[Table 11]

[Table 12]

[Table 13]

[Table 14]

[Table 15]

  The basic instructions are the same as those of the CPU described in "H8 / 300H Series Programming Manual" issued by Hitachi, Ltd. in June 1993, and employ a so-called load store architecture. The combination of the instruction and the addressing mode can be reduced, and the logical and physical scales of the instruction control of the CPU can be reduced.

  The CPU of the present invention realizes faster instruction execution time than the conventional CPU.

  CPU instructions are in units of 2 bytes (words). Each instruction includes an operation field (op), a register field (r), an EA extension (EA), and a condition field (cc) as described below.

(1) Operation field This field indicates the function of the instruction, and specifies the addressing mode and the processing contents of the operand. It always contains the first 4 bits of the instruction. It may have two operation fields.

(2) Register field Specify a general-purpose register. The address register has 3 bits, and the data register has 3 bits or 4 bits. It may have two register fields or no register field.

(3) EA extension part Specifies immediate data, an absolute address, or a displacement. 8, 16 or 32 bits.

(4) Condition field Indicates the condition for branching the Bcc instruction.

  FIG. 3 shows an example of the basic format of the instruction.

  FIG. 4 is a schematic block diagram in which a multiplier 2 is detachably provided from a CPU 1 in a microcomputer. Instruction register (IR) 21, instruction decoder / control circuit (CONT) 22, register selector (RSEL) 23, write data buffer (DBW) 24, read data buffer (DBR) 25, arithmetic unit (ALU) 26, arithmetic unit ( INC) 27, general-purpose registers (ER0 to ER7) 28A to 28H, emulator stack pointer (EMLSP) 29, program counter (PC) 30, condition code register (CCR) 31, extension register (EXR) 32, address buffer (MAB) It consists of 33. The CPU 1 without the multiplier 2 is constituted by these components. The function of each buffer, register, and each block of the arithmetic unit is substantially the same as that of the CPU described in Japanese Patent Application Laid-Open No. 5-241826. The CPU 1 including the multiplier 2 further includes a bus switch 34 and the multiplier 2.

  The instruction decoder / control circuit (CONT) 22 receives a control signal CPUS, a control signal INTM1, and other control signals (such as an interrupt request). The CONT 22 outputs control signals A, B, and C having different output timings for controlling each unit.

  Note that C1 and C2 in the figure indicate the synchronization timing of the signal. For example, C1 of RSEL input 1 indicates that input is performed in synchronization with φ, and C2 of RSEL input 2 indicates that input is performed in synchronization with φ # (# is logical inversion). Further, C1 of the ALU input indicates that the input is performed during the period of φ, and C2 of the ALU output indicates that the output is performed during the period of φ #. The ALU 26 and the INC 27 are arithmetic units having different operation timings, and can perform arithmetic operations while overlapping each other.

  Other registers can input / output data in both φ and φ #. The GB, DB, and WB buses can transfer different data in both φ and φ #. φ and φ # may be two-phase clocks having a no-overlap relationship with each other.

  The register selector (RSEL) 23 receives a part of the instruction code (register designation field) from the IR 21 to the CONT 22. This supply timing differs depending on the position of the register designation field. The RSEL 23 outputs register selection signals A and B having different output timings.

  For example, in the CPU described in "H8 / 300H Series Programming Manual" issued by Hitachi, Ltd. in June 1993, bits 7-4 of a 16-bit instruction code are given simultaneously with CONT 22 (RSEL input 1). ), Bits 11-8 and 3-0 (RSEL input 2) are provided 0.5 state later than the contents of CONT22. An inversion control signal of RSEL input 2 is provided to RSEL.

  The DBW 24, DBR 25, ALU 26, INC 27, ER0 to ER7 (28A to 28H), PC 30, CCR 31, VAG, and AB inside the CPU 1 are interconnected by a GB bus, a DB bus, and a WB bus.

  Data is input from the GB and DB buses to the two arithmetic units ALU26 and INC27, and data is output to the WB bus. As the number of internal buses corresponding to the number of input / output buses, an increase in physical scale due to an increase in buses, that is, wiring, is suppressed.

  The write data buffer (DBW) 24 outputs to the internal data bus, the read data buffer (DBR) 25 inputs from the internal data bus, the address buffer (MAB) 33 outputs to the internal address bus, and the instruction register stores the internal data bus. Input from the data bus is possible, and each is connected to the internal bus. The write data buffer (DBW) 24 and the read data buffer (DBR) 25 have a 32-bit configuration. Write data can be written to the write data buffer (DBW) 24 in a batch of 32 bits, and output to the 16-bit internal data bus at a predetermined timing. Further, data read from the internal data bus can be temporarily stored in the read data buffer (DBR) 25, and 32-bit read data can be output collectively. MAB has a +2 increment function.

  An instruction decoder / control circuit (CONT) 22 controls the operation based on the input from the IR 21, the CPUS signal, the INTM1 signal, and other input signals. The output of the control circuit is output via a predetermined buffer. The state number and the like are also fed back to the CONT 22 itself.

  The address buffer (MAB) 33 has an increment function (+2). ER0 to ER7 (28A to 28H) can be used as data registers or address registers.

  The EMLSP 29 is a resource that is not disclosed to the user, and is used as a stack pointer at the time of transition between a user program and an emulation program when operating on an emulator. In order to specify the contents, some contents are given from outside the CPU.

  The PC 30 is a 32-bit counter and indicates the address of an instruction to be executed next by the CPU 1. The condition code register (CCR) 31 includes an interrupt mask bit (I), a carry flag (C), a zero flag (Z), a negative flag (N), and an overflow flag (V).

  The CPU 1 and the multiplier 2 are connected via a bus switch 34. Bus switch 34 also interfaces with an internal data bus. Further, a control signal from the CPU 1 to the multiplier 2 is given. The status signal BUSY of the multiplier 2 and the flag detection signal are supplied to the CPU 1. The TESTMODE signal is supplied from, for example, SYSC3. The control signal CPUS may be a control bit output of the SYSCR 14 or another register, or may be designated by a control terminal of a microcomputer.

  FIG. 5 shows a specific example in which the control signal CPUS is configured by the control bits of the control register (CPUCR) 14. The figure shows the configuration of one bit. The CPUCR 14 is configured by a flip-flop. A reset signal is supplied to the flip-flop. The clock of the flip-flop is a logical product signal of an internal write signal and a CPUCR selection signal obtained by decoding an address. The data input is bit 8 of the data bus. The output is a CPUS signal. The data is output to the data bus via the clocked buffer CBF6. The clock of the clocked buffer CBF6 is a logical product signal of the internal write signal and the CPUCR selection signal.

  This register can be written only in the test mode or in the break mode when the emulator is mounted. The break mode and the like are described in JP-A-6-150026 and the like. Similarly, a TESTMODE signal can be generated. They can be located in the same register.

  FIG. 6 is a block diagram showing an emulation processor and an emulator as an example of a method of setting the control signal CPUS. The emulation processor 38 is configured by adding an emulation interface 39 to a microcomputer part. The emulation interface 39 has a control register 41 dedicated to the emulation processor. The memory 42 includes a ROM and a RAM, and the I / O includes an I / O port, a timer, an SCI, and the like.

  The connector section is mounted on an application system (user system) 43 instead of the microcomputer. The emulation processor 38 inputs and outputs signals to and from the application system 43 using the target system interface via the connector section and the interface cable 44.

  The application system (user system) 43 includes, but is not limited to, a user bus 45 and a user memory 46. The user memory 46 is read / written according to a user strobe signal output from the emulation processor 38 and supplied via the interface cable 44.

  On the other hand, the emulation processor 38 is connected to the emulation bus 47 using the emulation interface 39. The emulation bus 47 includes state signals and control signals (not shown). Using the emulation bus 47, information and the like corresponding to the internal state of the application system 43 and the emulation processor 38 are output from the emulation processor 38, and various control signals for emulation are sent to the emulation processor 38. Is entered. An emulation mode terminal (not shown) of the emulation processor 38 is fixed at the power supply level, and the emulation mode is set inside the emulation processor 38.

  Further, the emulation bus 47 includes, although not particularly limited to, an emulation memory 48 such as a RAM for substituting the built-in memory of the application system 43 or the target microcomputer. Further, the control state of the emulation processor 38 and the state of the emulation bus 47 are monitored, and when the state reaches a preset state, the emulator-dedicated interrupt is input to stop the execution of the user program by the CPU. And a break control circuit 49 for causing a transition to an emulation program execution state (break), and an address given to the emulation bus 47 based on a signal indicating a read operation or a write operation of the CPU, a signal indicating an instruction read operation, and the like. A real-time trace circuit 50 for sequentially storing data and control information is connected.

  The emulation bus 47 is connected to an emulation memory 48, a break control circuit 49, a real-time trace circuit 50, and the like. These components constitute the microcomputer development device 55.

  The emulation memory 48, break control circuit 49, and real-time trace circuit 50 are connected to a control bus 51, and are controlled by a control processor 52 via the control bus 51. The control bus 51 is connected to an emulation processor control circuit, and is connected to a system development device 54 such as a personal computer, though not particularly limited, through an interface circuit. For example, when the program input from the system development device 54 is transferred to the emulation memory 48 and the CPU 1 reads such a program to be arranged in the built-in ROM, the program on the emulation memory 48 is read. Also, a break condition, a real-time trace condition, and the like can be given from the system development device 54.

  The control processor 52 can supply the CPUS signal to the emulation processor 38 to select use / non-use of the multiplier. The control processor 52 controls the CPUS signal based on information input from the system development device 54 and the like. Alternatively, a control register as shown in FIG. 5 is provided in the control register in the emulation interface 39, and the CPU of the emulator 40 executes the software to specify the control register to generate the CPUS signal. can do. In this case, it is convenient to enable writing only in the execution mode of the emulation software, so-called break mode. Erroneous setting is not performed due to malfunction of software of a user under development.

  By enabling the emulation processor 38 and the emulator 40 to support a plurality of CPUs, only an actual microcomputer needs to be developed, and development efficiency can be improved. Note that the address designation information of the EMLSP 29 can also be designated by a control register in the emulation interface 39.

  The emulation processor 38 and the emulator 40 are described in JP-A-3-271834 and JP-A-6-150026.

  FIG. 7 is a block diagram showing a main part of a microcomputer which is an example of a control signal CPUS setting method. The CPUS signal is output from the CMOS inverter circuit 58 without depending on the register. The CMOS inverter circuit 58 includes a P-channel MOS transistor Q1 and an N-channel MOS transistor Q2. The input of the CMOS inverter circuit 58 is connected to a power supply Vdd via a resistor R and to a terminal P via protection circuits Q3 and Q4. The terminal P is connected to the ground level power supply lead L by a wire W or is set in an open state, and the CPU S is set.

  When the terminal P is released, the input of the CMOS inverter circuit 58 becomes high level, and the CPUS signal becomes inactive. On the other hand, if the terminal P is connected to the ground level power supply lead L via the wire W, the input of the CMOS inverter circuit 58 becomes low level and the CPUS signal is activated. Enable the multiplier.

  The terminal P does not have a corresponding lead, and for example, does not have a corresponding terminal when sealed in a plastic package.

  Thus, since the control of the multiplier can be set without directly using the terminals of the package of the semiconductor integrated circuit device, it is possible to prevent the effective number of terminals from decreasing when a fixed package is used. In this case, it is convenient to arrange the terminal P adjacent to the ground level power supply terminal.

  Alternatively, whether or not the terminal P is connected to the ground level power supply lead L by the wire W or not may be realized as a change in wiring of the semiconductor integrated circuit device. It is sufficient to select whether to connect the input of the CMOS inverter circuit 58 to the power supply voltage or the ground inside the semiconductor integrated circuit device. At this time, the resistor R and the terminal P can be deleted. Alternatively, the CPUS bit may be constituted by a PROM element or the like. In this case, the manufacturer may make the setting, or the user may make the setting.

  8 and 9 show the internal register configuration of the CPU. These registers are divided into two, a general-purpose register in FIG. 8 and a control register in FIG. Hereinafter, each register will be described.

(1) General-purpose registers The CPU has eight general-purpose registers. This general-purpose register has a 32-bit length and has the same function, and can be used as both an address register and a data register. The data register can be used as a 32-bit, 16-bit and 8-bit register.

  The address register and the 32-bit register are collectively used as general-purpose registers ER (ER0 to ER7). As a 16-bit register, the general-purpose register ER is divided and used as general-purpose registers E (E0 to E7) and general-purpose registers R (R0 to R7). These have equivalent functions and can use up to 16 16-bit registers.

  As the 8-bit register, the general-purpose register R is divided and used as general-purpose registers RH (R0H to R7H) and general-purpose registers RL (R0L to R7L). These have the same function and can use up to 16 8-bit registers.

  FIG. 10 shows how to use a general-purpose register. The usage of each register can be independently selected.

  The general-purpose register ER7 is assigned a function as a stack pointer (SP) in addition to the function as the general-purpose register, and is used implicitly in exception processing and subroutine branching. FIG. 11 shows the state of the stack.

(2) Control Register The control register includes a 24-bit program counter (PC), an 8-bit extension register (extended register) (EXR), and an 8-bit condition code register (CCR).

1. Program counter (PC)
A 24-bit counter indicates the address of an instruction to be executed next by the CPU. Since all CPU instructions are in units of 2 bytes (words), the least significant bit is invalid. (The least significant bit is regarded as "0" when reading the instruction code).

  The upper 8 bits of the execution address of the branch instruction are ignored. The area of H'00000000 to H'00FFFFFF can be used as the program area.

2. Extension register (EXR)
It is an 8-bit register, and is composed of 8 bits including a trace bit (T) and an interrupt mask bit (I2 to I0).

Bit 7: trace bit (T)
Specify whether it is a trace bit or not. When this bit is cleared to "0", instructions are sequentially executed. When set to "1", trace exception processing is executed each time one instruction is executed.

Bits 6-4: Reserved bits These are reserved bits.

Bits 2 to 0: interrupt mask bits (I2 to I0)
Specify the interrupt request mask level (0 to 7).

  EXR can be executed with LDC, STC, ANDC, ORC, and XORC instructions. When instructions other than the STC are executed, all interrupts including the NMI are not accepted for three states after the execution is completed.

3. Condition code register (CCR)
An 8-bit register indicating the internal state of the CPU. It is composed of 8 bits including an interrupt mask bit (I), a half carry (H), a negative (N), a zero (Z), an overflow (V), and a carry (C).

Bit 7: interrupt mask bit (I)
When this bit is set to "1", the interrupt is masked. However, NMI is accepted regardless of the I bit. It is set to "1" when the execution of the exception processing is started.

Bit 6: user bit / interrupt mask bit (UI)
It can be read / written by software (LDC, STC, ANDC, ORC, ZORC instructions). It can also be used as an interrupt mask bit.

Bit 5: Half carry flag (H)
ADD. B, ADDX. B, SUB. B, SUBX. B, CMP. B, NEG. The bit 3 is set to “1” when a carry or a borrow occurs in the bit 3 by execution of the B instruction, and cleared to “0” when no carry occurs. ADD. W, SUB. W, CMP. W, NEG. When a carry or borrow occurs in bit 11 due to execution of the ADD. L, SUB. L, CMP. L, NEG. This bit is set to “1” when a carry or borrow occurs in bit 27 due to execution of the L instruction, and cleared to “0” when no carry occurs.

Bit 4: User bit (U)
REIT / WRITE can be performed by software (LDC, STC, ANDC, ORC, XORC instructions).

Bit 3: Negative flag (N)
The most significant bit of the data is regarded as a sign bit, and the value of the most significant bit is stored.

Bit 2: Zero flag (Z)
It is set to "1" when the data is zero, and cleared to "0" when it is not zero.

Bit 1: Overflow flag (V)
Set to "1" when an overflow occurs due to an arithmetic operation instruction. Otherwise, it is cleared to "0".

Bit 0: carry flag (C)
It is set to "1" when a carry is generated by execution of an operation, and is cleared to "0" when no carry is generated. There are the following types of carry.

(A) Carry of addition result (b) Borrow of subtraction result (c) Carry of shift / rotate The carry flag has a bit accumulator function and is used in a bit manipulation instruction. Note that the flag may not change depending on the instruction. The CCR can be operated with LDC, STC, ANDC, ORC, and XORC instructions. The flags N, Z, V, and C are used in a conditional branch instruction (Bcc).

4. Multiply-accumulate register (MAC)
This is a 64-bit register that stores the product-sum operation result. It is composed of 32-bit MACH and MACL. The lower 10 bits of the MACH are valid, and the upper bits are sign-extended.

  FIG. 12 shows the basic operation timing of the CPU.

  ADD. This is the timing of the operation between registers such as W R0 and R1. Although there is no particular limitation, the internal data bus is 16 bits, and the internal ROM and RAM can be read / written in one state.

  The address is output to the IAB from the address buffer (MAB) 33 of the CPU 1 at C2 of T0 (φ # synchronization; # indicates inverted logic).

  At C1 (φ synchronization) of T1, the contents of IAB are output to PAB, and a read cycle is started. In C2, read data is obtained on the internal data bus, and this is latched in IR21. The above operation is performed by controlling the execution of the previous instruction.

  When the execution of the immediately preceding instruction is completed and the execution of the instruction is started earliest, the instruction code is input to the CONT 22 at C1 of T2, and the contents of the instruction are decoded. According to the decoding result, a control signal is output to control each unit. A part of the instruction (register designation field: RSEL input signal 1) is given to the register selector 23.

  In the inter-register operation instruction, the contents of the PC are read out to the internal bus GB at C2 of T2 and input to the MAB 33 and the INC 27. The address IAB is output from the MAB 33. A control signal is given to the register selector 23. The register selection signal B is generated based on the RSEL input signal 1 and the control signal A (Rs-DB output, Rd-GB output). The RSEL input signal 2 is provided to the register selector 23.

  From T3, the next next instruction is read. At C1 of T3, the result incremented (+2) by INC27 is written to PC 30 via internal bus WB. A register selection signal C is generated based on the RSEL input signal 2 and the control signal B (WB-Rd input). The register selection signal B selects the register, and inputs the data of the source-side and destination-side registers (S, D) to the ALU 26. The contents of the operation of the ALU 26 are specified by the control signal C by the CONT 22. Operations such as addition, subtraction, logical operation, and shift can be performed in one clock. For example, the above instruction performs 16-bit addition. Instructs loading of the next instruction into CONT22. A register selection signal C is generated based on the RSEL input signal 2 and the control signal B (WB-Rd input).

  At C2 in T3, the operation result (R) of the ALU 26 is written to the destination register selected by the register selection signal C via the internal bus WB. The CCR 31 is updated by the control signal C. Further, the next next instruction is taken into the IR 21. At the same time, the execution of the next instruction is started. For example, the contents of the PC 30 are read and input to the MAB 33 and the INC 27. The operation between registers can be executed in substantially one state. As the number of internal buses corresponding to the number of input / output buses of the two computing units 26 and 27 (without increasing the number of internal buses corresponding to the computing units), an increase in the physical scale due to an increase in the number of buses, that is, the number of wires, is reduced. It is deterred.

  FIG. 13 shows the basic operation timing of the CPU.

  MOV. This is the timing of data write by register indirect, such as WR0 and ＠ R1.

  At C2 of T0, the address is output from the MAB 33 of the CPU 1 to the IAB.

  At C1 of T1, the address is output to PAB, and a read cycle is started. In C2, read data is obtained on the internal data bus, and this is latched in IR21.

  When the execution of the immediately preceding instruction is completed, the instruction code is input to the CONT 22 at C1 of T2, the content of the instruction is decoded, and each unit is controlled. A register designation field (RSEL input signal 1) of a part of the instruction is supplied to the register selector 23. In data writing by register indirect, a register selection signal A is provided based on the control signal A and the RSEL input signal 1, and a register specified as an address is selected.

  At C2 of T2, the content (A) of the selected register is read out to the internal bus GB and output to the address IAB via the MAB 33. The RSEL input signal 2 is provided to the register selector 23. The register selection signal B is generated based on the RSEL input signal 2 and the control signal B (Rd-DB output).

  At C1 of T3, a part of the control signal C is input to the CONT 22, and a state transition is performed (a state machine is configured). A write cycle is started based on the contents of IAB. The contents (D) of the selected register are read out to the internal bus DB and output to the internal data bus via the data buffer (DBW).

  At C2 of T3, the contents of the PC 30 are read out to the internal bus GB and input to the MAB 33 and the INC 27. The address IAB is output from the MAB 33. The register selection signal B is generated based on the RSEL input signal 1 and the control signal A (Rd-GB output).

  From T4, the next next instruction is read.

  At C1 of T4, the result incremented (+2) by INC27 is written to PC 30 via internal bus WB. The register selection signal B selects the register, and inputs the data of the data register (D) to the ALU 26. The contents of the operation of the ALU 26 are specified by the control signal C by the CONT 22. In the case of transfer, only data check is performed. Instructs loading of the next instruction into CONT22.

  At C2 of T4, the CCR 31 is updated according to the result checked by the control signal C. Further, the next next instruction is taken into the IR 21. At the same time, the execution of the next instruction is started. For example, the contents of the PC 30 are read and input to the MAB 33 and the INC 27.

  The timing of input to the RSEL is different from the timing of each register specification field (φ synchronization and φ # synchronization), such as RSEL input 1 (address register, source register) and RSEL input 2 (data register, destination register). By doing so, high-speed instruction execution can be realized.

  Tables 16 to 19 show descriptions of instructions related to the present invention.

  Table 16 shows the instruction code, Table 18 shows the execution state of the instruction, and Table 19 shows the change of the condition code. Table 17 shows the correspondence between register fields and general-purpose registers.

[Table 16]

[Table 17]

[Table 18]

[Table 19]

  There are a MAC instruction for performing a sum-of-products operation, a CLRMAC instruction for clearing a MAC register, an LDMAC instruction for transferring the contents of a general-purpose register to a MAC register, and an STMAC instruction for transferring the contents of a MAC register to a general-purpose register.

  The save / restore instructions for general-purpose registers include PUSH and POP instructions for save / restore instructions for one register, and the STM / LDM instructions for save / restore instructions for multiple registers. There are three types of STM / LDM instructions corresponding to the number of designated registers.

  FIG. 14 is a schematic block diagram of the multiplier 2.

  The multiplier 2 includes an input latch (X) 61, an input latch (Y) 62, a partial product generation circuit 63, a matching multiplexer 64, decoders 65A, 65B, 65C, selection circuits 66A, 66B, 66C, an adder 67, and a feedback circuit 68. , A multiplication result register 69 and the like.

  The basic operation of the multiplier 2 is to perform 16 × 16-bit multiplication, and by using this, a product-sum operation of 16 × 16 bits + 42 bits can be performed.

  The multiplier performs a 16-bit × 6-bit multiplication operation three times using a second-order Booth decoding.

  The 16-bit multiplier Y is Y = −y [16] · 2］ 15 + Σ (y [i] · 2 ＾ (i−1)) = Σ (y [2j] + y [2j + 1] −2 · y [2j + 2] ) · 2 ＾ 2j. i = 1 to 15, j = 0 to 7, and y [0] = 0.

  The multiplication with the multiplicand X is XY = Σ (y [2j] + y [2j + 1] −2 · y [2j + 2]) · X · 2 ＾ 2j. There are five types of y [2j] + y [2j + 1] −2 · y [2j + 2] depending on the combination of the values of y [2j], y [2j + 1], and y [2j + 2]. , Partial products (y [2j] + y [2j + 1] −2 · y [2j + 2]) · X are of five types: 0, ± X, ± 2X. Of these, 0 and X are obtained immediately. 2X is one bit left shift (the least significant bit is 0), -X is a two's complement, and is obtained by logical inversion +1. -2X is obtained by shifting the logical inversion +1 by one bit to the left (the least significant bit is 0).

  The X side generates five types of partial products (17 bits) of 0, ± X, and ± 2X that can be taken. These five types are given to partial product selection circuits 66A to 66C.

  On the other hand, y [2j], y [2j + 1], y [2j + 2] of the Y input are decoded to determine 0, ± 1, ± 2, and the partial product selection circuits 66A to 66C are controlled based on the result. Then, the five types of partial products are selected. Three types of selection are performed at a time in units of two bits. This is added by the adder 67. The addition is performed by adding 17-bit partial products shifted by 2 bits each to obtain a result of 22 bits. Insufficient upper bits are sign-extended data.

  Of these, the lower 6 bits are stored in bits 0 to 5 of the multiplication result register 69. The upper 16 bits are included in the second addition via the feedback circuit 68. In the second processing, the 17-bit partial products, which are the outputs of the partial product selection circuits 66A to 66C obtained in the same manner and are shifted by 2 bits each, and the upper 16 bits of the first processing are added. The result for 22 bits is obtained. Insufficient upper bits are sign-extended data. Of these, the lower 6 bits are stored in bits 11 to 6 of the multiplication result register 69. The upper 16 bits are included in the second addition via the feedback circuit 68.

  Similarly, a third process is performed. The lower 20 bits of the addition result are stored in bits 31 to 12 of the multiplication result register 69. The two most significant bits of the addition result are ignored.

  In the case of a product-sum operation, the previous results are added simultaneously.

  Furthermore, a fourth addition with the upper bit of the previous result is performed to obtain a 42-bit result. By obtaining the result of a 16-bit × 16-bit product-sum operation in 42 bits, no overflow occurs even if the product-sum operation is repeated about 1000 times.

  In terms of the structure of the internal logic, if the result is 40 bits, the adder may be 22 bits long, and the logical scale can be optimized.

  FIG. 15 shows an operation method of the word size multiplication (16 bits × 16 bits).

  The byte size multiplication of 8 bits × 8 bits extends the high order. If there is no sign, 0 extension is performed, and if signed, sign extension is performed. In either case, the upper bit is either all bits “0” or all bits “1”, and the Booth decoding becomes “0”. Therefore, the second process is sufficient without performing the third process.

  In FIG. 4, the MUL signal (control signal B) as a signal indicating multiplication, the UNSINP signal (control signal B) as a signal indicating signed / non-signed, and a signal indicating byte / word size from the CPU 1 to the multiplier 2 BYTE signal (control signal B), MAC signal (control signal B) as a start signal of the product-sum operation, STMACH signal (control signal C) as a data transfer request signal from MACH to CPU, data transfer from MACL to CPU As a request signal, a STMACL signal (control signal C), as a data transfer request signal from the CPU to the MACH, an LDMACH signal (control signal B), as a data transfer request signal from the CPU to the MACL, an LDMACL signal (control signal B), As a clear signal of the MAC register, a CLRMAC signal (control signal B), a transfer signal of a multiplier To, STX signal (control signal B), as multiplicand transfer signal, STY signal (control signal B), as the transfer signal of the multiplication result, give MULRD signal (control signal C).

  Further, the multiplier 2 supplies the CPU 1 with a BUSY signal as a signal indicating that the operation is being performed and a VFLAG, ZFLAG, and NFLAG signal as data to be reflected in the flag.

  An X bus and a Y bus are used for mutual data transfer between the CPU and the multiplier.

  Further, a FIXED signal is given from the SYSCR 13 as a signal indicating selection of a saturation operation. Also, a TESTMODE signal is provided as a test mode signal. When the TESTMODE signal is activated and the test mode is instructed, the multiplier terminates the operation only once.

  By shortening the processing, the instruction execution state of the CPU can also be shortened. When a test is performed with various combinations of input data, the test time can be reduced. Since the addition is performed only once, test design can be facilitated. By performing the processing three times, the addition result is accumulated, and the result of the test of the desired operation is not difficult to obtain as the operation result.

  It goes without saying that the CPU or the multiplier can be tested even when the TESTMODE signal is inactive. The TESTMODE signal can be supplied as an output of a register, as in the CPUS described above.

  Table 20 shows a method of detecting a flag inside the multiplier 2 and a method of transferring the flag to the CPU 1.

[Table 20]

  The flag specifications of the multiplier 2 are as follows: V flag and 2. It consists of an N flag and a Z flag.

1. The V flag is set when an overflow or underflow occurs during the execution of the MAC instruction.

  The clear condition is when the LDMAC or CLRMAC instruction is executed.

  The transfer from the multiplier to the CCR is performed when STMAC is executed.

  Therefore, if an overflow or underflow occurs at least once during a series of successive product-sum operations, the V flag of the multiplier remains set. When the LDMAC or CLRMAC instruction is executed to determine the start of a new series of multiply-accumulate operations, the multiplier V flag is cleared.

2. N flag and Z flag The N and Z flags for the MUL instruction and the N and Z flags for the MAC instruction are separately provided and output.

  The transfer from the multiplier to the CCR is performed at the time of transfer of the multiplication result in the case of a multiplication (MUL) instruction, and at the time of execution of STMAC in the case of a MAC instruction.

  Note that the N flag and the Z flag are not changed by LDMAC / CLRMAC.

  FIG. 16 shows a conceptual diagram of realizing the V flag specification, and FIG. 17 shows a conceptual diagram of realizing the N flag and Z flag specifications.

  The V flag is constituted by a set-reset type flip-flop (RS-F / F), and once an overflow or underflow occurs, keeps its state until it is read out by STMAC.

  The N and V flags are composed of a latch circuit (DF / F) and a multiplexer (MPX). The operation result at the time of executing the MAC instruction is held in the latch circuit and supplied to the multiplexer. The operation result at the time of executing the multiplication instruction is directly supplied to the multiplexer. The multiplexer outputs the output of the latch circuit in the case of the STMAC instruction, and directly outputs the operation result otherwise.

  The MAC instruction and other instructions operate in parallel. If the flag of the MAC instruction is reflected in the CCR as needed, it contradicts the flag operation of the instruction being executed in parallel. The contradiction can be avoided by holding the flag of the MAC instruction inside the multiplier and transferring it to the CCR when the STMAC instruction is executed.

  FIG. 18 shows a block diagram of the bus switch 34.

  The bus switch 34 includes selection circuits 71A and 71B, extension circuits 72A, 72B and 72C, and output buffers 73A, 73B, 73C and 73D. The bus switch interfaces the GB, DB, and WB of the CPU internal bus, the X and Y buses of the multiplier, and the IDB that is the internal bus of the microcomputer.

  At the start of multiplication and in the case of an LDMAC instruction, data is input from GB and DB to the X bus and Y bus. The inputs of GB and DB are selected by the selection circuits 71A and 71B. This is because a general-purpose register and an internal bus have a 32-bit configuration, and since a multiplier and a multiplicand are 8 bits or 16 bits, a predetermined portion is selected based on the control signal A of the CONT 22 and the register control signal A. You.

  Outputs of the selection circuits 71A and 71B are input to extension circuits 72A and 72B. In the case of unsigned byte size multiplication (MULXU.B) based on the control signal A of the CONT 22, the upper 8 bits are extended to zero. In the case of signed byte size multiplication (MULXS.B), the upper 8 bits are sign-extended. In the case of the word size, the outputs of the selection circuits 71A and 71B are output as they are.

  Outputs of the selection circuits 71A and 71B are input to output buffers 73B and 73C. Based on the control signal A of the CONT 22, the outputs of the extension circuits 72A and 72B are output to the X bus or the Y bus at a predetermined timing.

  At the end of the multiplication and in the case of the STMAC instruction, the output is performed from the X bus and the Y bus to the WB. Inputs of the X bus and the Y bus are input to the extension circuit 72C. This sign-extends the upper 22 bits of the MACH. The output of the extension circuit 72C is input to the output buffer. Based on the control signal C of the CONT 22, the output of the extension circuit 72C is output to WB at a predetermined timing.

  At the time of data reading of the MAC instruction, input from the IDB to the X bus and the Y bus is performed once each. The contents of the IDB are output to the X bus or the Y bus at a predetermined timing based on the control signal A of the CONT 22. The IDB can receive an output from the DBW and can input data to the DBR and the IR.

  19 and 20 show the operation timing of the MAC instruction.

  For example, it is an example of a MAC $ ER1 +, $ ER2 + instruction. In this case, ER1 is a first address register, and ER2 is a second address register. As described above, the execution of the MAC instruction is started from T2.

  First, a prefix code is executed, an instruction using the contents of the PC 30 as an address is read, and the contents of the PC 30 are incremented.

  At φ # of T3, the contents of the first address are read to GB based on the register control signal A, transferred to the MAB 33, and output to the IAB.

  At φ of T4, the contents of the first address are read out to GB and input to the ALU 26 to perform the increment.

  At φ # of T4, the increment result is stored in the first address register via WB. The first read data input to the bus switch 34 is output to the X bus, and the STX signal included in the control signal B is activated to cause the multiplier 2 to latch this content in the input latch X. At the same time, the contents of the second address are read to GB, transferred to MAB, and output to IAB.

  At φ of T5, the content of the second address is read out to GB and input to the ALU 26 to perform the increment. At φ # of T5, the increment result is stored in the second address register via WB. The second read data input to the bus switch 34 is output to the Y bus, and the STY signal included in the control signal B is activated to cause the multiplier 2 to latch this content in the input latch Y. The MAC signal is activated to instruct the start of the product-sum operation. At the same time, an instruction using the contents of the PC 30 as an address is read, and the contents of the PC 30 are incremented.

  At φ of T6, the increment result is stored in the PC 30. On the other hand, the BUSY signal is activated. With the MAC instruction, the CPU 1 operates in parallel with the multiplier 2 and starts executing the next instruction ignoring the BUSY signal.

  Even when the MAC instruction is continuously executed, the operation of the multiplier is completed while the next MAC instruction is performing the address calculation, so that no wait is inserted into the execution of the MAC instruction.

  By using an instruction code with a prefix code, an instruction set can be extended while maintaining compatibility, as described in Japanese Patent Application Laid-Open No. Hei 5-11981. In addition, when the next product-sum operation is performed during the operation of the multiplier, the instruction fetch and the data access can be performed, so that the execution time does not decrease even if the instruction length becomes long. The product-sum operation can be continuously executed at high speed.

  At the end of the operation, the multiplier 2 refers to the MACS bit of the SYSCR 13 and fixes the contents of the MAC register to the upper limit (H'7FFFFFFF) or the lower limit (H'80000000) if an overflow has occurred.

  21 and 22 show the operation timing of the STMAC and LDMAC instructions.

  For example, it is an example of an STMAC MACH, ER2 instruction. As described above, the execution of the STMAC instruction is started from T2.

  First, the state of the BUSY signal is sampled. When the BUSY signal is in the active state, the state changes to the wait state.

  At φ # of T2, the contents of the PC are read to GB, input to MAB 33, and output to IAB. Also, the data is input to the INC 27, and the increment operation is started.

  The clock inside the CPU is fixed at the low level, and the operation of the CPU is stopped. When the MAC instruction is executed immediately before, the BUSY signal is active for three states, and the STMAC instruction is also in a three-state wait state.

  When the BUSY signal becomes inactive at T5, the clock operation starts at T6.

  At φ of T6, the increment result is output to WB and stored in the PC 30. The STMACH or STMACL signal becomes active, and an instruction to read the MAC register is issued. The contents of the MAC register are output to the X bus and the Y bus. Although there is no particular limitation, the X bus is the upper content and the Y bus is the lower content.

  At φ # of T6, the contents of the X bus and the Y bus are output to the WB and stored in the designated register (ER2 in the case of STMAC MACH, ER2). At the same time, the contents of the flags of the multipliers are stored in the N, Z, and V flags of the CCR.

  Also, examples are LDMAC ER1 and MACL instructions.

  The execution of the LDMAC instruction is started from T8.

  At φ in T9, the contents of the specified register (ER1 in the case of LDMAC ER1, MACL) are read. This content is output to the X bus and the Y bus.

  At φ # of T9, the LDMACH or LDMACL signal is activated. The contents of the PC 30 are input to the MAB 33 and the INC 27 via GB.

  At φ of T10, the incremented result is stored in the PC 30 via WB. The contents of the X bus and the Y bus are stored in the MAC register.

  Similarly to the above, when the BUSY signal is active, the LDMAC instruction may be activated.

  The CLRMAC command may be configured to activate the CLRMAC signal at the same timing as the LDMACH and L signals of the LDMAC command, in substantially the same operation as the LDMAC command.

  23 and 24 show timing diagrams of a multiplication instruction using a multiplier.

  The number of the step of the internal state machine is described in the part of CONT22. This is basically formed by the feedback signal of the output of the CONT 22. Further, using the control signal CPUS, whether to use or not use the multiplier is selected. For example, MULXU. This is an example of byte size / unsigned multiplication such as WR1, ER0. As described above, the execution starts from T2.

  When the instruction is decoded, first, the reading of the general-purpose register is instructed by the register control signal A at φ # of T2. The read result is output to the X bus and the Y bus via the GB, the DB, and the bus switch 34.

  Based on the STX and STY signals included in the control signal B, the contents of the X bus and Y bus are latched by the input latch of the multiplier at φ of T3. At the same time, the MUL signal included in the control signal B instructs the multiplier to perform multiplication. The control signal indicates from the CONT 22 the selection of byte / word, the selection of signed / unsigned, and the selection of multiplication / sum of products.

  The multiplier provides a BUSY signal at φ # of T3. Also, a multiplexer and a decoder are operated. The first addition is performed at φ of T4. The partial product is stored in the multiplication result register and the feedback latch at φ of T4. This is repeated three times. The CPU enters the wait state in response to the BUSY signal being activated.

  At φ in T5, BUSY becomes inactive, the CPU resumes operation, and at φ in T6, the MULRD signal included in the control signal C is activated to instruct reading of the multiplication result register. The contents of the multiplication result register are stored in the register specified by the register control signal C via the X bus, the Y bus, and the bus switch 34, and via the WB at φ # of T6. At the same time, the result flag of the multiplication is stored in the CCR 31.

  As described above, the clock of the multiplication instruction is stopped by the BUSY signal, and the multiplication instruction enters a wait state. A byte-size unsigned multiplication instruction (MULXU.B R0L, R1, etc.) is inserted in one wait and executed in three states. A word-size unsigned multiplication instruction (MULXU.WR0, ER1, etc.) is inserted in two wait states and executed in four states. In the case of signed multiplication, execution of a prefix code is added to each.

  The logic of the control circuit (CONT22) can be reduced by determining the end of the execution of the operation by the BUSY signal.

  When the test mode is activated and the test mode is instructed, the multiplier performs only one-step operation, and the BUSY signal keeps the inactive state. The CPU ends the process in one state.

  25 and 26 show timing diagrams of a multiplication instruction without using a multiplier. Multiplication without using a multiplier is performed in a sequence similar to division, although there is no particular limitation.

  When the instruction is decoded, first, the instruction to read the general-purpose register is issued. A sign determination is performed on the read result. In accordance with the selection of signed / unsigned, sign judgment is performed, and the divisor is sign-inverted to a negative number. Others are positive numbers.

  The multiplicand is shifted one bit at a time, with the upper and lower bits set to 0, and whether to add the multiplier to the lower bit is determined based on the shifted result. The result is further shifted, and a multiplier is added to the lower side according to the shifted result. This is repeated eight or sixteen times to obtain the absolute value of the multiplication result. For example, MULXU. B is an example of byte size / unsigned multiplication such as R1L, R0. As described above, the execution of the division instruction is started from T2. After performing the predetermined processing as described above, partial multiplication is performed from T5.

  Partial multiplication includes left shift processing and addition. The previous addition and the next shift processing are performed by the same ALU processing.

  In synchronization with φ1 of T5, the multiplicand is read from the designated register (destination register Rd) and shift processing is performed. The result (partial product) of the shift processing is written to Rd via WB in synchronization with φ #. Also, the shifted out carry is held internally.

  In synchronization with φ1 of T6, a partial product is read from Rd, and a partial multiplication process is performed. If the previous carry is "1", a multiplier is added to the lower 8 bits of the partial product, a shift process is performed with 16 bits, and the least significant bit is set to "0". In other cases, the partial product is shifted by 16 bits, and the least significant bit is set to “0”. The result is written to Rd via WB in synchronization with φ #. Also, the shifted out carry is held internally. This operation is repeated seven times.

  At T13, the same determination as above is performed. If the previous carry is “1”, a multiplier is added to the lower 8 bits of the partial product. Otherwise, the partial product is retained. A 16-bit product is obtained. The result is written to Rd via WB in synchronization with φ #. If signed, sign processing is performed at T14. In the case of a word size, a partial multiplication process is added eight times.

  The sign processing of the product is performed based on the sign judgment result held earlier. That is, when one of the multiplier and the multiplicand is a positive number and the other is a negative number, the sign of the product is inverted (the product is subtracted from 0).

  FIG. 27 shows a state transition diagram of the multiplication instruction. For example, MULXU. B is an example of byte size / unsigned multiplication such as R1L, R0. When the execution of the instruction is started, the operation branches depending on the state of the CPUS signal.

  When the CPUS signal is active and the use of the multiplier is permitted, the operation of FIG. 6 is performed. That is, in step 1, the contents of the designated register are output to the X and Y buses via GB and DB, and supplied to the multiplier. The state of the BUSY signal is determined. In the test mode, the BUSY signal is in an inactive state, and the process immediately transits to step S2.

  When the BUSY signal is in the active state, the state transitions to the WAIT state. When the BUSY signal goes into the inactive state, the flow goes to step 2.

  In step 2, the contents of the X and Y buses are written to the designated register via the WB. For example, the contents of the flag of the multiplier are stored in the CCR 31. Start executing the next instruction.

  When the CPUS signal is in the inactive state and the use of the multiplier is prohibited, the operations of FIGS. 25 and 26 are performed. That is, after performing data alignment and the like in steps 1 and 2, a partial multiplication process is performed from step 3. In step 3, the multiplicand is output to the upper GB, and the multiplicand is shifted.

  In step 4, the partial product is output to GB and the multiplier is output to the lower part of DB, and the ALU 26 performs addition. If the bit shifted out in the previous step is "1", the result of the addition is selected. If the bit shifted out is "0", the contents of GB are selected and the shift is performed. This is repeated until step 10.

  In step 11, the partial product is output to GB and the multiplier is output to the lower part of DB, and the ALU 26 performs addition. If the bit shifted out in the previous step is "1", the addition result is selected. If the bit shifted out is "0", the content of GB is selected. No shift is performed. In step 12, an instruction is read. For example, the product is checked and reflected in the CCR. Start executing the next instruction.

  25 and 26 show timing diagrams of the division instruction. For example, DIVXU. B is an example of byte size / unsigned division such as R1L, R0. As described above, the execution of the division instruction is started from T2. After performing predetermined processing such as sign inversion of the divisor, partial division is performed from T5. Partial division includes left shift processing and subtraction. The previous subtraction and the next shift processing are performed by the same ALU processing.

  In synchronization with φ1 of T5, the dividend is read from the designated register (destination register Rd) and shift processing is performed. The result of the shift processing (partial remainder) is written to Rd via WB in synchronization with φ #. Also, the shifted out carry is held internally.

  In synchronization with φ1 of T6, a partial remainder is read from Rd, and a partial division process is performed. When the previous carry is “1”, or when the upper 8 bits of the partial remainder are greater than or equal to the divisor, the divisor is subtracted from the upper 8 bits of the partial remainder (if the sign of the divisor is inverted, the divisor is inverted). Are added), and a shift process is performed with 16 bits, and the least significant bit is set to “1”. In other cases, the partial remainder is shifted by 16 bits, and the least significant bit is set to “0”. The result is written to Rd via WB in synchronization with φ #. Also, the shifted out carry is held internally. This operation is repeated seven times.

  At T13, the same determination as above is performed, and if the previous carry is “1” or if the upper 8 bits of the partial remainder are greater than or equal to the divisor, the divisor is subtracted from the upper 8 bits of the partial remainder to obtain the lower 8 bits. Shift processing is performed on the bits, and the least significant bit is set to “1”. In other cases, the partial remainder is shifted by the lower 8 bits, and the least significant bit is set to “0”. In either case, the value of bit 7 is lost. The remainder is obtained in the upper 8 bits, and the quotient is obtained in the lower 8 bits. The result is written to Rd via WB in synchronization with φ #.

  If signed, sign processing is performed at T14. In the case of a word size, a partial division process is added eight times.

  FIG. 28 shows a schematic block diagram of the ALU 26. The ALU 26 includes an arithmetic and logic operation circuit 76, a selection circuit 77, a shift circuit 78, and a control circuit 79. Parts not directly related to multiplication / division are omitted.

  The arithmetic and logic operation circuit 76 inputs the contents of GB and DB, performs operations such as addition, subtraction, logical product, logical sum, and exclusive logical sum, and outputs the result. The selection circuit 77 receives the output of the arithmetic and logic operation circuit and the content of GB, selects one of them, and outputs it. Shift circuit 78 receives the output of selection circuit 77 and performs a shift process.

  The selection circuit 77 and the shift circuit 78 are controlled by the control circuit 79. The control circuit 79 controls the selection of the selection circuit 77 and the shift input of the shift circuit 78 based on the control signal supplied from the CONT 22 and the outputs of the arithmetic and logic operation circuit 76 and the shift circuit 78. The control circuit 79 determines the above-described partial multiplication and partial division. If the condition is satisfied, the output of the arithmetic and logic operation circuit 76 is selected. In the case of division, 1 is input to the shift circuit. If the condition is not satisfied, GB input is selected, and in the case of division, 0 is input to the shift circuit. The input of the shift circuit in the case of multiplication is set to 0.

  The processing sequence of partial division of division and partial multiplication of multiplication and the circuit configuration of the ALU 26 are shared. The logical scale of the CONT 22 can be reduced by sharing the division and the multiplication.

  This makes it possible to easily provide a CPU having no multiplier. In a CPU having a multiplier, the logic of multiplication that does not use an unnecessary multiplier is shared with division, thereby minimizing the increase in the logic scale.

  Further, the testability can be improved by enabling selection without using the multiplier by the CPUS. During testing, both logic can be tested by choosing to use or not use a multiplier.

  Table 16 shows the instruction codes of the save / restore instructions of a plurality of instructions.

  The register number to be used first is specified in the instruction code. For example, instead of specifying an arbitrary combination of registers as in the save / restore instruction of multiple instructions described in the “H8 / 500 Series Programming Manual” issued by Hitachi, Ltd. , And two, three, and four fixed combinations. Three types of instruction codes are prepared according to the number of registers.

The save instruction of multiple instructions corresponds to the number of registers to be saved,
STM (ERl-ERl + 1), ＠ -SP
STM (ERm-ERm + 2), ＠ -SP
STM (ERn-ERn + 3), ＠ -SP
There are three types. l = 0, 2, 4, 6 and m, n = 0, 4. Save the specified general-purpose register to the stack. For example, when saving ER0 and ER1 to the stack,
STM (ER0-ER1), ＠ -SP
Is used. The data is written to the stack in the order of ER0 and ER1, and the stack pointer (ER7) is incremented by +8. The register designation part in the instruction code is the register number to be saved first.

  29 and 30 show an execution sequence of a save instruction of a plurality of registers. For example, in STM. This is an example in which two general-purpose registers such as LER0-ER1 and $ -SP are saved. The register designation field is B'000 (B 'indicates a binary number).

  As described above, the execution of the division instruction is started from T2. Although not particularly limited, the first word of the instruction code is a prefix code, specifies the operation of the next instruction code, and does not perform any other operation for incrementing the PC.

  The instruction code of the second word is made common to the PUSH instruction.

  At φ of T4, the contents of the SP are read out to GB and input to the ALU 26. The ALU 26 performs the operation of -4. As described above, it is assumed that the SP before execution indicates the top address of the stack.

  The calculation result is output to WB and GB at φ # of T4. The data is written from WB to SP, and stored from GB to MAB 33. The contents of MAB 33 are output to IAB. The register to be saved is selected by the first control signal B and RSEL2 (= B'000), and the register control signal B is generated.

  At φ of T5, the contents of the selected register (ER0) are transferred to the DBW 24 via the DB.

  At φ # of T5, the upper 16 bits (contents of the E register) of the transferred data (contents of ER0) are output to the internal data bus. Further, the output value of IAB is set to +2 by the increment function of MAB33.

  At φ of T6, the contents of the SP are further read to GB and input to the ALU 26. The ALU 26 performs the operation of -4.

  At φ # of T6, the lower 16 bits (contents of the R register) of the data transferred to the DBW 24 are output to the internal data bus. The operation result of the ALU 26 is output to WB and GB. The data is written from WB to SP and stored from GB to MAB. The contents of MAB 33 are output to IAB. Also, bit 0 of RSEL is inverted by the second control signal B. The register to be saved is selected by the first control signal and RSEL2 (= B'001), and the register control signal B is generated.

  At φ of T7, the contents of the selected register (ER1) are transferred to the DBW 24 via the DB.

  At φ # of T7, the upper 16 bits (contents of the E register) of the transferred data (contents of ER1) are output to the internal data bus. Further, the output value of IAB is set to +2 by the increment function of MAB33.

  At φ # of T8, the lower 16 bits (contents of the R register) of the data transferred to the DBW 24 are output to the internal data bus.

  After φ # at T8, the next next instruction is read and the PC 30 is incremented (+2) in the same manner as described above.

  When three registers are specified, the number of execution states increases by two states, and the SP decrement (−4) and the bit 1 of the RSEL are inverted. RSEL is set to 010 when the register designation field is 000, and the general-purpose register ER2 is selected. The write operation is performed twice.

  When four registers are specified, the number of execution states is further increased by two states, and the SP decrement (−4) and the bit 1 and bit 0 of RSEL are inverted. RSEL is set to 011 when the register designation field is 000, and the general-purpose register ER23 is selected. The write operation is performed twice.

  Since the lower bits of the register number are fixed, it is easy to change this in accordance with the execution of the instruction processing. For example, when saving two registers, the lower bit of the register specification field on the instruction code is 0, so the first register specification is performed according to the value of the register specification field, and the second register specification is performed using CONT22. Is performed by changing the lower 1 bit of the register designation field to 1 in accordance with the control of (1).

  On the other hand, the PUSH instruction saves one register, so that the second save operation is not performed, and the execution operation is shared.

  FIGS. 31 and 32 show the execution sequence of the return instruction of a plurality of registers. For example, LDM. In this example, two general registers such as L @ ER7 + and ER0-ER1 are saved. The register designation field is 001.

  33 and 34 show a specific configuration of the RSEL2 input control circuit and an operation description thereof. This control circuit includes AND circuits 75A and 75B and OR circuits 80A and 80B.

  In the bit 2, the bit 2 of the register designation field of the operation code is input as it is. Bits 1 and 0 are input via an OR gate and an AND gate. The other input of the OR gate is the STM control signal 1, 0, and the other input of the AND gate is the inverse of the LDM control signal 1, 0. The STM control signals 1 and 0 and the LDM control signals 1 and 0 are included in the control signal B that is the output of the CONT 22.

  When the STM control signal is activated, the RSEL bit becomes 1. When the LDM control signal is activated, the RSEL bit becomes 0. An STM control signal and an LDM control signal are generated according to the STM and LDM instructions and the designated number of registers.

  Thereby, the register selection circuit can be shared with other instructions. Commonization can suppress an increase in physical scale.

  35 and 36 schematically show functions written in the C language and lists converted from the functions into CPU instructions. This list shows items of offset (relative address), instruction code, C label, C source, and assembler instruction.

  Compilation from C language to CPU instructions is described in, for example, "H8 / 300 Series C Compiler" issued by Hitachi, Ltd., September, 1992. Arguments can be set in general-purpose registers ER0 and ER1.

In the function Proc1, an argument is passed to a register and is assigned to ER0. Since ER2, ER3, ER4, ER6 are used in the processing within the function, at the beginning of the function processing,
STM (ER2-ER3), ＠ -SP
STM (ER4-ER6), ＠ -SP
And at the end of the function,
LDM @ SP +, (ER4-ER6)
LDM @ SP +, (ER2-ER3)
And returns from the subroutine (RTS).

  Since ER0 and ER1 are argument areas, they are not used in the function and the contents are not saved / restored.

The function Proc3 called in this function passes an argument by register and assigns it to ER0. Since ER5 is used in the processing in the function, one register is saved at the beginning of the function processing. L ER5
And at the end of the function,
POP. L ER5
And returns from the subroutine (RTS).

Since the stack pointer is also used as ER7, it is meaningless to save / restore ER7. Therefore, when saving all the registers that can be used when performing task switching,
STM @ SP +, (ER0-ER3)
STM @ SP +, (ER4-ER6)
Are used. It is saved on the stack in the order of ER0 to ER6. Similarly, when returning,
LDM @ SP +, (ER4-ER6)
LDM @ SP +, (ER0-ER3)
Are used. Return from the stack in the order of ER6 to ER0.

  Although an arbitrary combination cannot be specified as described above, by allocating registers in advance, it is unlikely to be a substantial constraint. Two instructions are used to save / restore the seven registers, but this has little effect on the total number of execution states and the program capacity. At least, it is more effective to use the save / restore instruction for each register. In the latter case, 4 bytes × 7, 5 states × 7, whereas in the former, 4 bytes × 2, 9 + 11 states. At least, a read cycle for instruction read and an internal operation for address calculation can be shortened to achieve high speed.

  Like a program written in the C language, it is possible to realize a high-speed program using many functions or subroutines.

  In addition to the above-described functions and subroutines, it is necessary to perform the same save / restore of registers in an interrupt processing routine. When a microcomputer performs device control, etc., it is possible to improve real-time controllability by reducing the time from the occurrence of an interrupt event to the actual execution of interrupt processing. it can. By making it possible to save a plurality of registers at high speed, it is effective in improving such real-time controllability.

  Further, by using a fixed combination and fixing the number of execution states of each instruction, it is possible to eliminate internal conditional branching, simplify the internal logic, and reduce the logic scale. It can be easily realized by wired logic or the like without using a microprogram. By using wired logic or the like regardless of the microprogram, it is possible to contribute to speeding up of a logic circuit. In particular, a program that uses many functions or subroutines such as the C language can be executed at high speed.

  37 and 38 show the sequence of the interrupt exception handling.

  FIG. 39 shows a state transition diagram of the exception processing.

  In the same manner as described above, the execution of the interrupt exception handling is started from T2. The prefetched instruction is canceled, and the input of the CONT 22 is switched in response to an interrupt request signal (not shown).

  As an operation of step 1, the PC 30 is decremented. At φ2 of T2, the contents of the PC 30 are read, and the decrement (−4) is performed by the INC 27 via GB. This calculates the value of the PC 30 to be saved in response to the cancellation of the prefetch.

  The result of the decrement at φ of T3 is temporarily stored in the PC 30 via WB.

  In step 2, the SP is decremented, and a write operation is performed using the contents as an address and the contents of the PC 30 as data. That is, at φ of T3, the contents of SP are read out at the same time, and the ALU 26 decrements (−2) via GB.

  At φ # of T3, the decremented result is stored in the SP via the WB, transferred to the MAB 33 via the GB, and output to the IAB.

  At φ of T4, the contents of the PC 30 are transferred to the DBW 24 via the DB. The contents of the DBW 24 are output from φ # of T4 to the internal data bus.

  In step 3, the SP is decremented, and the write operation is performed using the contents as an address and the upper 8 bits of the PC 30 and the contents of the CCR 31 as data.

  At φ of T4, the contents of the SP are read at the same time, and the ALU 26 decrements (−2) via GB.

  At φ # of T4, the decremented result is stored in SP via WB, transferred to MAB 33 via GB, and output to IAB. The lower 16 bits of the content of the PC 30 held in the DBW 24 are output to the internal data bus.

  At φ of T5, the contents of the CCR 31 are transferred to the DBW 24 via the DB. The upper 8 bits of the PC 30 stored at T4 are held. The contents of the DBW 24 are output to the internal data bus from φ # of T5.

  If the INTM1 signal is in the inactive state, the process proceeds to step 4. If the INTM1 signal is in the active state, the flow goes to step 12 to decrement SP and perform a write operation using this content as an address and the EXR content as data.

  At φ of T5, the contents of SP are read, and decrement (-2) is performed by ALU 27 via GB.

  At φ5 of T5, the result of the decrement is stored in the SP via WB.

  At φ of T6, the contents of EXR are transferred to DBW 24 via DB. From φ # of T6, it is output to the internal data bus.

  In step 4, the contents of the vector address are read.

  At φ # of T5, the contents of VAG are simultaneously transferred to MAB 33 via GB and output to IAB. The VAG generates a vector address based on a vector number provided from an interrupt controller (not shown).

  In step 5, the process waits for the end of the vector address read operation.

  In step 6, an instruction is read using the contents of the vector address stored in the DBR 25 as an address. The contents of the DBR 25 are incremented and stored in the PC 30.

  At φ # of T8, the read content (start address of the branch destination) of the vector address stored in the DBR 25 is transferred to the MAB 33 via GB, output to the IAB, and incremented (+2) by the ALU 26.

  At φ of T9, the incremented result is stored in the PC 30 via WB.

  In step 7, an instruction is read using the contents of the PC 30 as an address, and the PC 30 is incremented.

  At φ # of T9, the contents of the PC 30 (the leading address of the branch destination) are transferred to the MAB 33 via GB, output to the IAB, and incremented (+2) by the ALU 26. The read instruction is stored in the IR 21.

  At φ of T10, the increment result is stored in the PC 30 via WB.

  Starts execution of the next instruction.

  According to control signal INTM1, whether to perform step 12 or not is selected, and whether to perform stacking twice or three times is selected. When stacking is performed twice, only the PC and the CCR 31 are saved. SP is -4. The part corresponding to the operation of the above T5 (step 12) is not executed. When the operation is performed three times, the PC 30, CCR 31, and EXR are saved. SP is -6.

  It should be noted that the operation in units of steps spans a plurality of states because a plurality of control signals A, B, C and register selection signals A, B, C at different timings are generated in response to the input of one CONT 22. Corresponding to being done.

  40 and 41 show the state of the stack after the exception processing. FIG. 41 shows the normal mode, and FIG. 42 shows the advanced mode.

  FIG. 42 shows an execution sequence of the RTE instruction.

  FIG. 43 shows a state transition diagram of the exception processing.

  As described above, the execution of the RTE instruction is started from T2.

  As an operation of step 1, the stack is read using the contents of the SP as an address. At φ # of T2, the contents of the SP are read, transferred to the MAB 33 via GB, and output to the IAB.

  At φ of T3, the contents of the SP are read and incremented (+2) by the ALU 27 via GB. Read the stack with the IAB address. At φ # of T3, the read contents are stored in the DBR 25.

  If the INTM1 signal is in the inactive state, the process proceeds to step 2. If the INTM1 signal is in the active state, the flow goes to step 10 to store the read result in EXR. SP is incremented, and reading is performed with this content.

  At φ # of T3, the incremented result is simultaneously stored in SP via WB. Further, the data is transferred to the MAB 33 via the GB and output to the IAB.

  At φ of T4, the contents of the DBR 25 are read to GB and input to the ALU 27. At φ # of T4, the ALU 27 outputs the content input from GB as it is to WB and stores it in EXR.

  In step 2, the read result is stored in the CCR 31. The contents stored in the MAB 33 are incremented by the MAB 33. A read is performed with these contents. The increment function of the MAB 33 is described in, for example, JP-A-4-333153.

  At φ of T5, the contents of the DBR 25 are read to GB, and this is input to the ALU 27. At φ # of T5, the ALU 27 outputs the content input from the GB as it is to the WB and stores it in the CCR 31.

  In step 3, the content of the SP is incremented (+4).

  At φ of T6, the contents of the SP are read and incremented (+4) by the ALU 26 via GB.

  At φ6 of T6, the increment result is stored in the SP via WB.

  In step 4, an instruction is read using the contents of the PC 30 restored from the stack stored in the DBR 25 as an address. The contents of the DBR 25 are incremented and stored in the PC 30.

  At φ # of T6, at the same time, the read contents of the vector address (the leading address of the branch destination) stored in the DBR 25 are transferred to the MAB via GB, output to the IAB, and incremented (+2) by the ALU.

  At φ of T7, the increment result is stored in the PC 30 via WB.

  In step 5, an instruction is read using the contents of the PC 30 as an address, and the PC 30 is incremented.

  At φ # of T7, the contents of the PC 30 (the leading address of the branch destination) are transferred to the MAB 33 via GB, output to the IAB, and incremented (+2) by the ALU 26. The read instruction is stored in the IR.

  At φ of T8, the increment result is stored in the PC 30 via WB. Starts execution of the next instruction.

  For example, when the INTM1 signal is at the 0 level, the same stack structure as that of the conventional CPU (for example, the CPU described in "H8 / 300H Series Programming Manual" issued by Hitachi, Ltd., June 1993) is used. Is done. The program written by the conventional CPU can be directly executed in combination with the common instruction code.

  When a new condition code, interrupt mask bit, trace bit, or the like is added, a program corresponding to this is created, so that there is no substantial problem even if the stack structure is different. Usability can be improved by adding an interrupt mask bit or the like.

  As described above, the INTM1 bit exists in the SYSCR, and the state of this bit is reflected in the INTM1 signal. After the reset, the setting of the SYSCR is performed to select whether to use the EXR.

  FIG. 44 shows a part of the logic of the CONT 22. The CONT 22 includes AND circuits 86A to 86D.

  When EXR is not used, that is, when the INTM1 bit is cleared to “0”, all bits of EXR are regarded as “0” and the set value is ignored.

  Next, the configuration of the control register 41 included in the emulation interface 39 in FIG. 4 will be described. As described below, this control register 41 includes (1) ASE control register D (ASECRD), (2) break control register AB (BRCR, B), and (3) break address register A, B (BARA, B). ), (4) Break address mask register A, B (BAMRA, B), and (5) ASE dedicated stack register (BRKSTKR).

  FIG. 45 shows the configuration of (1) ASE control register D (ASECRD). This register is an 8-bit readable / writable register, and specifies single step setting, interrupt control after execution of an RTB instruction, permission / prohibition of multiple breaks, and a window function. Tables 21 to 24 show the contents of each bit.

[Table 21]

[Table 22]

[Table 23]

[Table 24]

  FIG. 46 shows the configuration of (2) Break Control Register AB (BRCR, B). This register is composed of (a) BRCRA and (b) BRCRB, each of which is an 8-bit readable / writable register and controls the PC break channels A and B, respectively. Tables 25 to 28 show the contents of each bit.

[Table 25]

[Table 26]

[Table 27]

[Table 28]

  FIG. 47 shows the configuration of (3) break address registers A and B (BARA, B). This register is composed of (a) BARA and (b) BARB, each of which is a 32-bit readable / writable register and specifies the address of a channel A or B of a PC break, respectively. A 32-bit register may be divided into byte sizes and denoted as BARR, E, H, and L. The top BARR is reserved. When read, an undefined value is read. Light is invalid.

  FIG. 48 shows the configuration of (4) Break address mask registers A and B (BAMRA, B). This register comprises (a) BAMRA and (b) BAMRB, each of which is a 32-bit readable / writable register and specifies a bit for masking the address comparison of channels A and B of a PC break, respectively. When the bit of BAMR is set to "1", the bit of the address corresponding to this bit is excluded from the address comparison target. In some cases, a 32-bit register is divided into byte sizes and denoted as BAMRR, E, H, and L. The top BARR is reserved. When read, an undefined value is read. Light is invalid.

  FIG. 49 shows the configuration of (5) ASE dedicated stack register (BRKSTKR). This register is a 6-byte (48-bit) readable / writable register, and is used as a stack area when transitioning from user mode to break mode. The user's SP is not used and is retained. The resources to be stacked and the structure of the stack differ depending on the MCU operation mode (normal mode / advanced mode) and the setting of the control register (INTM1 bit of SYSCR). Table 29 shows how to use this register.

[Table 29]

  At the time of transition (break) to the execution state of the emulation software, a break stack register at a fixed address is used. At the time of break exception handling or a return instruction from a break, a fixed stack address is generated without using the user's stack pointer (ER7). The generation of such a stack address is performed by the EMLSP 29.

  FIG. 50 shows the configuration of the EMLSP 29. This EMLSP 29 is composed of a clocked buffer.

  Of the clocked buffers, bits 23 to 10 are fixed at 1, bits 5, 4, and 0 are fixed at 0, and bits 9 to 6 are input from outside. Bits 3, 2, and 1 receive the control signal of CONT22. When a CMOS circuit is used, logical inversion may be used as needed. The output of the clocked buffer is connected to GB. The control signal m is a logical product signal of the control signal of CONT and the clock (φ #).

  A normal register circuit must have a latch circuit for holding data, but the EMLSP 29 does not have this and is trying to reduce the size.

  Therefore, the start address of the break stack register is B'000000, and 16 addresses can be selected in units of 64 kbytes. The address can be changed depending on the arrangement of the internal I / O registers of the microcomputer.

The execution sequence of the break exception process is the same as that shown in FIGS. 37 and 38, and the EMLSP 29 is read instead of reading the SP (ER7) there.
In this case, at the beginning (φ of T3), the lower address is B'000110, and the decremented content B'000100 is set as the address of the stack.

  In the second time (φ of T4), the lower address is set to B'000100, and the decremented content B'000010 is set as the stack address.

  For the third time (φ of T5), the lower address is set to B'000010, and the decremented content B'000000 is set as the address of the stack. The third time is effective when the INTM signal is in the active state. The bits 2 and 1 to be read are selected by a control signal of the CONT 22.

  The execution sequence of the return instruction is the same as that in FIG. 42, and the EMLSP 29 is read instead of reading the SP (ER7).

  The first (φ # of T2) differs depending on the INTM1 signal. When the INTM1 signal is inactive, the lower address is read as B'000010, and when the INTM1 signal is active, the lower address is read as B'000000. These are the addresses of the stack.

  The second time (φ of T3) is effective when the INTM1 signal is in the active state. The lower address is set to B'000010, and the result of the decrement is read as the address.

  In the third time, an address is generated by incrementing the MAB 33, and the EMLSP 29 is not used.

  Thereby, the logic scale can be reduced as a fixed output circuit. An increase in logical scale due to resources not disclosed to the user can be minimized.

  FIG. 51 shows the execution timing of the break exception handling. The execution sequence is the same as the exception processing timing in FIGS.

  In the same manner as described above, the execution of the interrupt exception handling is started from T2. The prefetched instruction is canceled, and the input of the CONT 22 is switched in response to a break request signal (not shown).

  During a period in which the bus operation of T3 is not performed, the signal BRKAK # indicating the break mode is activated.

  FIG. 52 shows a circuit configuration of the break control logic. This circuit includes AND circuits 81A to 81G, OR circuits 82A to 82D, and a flip-flop 83.

  There are three causes for a break request to the CPU. The first is a request by the BRK terminal. The second is a request by address comparison A, which is granted by the BIEA bit of BRKCR. Third is a request by address compare B, which is granted by the BIEB bit of BRKCR. As described above, this address comparison is expressed as (CA23 / AR23 + @ CA23 / @ AR23 + AMR23)... (CAn / ARn + @ CAn / @ ARn + AMRn)... (CA0.AR0 + @ CA0. @ AR0 + AMR0). You. (¬ indicates logical inversion).

  These OR signals are supplied to the CPU as a break request. In the break mode, permission / prohibition of the break request by the BRK terminal is selected according to the state of the MBIE bit. That is, when the MBIE bit is cleared to "0" in the break mode, the break request is suppressed. Break requests by address comparison are prohibited in the break mode.

  The MBIE bit is formed by a flip-flop, and is cleared to “0” by an inverted signal of the BRKAK signal. The input of the flip-flop is a bit of a predetermined data bus, and the clock is an AND signal of a break mode signal, an address decode signal, and a write signal. Such an address decode signal is activated when the address output from the CPU becomes an address where BRKCR exists. That is, writing is enabled only in the break mode.

  That is, immediately after the transition to the break mode, the break request is in a disabled state, and the multiple exception processing of the undesired break (destruction of the stacked contents) is prohibited. The logical product of the SSTP bit of BRKCR and the inverted signal of the BRKAK signal is given to the CPU as a single step break request.

  The logical product signal of the single step break request, the RTB instruction execution signal, and the break request are recognized inside the CPU as a CPU break exception processing request. The contents of these exception processes are common.

  When executing the RTB instruction, the CPU ignores the single step break request.

  According to the above embodiment, the following operation and effect can be obtained.

  (1) Incorporating a multiplier while maintaining compatibility with the existing instruction set, by supporting only the post-increment register indirect addressing mode, the increase in the addressing mode is minimized. In addition, the product-sum operation can be executed without lowering the processing performance. Further, correction of the address register can be performed by an inter-register operation instruction, and this can be executed in one state, so that the flexibility of addressing can be improved. Further, by performing the product-sum operation in parallel with the internal operation of the CPU (post-increment address calculation), the number of execution states can be reduced.

  (2) In executing a multiplication instruction using a multiplier, the result of multiplication (product, flag) is directly stored in a general-purpose register or CCR so that the result can be used immediately, The execution speed of the multiplication can be improved. In addition, by reading the result (MAC) of the product-sum operation (STMAC) and storing the flag held in the multiplier in the CCR at the same time, the result of the product-sum operation can be easily used and determined. Can be improved.

  (3) By making the multiplier removable, when the multiplier is removed, the lower CPU can be easily realized by not supporting the product-sum operation, thereby reducing the logical and physical scale, and the manufacturing cost. It is possible to easily develop another microcomputer in which the number is reduced. Further, by supporting a general-purpose multiplication instruction without using a multiplier, it is possible to prevent the usability of such another microcomputer from being reduced. Further, by executing a multiplication instruction which does not depend on the multiplier in the same sequence as the division, redundant logic can be minimized even in a microcomputer having a multiplier.

  In addition, by providing a control signal indicating whether a multiplier is used or not, control can be performed to improve testability and to use a common emulator. Overall development efficiency can be improved. Furthermore, by eliminating the multiplier and configuring the microcomputer using a downsized CPU, the logical scale and the physical scale of the semiconductor integrated circuit can be reduced, and the manufacturing cost can be reduced.

  (4) The multiplier and the CPU are integrally formed to reduce the wiring between the multiplier and the CPU, thereby reducing the physical scale. In addition, it can contribute to speeding up.

  (5) By setting the test mode of the multiplier and performing only one step of the processing of the multiplier at this time, it is possible to minimize the increase in the logic scale and improve the testability. Test steps can be shortened.

  (6) By providing a plurality of register selection circuits having different input / output timings corresponding to the pipeline of the internal operation, one instruction / one state can be executed substantially.

  (7) By having a save / restore instruction for a plurality of registers and fixing this combination, the logical scale can be reduced. By supporting a plurality of instructions having different numbers of registers, it is possible to prevent a decrease in usability. Also, by executing save / restore instructions of a plurality of registers at the entrance / exit of a function (subroutine), the processing speed is particularly improved when the function is frequently used, such as when the function is described in C language or the like. can do. Further, by using the saving of a plurality of registers at the beginning of the interrupt exception handling routine, the real-time property can be improved.

  (8) By switching between valid / invalid of EXR, compatibility can be maintained and function expansion can be achieved at the same time. By disabling EXR and not saving / restoring in exception processing, it is possible to contribute to saving the stack and shortening the interrupt response time. Also, maintain compatibility. Further, by enabling the EXR, the usability can be improved by extending the interrupt mask level and adding a trace function.

  (9) By having a fixed stack pointer for the emulator, at the transition between the user program and the emulation program, saving and restoring to a fixed address are performed independently of the user's stack pointer. Emulator software and hardware development can be facilitated.

  In addition, by fixing the stack pointer for the emulator, resources that are not disclosed to the user can be reduced to a minimum logical and physical scale. By making it possible to prohibit multiple transitions (breaks) from the user program to the emulation program, it is possible to prevent undesired destruction of the contents of the stack.

  The invention made by the inventors of the present invention is not limited to the embodiment, but can be variously changed without departing from the gist of the invention. The embodiments may be used in combination with each other.

  For example, the instruction set and register configuration of the CPU can be changed. The internal bus width can be changed. However, it is desirable that the bus width is not smaller than the instruction code length of most of the instructions.

  Further, the internal configuration of the multiplier can be variously changed. Instead of repeating 16 bits × 6 bits three times, 16 bits × 4 bits may be repeated four lower orders. The selection may be made in consideration of the instruction execution state and the logical scale.

  Further, it goes without saying that the designation of the saturation operation, the designation of the presence / absence of the multiplier, and the designation method of the test mode can be variously changed.

  Furthermore, the present invention is not limited to the multiplier, and may include a divider.

  Further, the object for which compatibility should be maintained is not limited to the above example. Generally, the contents of the control register are saved during exception processing of the CPU, and the functions of the control register are extended to other CPUs while maintaining compatibility by applying the present invention. can do.

  Further, the other functional blocks of the single-chip microcomputer are not restricted at all.

  In the above description, the case where the invention made by the present inventor is mainly applied to a single-chip microcomputer, which is a field of use as a background, has been described. The present invention is applicable to at least a data processing device that operates by selecting a plurality of operation modes.

FIG. 1 is a block diagram illustrating a configuration of a microcomputer according to an embodiment of the present invention. FIG. 3 is a configuration diagram of a system control register of the microcomputer according to the present embodiment. FIG. 2 is a configuration diagram of an instruction format of a CPU used in the microcomputer of the present embodiment. FIG. 2 is a block diagram illustrating a CPU and a multiplier used in the microcomputer of the present embodiment. FIG. 2 is a configuration diagram of one bit of a control register in the microcomputer of the present embodiment. 3 is a block diagram illustrating an example of a control signal setting method in the microcomputer according to the present embodiment. FIG. 4 is a schematic diagram illustrating an example of a control signal setting method in the microcomputer of the present embodiment. FIG. 2 is a configuration diagram of a register of a CPU used in the microcomputer of the present embodiment. FIG. 2 is a configuration diagram of a register of a CPU used in the microcomputer of the present embodiment. FIG. 4 is a block diagram illustrating a method of using a register of a CPU used in the microcomputer of the present embodiment. FIG. 3 is an explanatory diagram of a state of a stack of registers of a CPU used in the microcomputer of the present embodiment. FIG. 3 is a timing chart of a basic operation of a CPU used in the microcomputer of the present embodiment. FIG. 3 is a timing chart of a basic operation of a CPU used in the microcomputer of the present embodiment. FIG. 2 is a block diagram illustrating a configuration of a multiplier used in the microcomputer of the present embodiment. FIG. 4 is an explanatory diagram of a calculation method by a multiplier used in the microcomputer of the present embodiment. FIG. 3 is an explanatory diagram of a method of realizing a flag of a multiplier used in the microcomputer of the present embodiment. FIG. 3 is an explanatory diagram of a method of realizing a flag of a multiplier used in the microcomputer of the present embodiment. FIG. 2 is a block diagram illustrating a configuration of a bus switch used in the microcomputer of the present embodiment. FIG. 4 is a timing chart of an operation of a MAC instruction in the microcomputer of the embodiment. FIG. 20 is a timing chart of the operation following FIG. 19. FIG. 5 is a timing chart of the operation of the STMAC instruction and the LDMAC instruction in the microcomputer of the embodiment. FIG. 22 is a timing chart of the operation following FIG. 21. FIG. 5 is a timing chart of an operation of a multiplication instruction when a multiplier is used in the microcomputer of the present embodiment. FIG. 20 is a timing chart of the operation following FIG. 19. FIG. 5 is a timing chart of an operation of a multiplication instruction when a multiplier is not used in the microcomputer of the present embodiment. FIG. 26 is a timing chart of the operation following FIG. 25. FIG. 4 is a state transition diagram of a multiplication instruction in the microcomputer of the embodiment. FIG. 2 is a block diagram illustrating a configuration of an arithmetic unit used in the microcomputer of the present embodiment. FIG. 5 is an execution sequence diagram of a save instruction of a plurality of registers in the microcomputer according to the present embodiment. FIG. 30 is a timing chart of the operation following FIG. 29. FIG. 5 is an execution sequence diagram of a return instruction of a plurality of registers in the microcomputer of the present embodiment. FIG. 32 is a timing chart of the operation following FIG. 31. FIG. 2 is a block diagram illustrating a configuration of an RSEL2 input control circuit in the microcomputer of the present embodiment. FIG. 34 is an explanatory diagram of the operation in FIG. 33. 3 is a schematic example of a conversion list in C language applied to the microcomputer of the present embodiment. 3 is a schematic example of a conversion list in C language applied to the microcomputer of the present embodiment. FIG. 4 is an execution sequence diagram of interrupt exception processing in the microcomputer of the present embodiment. FIG. 38 is a timing chart of the operation following FIG. 37. FIG. 6 is a state transition diagram of exception processing in the microcomputer of the present embodiment. FIG. 4 is an explanatory diagram of a state of a stack after exception processing in the microcomputer of the present embodiment. FIG. 4 is an explanatory diagram of a state of a stack after exception processing in the microcomputer of the present embodiment. FIG. 3 is an execution sequence diagram of an RTE instruction in the microcomputer of the embodiment. FIG. 6 is a state transition diagram of exception processing in the microcomputer of the present embodiment. FIG. 2 is an explanatory diagram of a configuration of a control circuit in the microcomputer of the present embodiment. FIG. 2 is a configuration diagram of a control register in the microcomputer of the present embodiment. FIG. 2 is a configuration diagram of a control register in the microcomputer of the present embodiment. FIG. 2 is a configuration diagram of a control register in the microcomputer of the present embodiment. FIG. 2 is a configuration diagram of a control register in the microcomputer of the present embodiment. FIG. 2 is a configuration diagram of a control register in the microcomputer of the present embodiment. FIG. 3 is an explanatory diagram of a configuration of an emulation stack pointer in the microcomputer according to the present embodiment. FIG. 4 is a timing chart of the execution of a break interrupt sequence in the microcomputer of the present embodiment. FIG. 3 is a circuit configuration diagram of a break control process in the microcomputer of the present embodiment.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... Multiplier, 3 ... System controller (SYSC), 4 ... Interrupt controller (INT), 5 ... ROM, 6 ... RAM, 9 ... Serial communication interface (SCI), 13 ... System control register (SYSCR) ), 14: control register (CPUCR), 21: instruction register (IR), 22: instruction decoder / control circuit (CONT), 23: register selector (RSEL), 24: write data buffer (DBW), 25: read data Buffers (DBR), 26, 27 arithmetic unit, 29 emulator stack pointer (EMLSP), 30 program counter (PC), 31 condition register (CCR), 32 extension register (EXR), 33 address buffer ( MAB), 34 ... bus switch 38, emulation processor, 39, emulation interface, 44, interface cable, 48, emulation memory, 49, break control circuit, 50, real-time trace circuit, 58, CMOS inverter circuit, 65A to 65C, decoder, 66A to 66C , 71A, 71B, 77: selection circuit, 67: adder, 72A to 72C: expansion circuit, 76: arithmetic and logic operation circuit, 78: shift circuit, 79: control circuit, 75A, 75B, 81A to 81G, 86A to 86D ... AND circuits, 80A, 80B, 82A to 82D ... OR circuits, 83 ... flip-flops.

Claims (6)

A data processing device that sequentially executes a predetermined instruction,
A data processing apparatus, wherein a combination of a plurality of registers that can be specified is fixed to a control unit that controls an execution unit that executes the instruction, and a save / restore instruction for the plurality of registers is provided. 2. The data processing apparatus according to claim 1, wherein the save / restore instructions are a plurality of different types of register combinations that can be specified. 3. The data processing device according to claim 1, wherein the save instruction and the return instruction have the same combination of registers that can be specified. 4. The data processing device according to claim 1, wherein the plurality of registers to be saved / restored are a plurality of registers having consecutive register numbers. 5. The data processing apparatus according to claim 4, wherein the register designator of the instruction code of the save / restore instruction represents a combination of a plurality of registers to be saved / restored by a register number saved first. A data processing device wherein a combination of registers that can be designated by a save / restore instruction is fixed.

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