JP2004221358A - Dielectric memory and method of manufacturing the same - Google Patents

Abstract

An object of the present invention is to provide a dielectric memory capable of preventing a lower electrode, an oxygen barrier film, and a contact plug interface from being peeled off due to oxidation or contact stress of a contact plug of a stacked ferroelectric capacitor, and a highly integrated dielectric memory and a method of manufacturing the same.
The dielectric memory includes a lower electrode (3), a capacitor insulating film (4), and an upper electrode (5), which are sequentially stacked from below on a substrate (1), wherein the lower electrode (3) is provided. ) Is formed so as to cover and extend around the contact plug (6) electrically connected to the substrate (1), and the upper electrode (5) extends in the first direction (upper electrode extension direction). Form. The length of the lower electrode (3) extending above the contact plug (6) (the amount of extension of the lower electrode) is more perpendicular to the first direction of the upper electrode (5) than the first direction (the upper electrode non-extending direction). (Extended direction).
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a dielectric memory and a method of manufacturing the same, and more particularly, to a ferroelectric memory and a high dielectric memory that require high-temperature sintering.
[0002]
[Prior art]
In the development of ferroelectric memories, small-capacity memories of 1 to 64 kbits using a planar type structure have begun to be mass-produced, and recently, large-capacity memories of 256 kbits to 4 Mbits using a stack type structure have become the main focus of development. ing. The structure of the stacked ferroelectric memory aims at reducing the cell size and greatly improving the degree of integration by arranging a contact plug electrically connected to the semiconductor substrate immediately below the lower electrode. In order to realize such a stacked structure, it is important to take measures to prevent the contact plug from being oxidized by high-temperature heat treatment in an oxygen atmosphere for crystallizing the ferroelectric film. Conventionally, an oxygen barrier film is laminated below an electrode material to realize a structure that prevents oxidation of a contact plug (for example, Patent Document 1).
[0003]
Hereinafter, a ferroelectric capacitor structure in a conventional ferroelectric memory will be described with reference to the drawings. 8A to 8C are diagrams showing the main parts of a conventional dielectric memory, where A is a cross-sectional view taken along line VV of C, B is a cross-sectional view taken along line VI-VI of C, and C is a plan view. A ferroelectric capacitor is formed on a first interlayer insulating film 2 on a semiconductor substrate 1. The ferroelectric capacitor includes a lower electrode 3 having a laminated structure made of a conductive oxygen barrier film (for example, Ru, Ir or an oxide thereof) and Pt, a capacitance insulating film 4 made of a ferroelectric film, and an upper electrode 5. The lower electrode 3 is electrically connected via a contact plug 6 to the semiconductor substrate 1 on which the memory cell transistor is formed. Although omitted here, after that, a wiring process is formed on the ferroelectric capacitor after forming the capacitor interlayer insulating film.
[0004]
With the above structure, even during high-temperature heat treatment in an oxygen atmosphere during crystallization of the ferroelectric film, diffusion of oxygen diffusing in the lower electrode is blocked by the oxygen barrier film, and oxidation of the contact plug is prevented. Thus, a highly reliable ferroelectric memory with a high yield can be realized.
[0005]
[Patent Document 1]
JP-A-10-93036
[0006]
[Problems to be solved by the invention]
However, in the above-described conventional example, oxidation of the contact plug from the lateral direction (so-called side oxidation) during ferroelectric sintering cannot be completely prevented. Therefore, as the miniaturization progresses, that is, as the size of the lower electrode becomes smaller, the problem that the contact yield decreases due to side oxidation has become apparent.
[0007]
In addition, at the interface between the lower electrode and the contact plug or the interface when the lower electrode and the oxygen barrier film are laminated, the difference in the thermal expansion coefficient of each material, the behavior with respect to the temperature of the film stress, or the difference in the degree of oxidation, etc. In addition, there is a new problem that peeling occurs at the interface during ferroelectric sintering.
[0008]
In particular, when the ferroelectric film is crystallized, in addition to the high-temperature heat treatment at 650 ° C. or more, in the process of removing the organic components in the ferroelectric film and growing the crystal, the ferroelectric film contracts and large stress migration occurs. . Similarly, stress migration occurs in the upper electrode due to the heat treatment. Although depending on the manufacturing method, when the upper electrode and the ferroelectric film are sintered in a state where they are present on the entire surface of the wafer, the amount of stress change is large, and the firing is performed after the upper electrode and the ferroelectric film are patterned. Even if the bonding is performed, for example, a certain amount of the change in the stress remains in the cell plate direction, and if the stress is concentrated on one lower electrode, this causes the above-described separation to be promoted.
[0009]
The present invention solves the above-mentioned conventional problems by preventing oxidation of a contact plug of a stacked ferroelectric capacitor or peeling of an interface of a lower electrode, an oxygen barrier film, and a contact plug due to stress, thereby achieving a highly integrated dielectric. It is an object to provide a body memory and a method for manufacturing the same.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a first dielectric memory of the present invention is a dielectric memory including a lower electrode, a capacitor insulating film, and an upper electrode formed by sequentially laminating on a substrate from below, The lower electrode is formed so as to cover and extend around the contact plug electrically connected to the substrate, and the upper electrode is formed so as to extend in the first direction, and extends over the contact plug of the lower electrode. The length extending beyond is longer in the direction orthogonal to the first direction than in the first direction.
[0011]
A second dielectric memory according to the present invention is a dielectric memory comprising a lower electrode, a capacitor insulating film, and an upper electrode which are sequentially formed on a substrate from below, wherein the lower electrode is electrically connected to the substrate. The upper electrode is formed so as to cover and extend around the contact plug to be electrically connected, the upper electrode is formed to extend in a first direction, and the length of the lower electrode extending over the contact plug is: In a direction orthogonal to the first direction, the length is set so that the contact plug is not oxidized by invasion of oxygen from the direction.
[0012]
A third dielectric memory according to the present invention is a dielectric memory comprising a lower electrode, a capacitor insulating film, and an upper electrode, which are sequentially stacked on a substrate from below, wherein the lower electrode is electrically connected to the substrate. The upper electrode is formed so as to cover and extend around the contact plug to be electrically connected, the upper electrode is formed to extend in a first direction, and the length of the lower electrode extending over the contact plug is: In the first direction, the length is set so that the lower electrode does not peel off due to the stress of the capacitive insulating film.
[0013]
A fourth dielectric memory according to the present invention is a dielectric memory comprising a lower electrode, a capacitor insulating film, and an upper electrode which are sequentially stacked on a substrate from below, wherein the lower electrode is electrically connected to the substrate. The upper electrode is formed to extend in a first direction, and the contact plug is formed to extend in a first direction, and the contact plug is formed in a direction perpendicular to the first direction. It is characterized by having a long cross-sectional shape in the first direction.
[0014]
A fifth dielectric memory according to the present invention is a dielectric memory comprising a lower electrode, a capacitor insulating film, and an upper electrode which are sequentially formed on a substrate from below, wherein the upper electrode is disposed in a first direction. And the length of the upper electrode in the first direction is 500 μm or less.
[0015]
A sixth dielectric memory according to the present invention is a dielectric memory comprising a lower electrode, a capacitor insulating film, and an upper electrode which are sequentially stacked on a substrate from below, wherein the upper electrode is disposed in a first direction. The upper electrodes are adjacent to each other and electrically connected to each other via a substrate.
[0016]
A seventh dielectric memory according to the present invention is a dielectric memory comprising a lower electrode, a capacitor insulating film, and an upper electrode which are sequentially stacked on a substrate from below, wherein the upper electrode is disposed in a first direction. The upper electrodes adjacent to each other are electrically connected to each other through a wiring layer.
[0017]
According to a first method of manufacturing a dielectric memory of the present invention, a step of forming an insulating film on a substrate; forming a contact plug by opening a predetermined region of the insulating film;
Forming a lower electrode so as to cover the contact plug and spread around the contact plug,
Forming a dielectric film on the lower electrode,
Forming an upper electrode on the dielectric film so as to extend in a first direction;
Heat treating and crystallizing the dielectric after the step of forming the dielectric film,
The step of forming the lower electrode may include forming the lower electrode such that a length of the lower electrode extending above the contact plug is longer in a direction orthogonal to the first direction than in the first direction. Features.
[0018]
According to a second method of manufacturing a dielectric memory of the present invention, an insulating film is formed on a substrate,
Opening a predetermined region of the insulating film to form a contact plug,
Forming a lower electrode so as to cover the contact plug and spread around the contact plug,
Forming a dielectric film on the lower electrode,
Forming an upper electrode on the dielectric film so as to extend in a first direction;
Heat treating and crystallizing the dielectric after the step of forming the dielectric film,
The contact plug is formed so as to have a cross-sectional shape that is longer in the first direction than in a direction orthogonal to the first direction.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
In the first dielectric memory of the present invention, the lower electrode is formed so as to cover a contact plug electrically connected to the substrate and spread around the contact plug, and the upper electrode is formed so as to extend in the first direction. The length of the lower electrode extending over the contact plug is longer in the direction orthogonal to the first direction than in the first direction. With such a configuration, it is possible to prevent a defect of the contact plug and to realize a finer cell.
[0020]
Further, in the first dielectric memory of the present invention, the length of the lower electrode extending over the contact plug is equal to 0.1 mm in a direction perpendicular to the first direction rather than the first direction. It is preferably longer than 1 μm. With such a configuration, the oxidation of the contact plug can be more reliably prevented.
[0021]
In the second dielectric memory of the present invention, the lower electrode is formed so as to cover a contact plug electrically connected to the substrate and spread around the contact plug, and the upper electrode is formed so as to extend in the first direction. The length of the lower electrode extending over the contact plug is set in a direction orthogonal to the first direction such that the contact plug is not oxidized by intrusion of oxygen from that direction. With such a configuration, it is possible to prevent defects due to side oxidation of the contact plug.
[0022]
In the third dielectric memory according to the present invention, the lower electrode is formed so as to cover a contact plug electrically connected to the substrate and spread around the contact plug, and the upper electrode is formed so as to extend in the first direction. The length of the lower electrode extending over the contact plug is set in the first direction to a length that does not cause the lower electrode to peel off due to the stress of the capacitive insulating film. With such a configuration, it is possible to prevent a shape defect such as separation due to stress of the contact plug.
[0023]
In the third dielectric memory of the present invention, it is preferable that a length of the lower electrode extending over the contact plug is equal to or less than 0.25 μm in the first direction. With such a configuration, separation of the contact plug due to stress can be reliably prevented.
[0024]
In a fourth dielectric memory according to the present invention, the lower electrode is formed so as to cover a contact plug electrically connected to the substrate and spread therearound, and the upper electrode is formed so as to extend in the first direction. The contact plug has a cross-sectional shape that is longer in the first direction than in a direction orthogonal to the first direction. With such a configuration, it is possible to prevent a defect of the contact plug and to realize a finer cell.
[0025]
In a fifth dielectric memory according to the present invention, the upper electrode is formed to extend in the first direction, and the length of the upper electrode in the first direction is 500 μm or less. With such a configuration, stress applied to the contact plug from the cell plate direction can be suppressed.
[0026]
In a sixth dielectric memory according to the present invention, the upper electrode is divided into units each having a length of 500 μm or less so as to extend in the first direction, and adjacent upper electrodes are electrically connected to each other via a substrate. ing. In a seventh dielectric memory according to the present invention, the upper electrode is divided into units each having a length of 500 μm or less so as to extend in the first direction, and adjacent upper electrodes are electrically connected via a wiring layer. Have been. With such a configuration, it is possible to suppress only the stress without being restricted by the length direction of the cell plate.
[0027]
In the first to seventh dielectric memories of the present invention, it is preferable that at least a part of the lower electrode includes an oxygen barrier film. With such a structure, oxygen diffused through the lower electrode can be reliably prevented by the oxygen barrier film, and a better effect can be obtained by suppressing the oxidation of the contact plug.
[0028]
In the first to seventh dielectric memories of the present invention, it is preferable that at least a part of the upper electrode includes an oxygen barrier film. With this configuration, oxygen diffused through the upper electrode can be reliably prevented by the oxygen barrier film, and a better effect can be obtained by suppressing the oxidation of the contact plug.
[0029]
According to the first and second methods for manufacturing a dielectric memory of the present invention, side oxidation of a contact plug can be efficiently and rationally prevented.
[0030]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0031]
(1st Embodiment)
FIG. 1A is a cross-sectional view of an upper electrode extension direction (cell plate direction), which is a direction in which upper electrodes of a dielectric memory according to a first embodiment of the present invention are connected to each other and extends. FIG. 1B is a direction orthogonal to the upper electrode extension direction. 1C is a cross-sectional view in the non-extending direction (bit line direction) of the upper electrode, and FIG. 1C is a plan view.
[0032]
SiO 2 doped with B, P, etc. on the semiconductor substrate 1 ₂ A first interlayer insulating film 2 (thickness: 500 to 800 nm) made of a (commonly called BPSG) film is formed, and a ferroelectric capacitor is formed thereon. ４００400 nm), SBT (for example, SrBi ₂ Ta ₂ O ₉ ), A capacitive insulating film 4 (film thickness 50 to 200 nm) made of a ferroelectric film and an upper electrode 5 (film thickness 50 to 200 nm). The lower electrode 3 here of the ferroelectric capacitor is connected to the semiconductor substrate 1 via a contact plug 6 made of tungsten (W). Reference numeral 12 denotes an element isolation insulating film (STI).
[0033]
Generally, crystallization of a ferroelectric film is performed in a high-temperature oxygen atmosphere of 650 ° C. or higher. At this time, yield problems such as increase in resistance of a contact plug and abnormal shape (peeling) occur. The causes are oxidation of the lower electrode due to the inflow of oxygen from the outside, and separation of the lower electrode due to a change in thermal stress of the upper electrode and the capacitor insulating film. In the former case, the upper electrode and the ferroelectric film extend in the direction in which the upper electrode extends, and thus provide a barrier to oxygen to some extent. Since there is only an interlayer insulating film, more oxygen diffuses from this direction. Therefore, in the non-extension direction of the upper electrode, it is important to secure a margin for side oxidation by increasing the length of the lower electrode end extending beyond the contact plug end (the amount of extension of the lower electrode) in plan view. It is. For the latter, it is clear that the absolute amount of the upper electrode and the capacitor insulating film with respect to the thermal stress change is greater in the extension direction of the upper electrode, and this amount of the stress change is concentrated on a specific lower electrode to cause peeling. I have. In order to prevent this peeling, it is important to ensure the adhesion. Further, the experiment by the present inventor has revealed that peeling occurs not in a region immediately above the contact plug but in a region other than the contact plug. This is because the material of the contact plug diffuses to the lower electrode immediately above the contact plug, and the adhesion is improved. For this reason, it is important to increase the amount of overlap between the lower electrode and the contact plug in the extension direction of the upper electrode where the stress change is large, that is, to increase the region where the adhesion is improved by the diffusion of the contact plug material.
[0034]
For the above reasons, in the present embodiment, the lower electrode has a rectangular shape that is short in the upper electrode extension direction and long in the upper electrode non-extension direction. As a result, the length of extension of the lower electrode in the non-extension direction of the upper electrode is increased, and the upper electrode, which has a large stress change, is prevented from oxidizing the contact by oxygen flowing from the outside that is not protected by the upper electrode or the capacitor insulating film. By increasing the amount of overlap between the lower electrode and the contact plug in the electrode extension direction, contact failure can be prevented.
[0035]
FIG. 2 shows a conventional square lower electrode and a rectangular lower electrode in which the upper electrode non-extending direction is 0.2 μm larger than the upper electrode extending direction according to the present invention. It shows the value of the contact resistance with respect to the extension amount of the lower electrode in the extension direction of the upper electrode when the heat treatment is performed in an oxygen atmosphere. In the case of a square lower electrode, the extension of the lower electrode is required to be 0.20 μm or more in order for the contact resistance to satisfy the standard value, and when the extension of the lower electrode is 0.15 μm or less, the resistance increases (20 Ω · cm or more). (Upper limit specification cracking), whereas the rectangular lower electrode has not started increasing the resistance to 0.10 μm.
[0036]
As described above, the upper electrode non-extending direction is more susceptible to side oxidation than the upper electrode extending direction, and a rectangular lower electrode in which the upper electrode non-extending direction is 0.2 μm larger than the upper electrode extending direction is used. If it is adopted, it can be understood that the same contact resistance can be obtained even if the extension amount of the lower electrode in the extension direction of the upper electrode is reduced by 0.10 μm as compared with the conventional square-shaped lower electrode.
[0037]
FIG. 3 shows the relationship between the extension amount of the lower electrode with respect to the contact plug of the lower electrode and the number of occurrences of peeling of the lower electrode in the extension direction of the upper electrode. When the extension amount of the lower electrode is 0.25 μm or less, peeling of the lower electrode does not occur, but peeling occurs from 0.3 μm to 0.4 μm, and peeling does not occur when it is 0.5 μm or more.
[0038]
This phenomenon similarly occurs even when stress migration occurs in the extension direction of the upper electrode. The cause is considered as follows.
(1) When the thickness is 0.25 μm or less, the interface having better adhesion right above the contact plug accounts for a large proportion of the entire area, and peeling hardly occurs.
(2) When the thickness is 0.3 to 0.45 μm, the effective ratio of the region having good adhesion directly above the contact plug is reduced, but only the region exposed to the side oxide region is increased, and the adhesion is effectively improved. Does not contribute to peeling, and peeling is likely to occur.
(3) When the thickness is 0.5 μm or more, a region that is not exposed to the side oxide region is sufficiently secured, which leads to an improvement in adhesion.
[0039]
As described above, in consideration of the miniaturization of the cell, it is desirable that the extension amount of the lower electrode in the extension direction of the upper electrode is 0.25 μm or less.
[0040]
Next, a method for manufacturing the dielectric memory according to the present embodiment will be described with reference to FIGS. 1A to 1C are views showing a main part of a dielectric memory according to a first embodiment of the present invention. FIG. 1A is a cross-sectional view taken along line II of FIG. 1C, and FIG. 1B is a line II-II of FIG. 1C. Sectional view, C is a plan view. 7A to 7E are process cross-sectional views illustrating a method for manufacturing a dielectric memory according to an embodiment of the present invention.
[0041]
In FIG. 7A, an interlayer insulating film (for example, BPSG) 2 is formed on the semiconductor substrate 1 formed of the high-concentration impurity diffusion layer and the isolation region. Next, in FIG. 7B, a contact is opened in the interlayer insulating film 2 using a desired mask, and a contact plug 6 (W, Poly Si) for electrically connecting the semiconductor substrate and the lower electrode of the ferroelectric capacitor is formed. To form Next, in FIG. 7C, a film (Pt) for promoting the crystal growth of the ferroelectric film and a conductive film composed of an oxygen barrier layer (IrO / Ir / TiAlN) are laminated, and a desired mask, that is, an upper portion formed thereon is formed. Using a lower electrode mask having a small width in the direction in which the electrodes extend and a large width in the non-extension direction, patterning is performed so as to cover the first contact plugs 3, and the lower electrode 3 as shown in FIG. To form Next, a lower inter-electrode buried insulating film 11 (for example, O3TEOS, O3 ₃ And Si (OC ₂ H ₅ ) ₄ A film of tetraethylorthosilicate is formed by a CVD method, and the surface of the lower electrode 3 is exposed by using a CMP (chemical mechanical polishing) method. Here, the lower electrode is embedded in the insulating film. However, the present invention is not limited to the structure. Next, as shown in FIG. 7D, a ferroelectric solution is applied by spin coating to form a ferroelectric film 4A. The ferroelectric film is baked at a low temperature of 400 ° C. or less to remove organic components, and subjected to RTP (Rapid Thermal Process) in an oxygen atmosphere for 1 minute at 650 ° C. which serves as a nucleus for crystallization. Is desirable. A conductive film 5A made of Pt is formed thereon. Finally, as shown in FIG. 7E, a ferroelectric film 4 and an upper electrode 5 are formed by patterning using a desired mask so that the lower electrode 3 is covered. Here, the ferroelectric film and the upper electrode are patterned using the same mask, but may be performed using different masks. After patterning, the ferroelectric film is heat-treated at a high temperature and crystallized. In the case of the SBT material, the heat treatment temperature is about 650 ° C. to 800 ° C. By performing sintering after patterning, the stress migration of the upper electrode and the ferroelectric film can be limited to the direction in which the upper electrode extends, and at the same time, the lower electrode moves in the non-extension direction of the upper electrode against side oxidation from the non-extension direction. It can be formed while securing a sufficient extension amount of the lower electrode.
[0042]
(Second embodiment)
4A to 4C are views showing the main part of the dielectric memory according to the second embodiment of the present invention. FIG. 4A is a sectional view taken along the line III-III of FIG. 4C, and FIG. 4B is a line IV-IV of FIG. 4C. Sectional view, C is a plan view. That is, a sectional view of an upper electrode extension direction (cell plate direction), which is a direction in which upper electrodes of the dielectric memory are connected to each other, and an upper electrode non-extension direction (bit line direction), which is a direction orthogonal to the upper electrode extension direction. FIG.
[0043]
A ferroelectric capacitor is formed on a first interlayer insulating film 2 (thickness: 500 to 800 nm) made of a BPSG film on a semiconductor substrate 1, and the lower electrode 3 (thickness: 200 to 400 nm) is formed on the ferroelectric capacitor. ), A capacitive insulating film 4 (50-200 nm in thickness) made of an SBT ferroelectric film, and an upper electrode 5 (50-200 nm in thickness). The lower electrode 3 here of the ferroelectric capacitor is connected to the semiconductor substrate 1 via a W contact plug 6.
[0044]
In contrast to the problem described in the first embodiment, in the present embodiment, the contact plug has a rectangular shape that is long in the upper electrode extension direction and short in the non-extension direction. As a result, the length of extension of the lower electrode in the non-extension direction of the upper electrode is increased, and the upper electrode, which has a large stress change, is prevented from oxidizing the contact by oxygen flowing from the outside that is not protected by the upper electrode or the capacitor insulating film. By increasing the amount of overlap between the lower electrode and the contact plug in the electrode extension direction, contact failure can be prevented.
[0045]
Next, a method of manufacturing the dielectric memory according to the present embodiment will be described with reference to FIGS. 4A and 4B and FIGS.
[0046]
In FIG. 7A, an interlayer insulating film (for example, BPSG) 2 is formed on the semiconductor substrate 1 formed of the high-concentration impurity diffusion layer and the isolation region. Next, in FIG. 7B, using a desired mask, a contact is opened in the interlayer insulating film 2 to electrically connect the semiconductor substrate and the lower electrode of the ferroelectric capacitor as shown in FIG. 4C. 6 (W, Poly Si) is formed. Next, in FIG. 7C, a film (Pt) for promoting crystal growth of a ferroelectric film and a conductive film composed of an oxygen barrier layer (IrO / Ir / TiAlN) are laminated, and a desired mask, that is, a square-shaped lower part is formed. The lower electrode 3 is formed by patterning using the electrode mask so that the first contact plug 3 is covered. Next, a lower inter-electrode buried insulating film 11 (for example, O3TEOS) is formed on the lower electrode 3, and the surface of the lower electrode 3 is exposed using CMP. Here, the lower electrode is embedded in the insulating film. However, the present invention is not limited to the structure. Next, as shown in FIG. 7D, a ferroelectric solution is applied by spin coating to form a ferroelectric film 4A. The ferroelectric film is preferably baked at a low temperature of 400 ° C. or less to remove organic components, and is subjected to RTP in an oxygen atmosphere at 650 ° C. for 1 minute as a nucleus for crystallization later. A conductive film 5A made of Pt is formed thereon. Finally, as shown in FIG. 7E, a ferroelectric film 4 and an upper electrode 5 are formed by patterning using a desired mask so that the lower electrode 3 is covered. Here, the ferroelectric film and the upper electrode are patterned using the same mask, but may be performed using different masks. After patterning, the ferroelectric film is heat-treated at a high temperature and crystallized. The temperature of the SBT material is approximately 650 ° C to 800 ° C. By performing sintering after patterning, the stress migration of the upper electrode and the ferroelectric film can be limited to the direction in which the upper electrode extends, and at the same time, the lower electrode moves in the non-extension direction of the upper electrode against side oxidation from the non-extension direction. It can be formed while securing a sufficient extension amount of the lower electrode.
[0047]
Further, in the first and second embodiments, at least a part of the lower electrode and / or at least a part of the upper electrode are provided with, for example, Ir, IrO, Ru, RuO, TiAlN, TaAlN, TaN, TaSiN, or a laminated structure thereof. It is desirable to include an oxygen barrier film composed of Thus, diffusion of oxygen directly above the contact plug through the contact plug can be prevented.
[0048]
(Third embodiment)
FIG. 5 shows the number of occurrences of peeling of the lower electrode with respect to the total extension in the extension direction of the upper electrode. Here, as for the lower electrode, an RTP heat treatment in an oxygen atmosphere at 800 ° C. for 1 minute is performed using a conventional structure having the same lower electrode extension with respect to the contact plug in both the upper electrode extension direction and the upper electrode non-extension direction.
[0049]
From FIG. 5, it can be seen that peeling is observed from a region where the total extension in the upper electrode extension direction is larger than 500 μm, and that the total extension in the upper electrode extension direction is preferably 500 μm or less.
[0050]
6A and 6B are cross-sectional views of a connection portion between upper electrodes of the dielectric memory according to the third embodiment of the present invention, in which the total extension in the extension direction of the upper electrode is set to 500 μm.
[0051]
A ferroelectric capacitor is formed on a first interlayer insulating film 2 made of a BPSG film on a semiconductor substrate 1. The ferroelectric capacitor includes a lower electrode 3, a capacitive insulating film 4 made of an SBT ferroelectric film. , Upper electrode 5. The lower electrode 3 here of the ferroelectric capacitor is connected to the semiconductor substrate 1 via a W contact plug 6.
[0052]
In FIG. 6A, a contact opening 7 is provided at a specific portion of the capacitance insulating film, and the adjacent upper electrode is electrically connected to the contact opening 7, the lower electrode 3, and the diffusion layer in the semiconductor substrate 1. It is connected.
[0053]
In FIG. 6B, a contact plug 9 is formed at a specific location in the interlayer insulating film 8 formed on the capacitor, and the adjacent upper portion is formed via the contact plug 9 and the wiring 10 formed on the interlayer insulating film 8. The electrodes 7 are electrically connected.
[0054]
As described above, even if the total extension in the upper electrode extension direction is restricted, by connecting the adjacent upper electrode via another conductive layer, the restriction on the total extension in the upper electrode extension direction is effectively eliminated, and the upper electrode is freely extended. Layout.
[0055]
【The invention's effect】
As described above, according to the dielectric memory and the method of manufacturing the same of the present invention, oxidation from the side wall direction from the lower electrode to the contact plug due to oxygen, that is, so-called side oxidation, is prevented, and the stress applied in the upper electrode extension direction is further reduced. Separation inside the lower electrode due to migration and separation at the interface of the contact plug can be prevented.
[Brief description of the drawings]
FIGS. 1A to 1C are diagrams showing main parts of a dielectric memory according to a first embodiment of the present invention, wherein A is a cross-sectional view taken along line II of C, and B is a cross-sectional view taken along line II-II of C; , C is a plan view
FIG. 2 is a diagram showing a relationship between a lower electrode extension amount and a contact resistance in the dielectric memory according to the first embodiment of the present invention.
FIG. 3 is a diagram showing the relationship between the amount of extension of the lower electrode (the direction in which the upper electrode does not extend) and the number of occurrences of peeling in the dielectric memory according to the first embodiment of the present invention.
FIGS. 4A to 4C are views showing a main part of a dielectric memory according to a second embodiment of the present invention, wherein A is a cross-sectional view taken along line III-III of C, and B is a cross-sectional view taken along line IV-IV of C; , C is a plan view
FIG. 5 is a diagram showing the relationship between the length of an upper electrode extending direction and the number of occurrences of peeling in a dielectric memory according to a third embodiment of the present invention.
FIGS. 6A and 6B are cross-sectional views showing connection means between adjacent upper electrodes in a dielectric memory according to a third embodiment of the present invention;
FIGS. 7A to 7E are process cross-sectional views illustrating a method of manufacturing the dielectric memory according to the first and second embodiments of the present invention.
8A to 8C are views showing main parts of a conventional dielectric memory, wherein A is a cross-sectional view taken along line VV of C, B is a cross-sectional view taken along line VI-VI of C, and C is a plan view.
[Explanation of symbols]
1 semiconductor substrate
2 Interlayer insulating film
3 Lower electrode
4 Ferroelectric film (capacitive insulating film)
4A ferroelectric film
5 Upper electrode
5A conductive layer
6 Contact plug (between semiconductor substrate and lower electrode)
7 Contact (capacitive insulating film)
8 Interlayer insulating film on capacitor
9 Contact plug (upper electrode and wiring)
10 AL wiring
11 Lower electrode spacer film
12 Element isolation insulating film (STI)

Claims (13)

A dielectric memory comprising a lower electrode, a capacitor insulating film, and an upper electrode formed by laminating in order from the bottom on a substrate,
The lower electrode is formed so as to cover a contact plug electrically connected to the substrate and spread around the contact plug,
The upper electrode is formed to extend in a first direction,
A dielectric memory, wherein a length of the lower electrode extending over the contact plug is longer in a direction orthogonal to the first direction than in the first direction. 2. The dielectric memory according to claim 1, wherein a length of the lower electrode extending above the contact plug is longer than the first direction by 0.1 μm or more in a direction orthogonal to the first direction. 3. A dielectric memory comprising a lower electrode, a capacitor insulating film, and an upper electrode formed by laminating in order from the bottom on a substrate,
The lower electrode is formed so as to cover a contact plug electrically connected to the substrate and spread around the contact plug,
The upper electrode is formed to extend in a first direction,
A length of the lower electrode extending over the contact plug is set in a direction orthogonal to the first direction so that the contact plug is not oxidized by intrusion of oxygen from the direction. Characteristic dielectric memory. A dielectric memory comprising a lower electrode, a capacitor insulating film, and an upper electrode formed by laminating in order from the bottom on a substrate,
The lower electrode is formed so as to cover a contact plug electrically connected to the substrate and spread around the contact plug,
The upper electrode is formed to extend in a first direction,
The length of the lower electrode extending over the contact plug is set in the first direction to a length that does not cause separation of the lower electrode due to stress of the capacitive insulating film. Dielectric memory. 5. The dielectric memory according to claim 4, wherein a length of the lower electrode extending over the contact plug is equal to or less than 0.25 [mu] m in the first direction. A dielectric memory comprising a lower electrode, a capacitor insulating film, and an upper electrode formed by laminating in order from the bottom on a substrate,
The lower electrode is formed so as to cover a contact plug electrically connected to the substrate and spread around the contact plug,
The upper electrode is formed to extend in a first direction,
2. The dielectric memory according to claim 1, wherein the contact plug has a cross section longer in the first direction than in a direction orthogonal to the first direction. A dielectric memory comprising a lower electrode, a capacitor insulating film, and an upper electrode formed by laminating in order from the bottom on a substrate,
The upper electrode is formed to extend in a first direction,
The length of the upper electrode in the first direction is 500 μm or less. A dielectric memory comprising a lower electrode, a capacitor insulating film, and an upper electrode formed by laminating in order from the bottom on a substrate,
The dielectric memory, wherein the upper electrode is formed so as to extend in a first direction by a unit of a length of 500 μm or less, and the adjacent upper electrodes are electrically connected via a substrate. . A dielectric memory comprising a lower electrode, a capacitor insulating film, and an upper electrode formed by laminating in order from the bottom on a substrate,
The upper electrode is divided and formed in units of a length of 500 μm or less so as to extend in a first direction, and the adjacent upper electrodes are electrically connected via a wiring layer. memory. 10. The dielectric memory according to claim 1, wherein at least a part of said lower electrode includes an oxygen barrier film. The dielectric memory according to claim 1, wherein at least a part of the upper electrode includes an oxygen barrier film. Forming an insulating film on the substrate, forming a contact plug by opening a predetermined region of the insulating film,
Forming a lower electrode so as to cover the contact plug and spread around the contact plug,
Forming a dielectric film on the lower electrode,
Forming an upper electrode on the dielectric film so as to extend in a first direction;
Heat treating and crystallizing the dielectric after the step of forming the dielectric film,
The step of forming the lower electrode may include forming the lower electrode such that a length of the lower electrode extending above the contact plug is longer in a direction orthogonal to the first direction than in the first direction. A method for manufacturing a dielectric memory. Forming an insulating film on the substrate,
Opening a predetermined region of the insulating film to form a contact plug,
Forming a lower electrode so as to cover the contact plug and spread around the contact plug,
Forming a dielectric film on the lower electrode,
Forming an upper electrode on the dielectric film so as to extend in a first direction;
Heat treating and crystallizing the dielectric after the step of forming the dielectric film,
The method of manufacturing a dielectric memory according to claim 1, wherein the contact plug is formed to have a cross section longer in the first direction than in a direction orthogonal to the first direction.

Images