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JP2004221555A - Semiconductor element with film, semiconductor device, and method of manufacturing the same - Google Patents

Semiconductor element with film, semiconductor device, and method of manufacturing the same Download PDF

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JP2004221555A
JP2004221555A JP2003421636A JP2003421636A JP2004221555A JP 2004221555 A JP2004221555 A JP 2004221555A JP 2003421636 A JP2003421636 A JP 2003421636A JP 2003421636 A JP2003421636 A JP 2003421636A JP 2004221555 A JP2004221555 A JP 2004221555A
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film
semiconductor
semiconductor element
semiconductor device
manufacturing
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Hitoshi Kawaguchi
均 川口
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J-SIP WALTON KK
Ibiden Co Ltd
Disco Corp
Sumitomo Bakelite Co Ltd
Toppan Inc
Resonac Corp
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J-SIP WALTON KK
Ibiden Co Ltd
Hitachi Chemical Co Ltd
Sumitomo Bakelite Co Ltd
Toppan Printing Co Ltd
Disco Abrasive Systems Ltd
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Publication of JP2004221555A publication Critical patent/JP2004221555A/en
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Abstract

【課題】 半導体素子を含む半導体装置を小型化する。
【解決手段】 複数の素子が形成された半導体基板101の素子形成面の反対面全面にフィルム104を貼り付ける工程と、素子毎の外縁に沿って所定幅でフィルム104を選択的に除去する工程と、フィルム104を選択的に除去する工程と同時または当該工程の後に、半導体基板101を外縁に沿って切断し、形成領域よりも小さく形成されたフィルム104が貼り付けられた複数の半導体素子102に分割する工程とによりフィルム付き半導体素子106を製造する。このように形成された複数のフィルム付き半導体素子106を積層して半導体装置を製造する。
【選択図】 図1



To reduce the size of a semiconductor device including a semiconductor element.
SOLUTION: A step of attaching a film 104 to an entire surface opposite to an element forming surface of a semiconductor substrate 101 on which a plurality of elements are formed, and a step of selectively removing the film 104 with a predetermined width along an outer edge of each element. And at the same time as or after the step of selectively removing the film 104, the semiconductor substrate 101 is cut along the outer edge, and the plurality of semiconductor elements 102 to which the film 104 formed smaller than the formation region is attached. The semiconductor device 106 with a film is manufactured by the step of dividing into two. A semiconductor device is manufactured by laminating a plurality of semiconductor elements with a film 106 thus formed.
[Selection diagram] Fig. 1



Description

本発明は、フィルム付き半導体素子、半導体装置およびそれらの製造方法に関する。   The present invention relates to a semiconductor element with a film, a semiconductor device, and a method for manufacturing the same.

近年の電子機器の高機能化並びに軽薄短小化の要求に伴い、電子部品の高密度集積化、さらには高密度実装化が進んできている。これらの電子機器に使用される半導体パッケージは、小型化かつ多ピン化してきており、また、半導体パッケージを含めた電子部品を実装する、実装用基板も小型化してきている。さらには電子機器への収納性を高めるため、リジット基板とフレキシブル基板を積層し一体化して、折り曲げを可能としたリジットフレックス基板が、実装用基板として使われるようになってきている。   2. Description of the Related Art In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and high-density mounting of electronic components have been progressing. Semiconductor packages used in these electronic devices have become smaller and have more pins, and mounting substrates for mounting electronic components including the semiconductor packages have also become smaller. Furthermore, in order to enhance the storage in electronic devices, a rigid-flex board, in which a rigid board and a flexible board are laminated and integrated to be bent, has been used as a mounting board.

半導体パッケージの小型化に伴い、回路基板上にチップを実装したBGA(Ball Grid Array)やCSP(Chip Scale Package)等のエリア実装型の新しい方式が提案されている。これらの半導体パッケージにおいて、半導体チップの電極とサブストレートの端子との電気的接続方法として、ワイヤボンディング方式やTAB(Tape Automated Bonding)方式、FC(Frip Chip)方式等が用いられている。ここで、サブストレートは、半導体パッケージ用基板とも呼ばれ、プラスチックやセラミックス等各種材料を使って構成され、従来型半導体パッケージのリードフレームの機能を有する。   With the miniaturization of the semiconductor package, a new method of area mounting type such as BGA (Ball Grid Array) or CSP (Chip Scale Package) in which a chip is mounted on a circuit board has been proposed. In these semiconductor packages, a wire bonding method, a TAB (Tape Automated Bonding) method, an FC (Flip Chip) method, or the like is used as an electrical connection method between the electrode of the semiconductor chip and the terminal of the substrate. Here, the substrate is also called a substrate for a semiconductor package, is made of various materials such as plastic and ceramics, and has a function of a lead frame of a conventional semiconductor package.

しかし、上記のような従来の工法では一つの半導体パッケージに対し半導体素子を一つしか収納できないため、半導体パッケージの小型化には自ずと限界があった。このため、複数個の半導体素子を積み重ねて一つの半導体パッケージの内部に収納することにより、実装密度を向上させる手法が提案されている。   However, in the conventional method as described above, only one semiconductor element can be accommodated in one semiconductor package, and there is naturally a limit to miniaturization of the semiconductor package. For this reason, a method has been proposed in which a plurality of semiconductor elements are stacked and housed in one semiconductor package to improve the mounting density.

ところで、半導体素子は、外部のリードフレームまたはサブストレートと電気的に接続される必要がある。サブストレート直上に設けられた半導体素子は、フリップチップ方式でサブストレートに接続されることもあるが、上層に設けられた半導体素子は、素子形成面に電極パッドが形成され、電極パッドを介してサブストレートと電気的に接続される。電極パッドとサブストレートとは、たとえばワイヤボンディングによる金線接合により接続される。   Incidentally, the semiconductor element needs to be electrically connected to an external lead frame or substrate. The semiconductor element provided directly above the substrate may be connected to the substrate by a flip chip method, but the semiconductor element provided in the upper layer has an electrode pad formed on the element formation surface, and via the electrode pad. It is electrically connected to the substrate. The electrode pad and the substrate are connected by, for example, gold wire bonding by wire bonding.

複数個の半導体素子を積層する場合、下層の半導体素子の電極パッドを露出させるため、また下層のワイヤボンディングによる金線接合と上層の半導体素子との干渉を避けるため、上層の半導体素子は下層の半導体素子よりも小さく形成される必要があり、実装上の制約が大きくなっている。   When a plurality of semiconductor elements are stacked, the upper semiconductor element is formed on the lower layer in order to expose the electrode pads of the lower semiconductor element and to avoid interference between the gold wire bonding by the lower wire bonding and the upper semiconductor element. It must be formed smaller than a semiconductor element, and mounting restrictions are increasing.

以上のような問題を解決するために、たとえば、特許文献1には、ほぼ同じサイズの半導体チップを積層する際に、上層の半導体チップの端を局所的に研削して凹部を設け、凹部の空間を利用して下層の半導体チップの電極パッドとボンディングワイヤとの接続を行う技術が開示されている。   In order to solve the above problems, for example, in Patent Document 1, when stacking semiconductor chips of substantially the same size, a concave portion is formed by locally grinding the edge of an upper semiconductor chip, and forming a concave portion. There is disclosed a technology for connecting an electrode pad of a lower semiconductor chip and a bonding wire using a space.

また、特許文献2には、下層の半導体素子のワイヤボンディング部に干渉しないように、上層の半導体素子の一部を研削してから、半導体素子を積層する技術が開示されている。
特開平10−70232号公報 特開2000−58742号公報
Patent Document 2 discloses a technique in which a part of an upper semiconductor element is ground and then a semiconductor element is stacked so as not to interfere with a wire bonding portion of a lower semiconductor element.
JP-A-10-70232 JP 2000-58742 A

しかし、従来の方法では、パッケージサイズが大きくなったり、プロセスが複雑になるなどの問題点があった。   However, the conventional method has problems such as an increase in package size and a complicated process.

本発明は上記事情を踏まえてなされたものであり、本発明の目的は、半導体素子を含む半導体装置を小型化する技術を提供することにある。本発明の別の目的は、このような半導体装置を簡易に製造する技術を提供することにある。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a technique for reducing the size of a semiconductor device including a semiconductor element. Another object of the present invention is to provide a technique for easily manufacturing such a semiconductor device.

本発明によれば、半導体素子と、半導体素子の素子形成面の反対面に接着されたフィルムと、を含み、フィルムは、半導体素子と接着する接着面において、半導体素子よりも小さく形成されたことを特徴とするフィルム付き半導体素子が提供される。   According to the present invention, the semiconductor device includes a semiconductor device and a film bonded to the surface opposite to the device forming surface of the semiconductor device, and the film is formed smaller than the semiconductor device on the bonding surface bonded to the semiconductor device. A semiconductor device with a film is provided.

ここで、フィルムは、このようなフィルム付き半導体素子が複数積層されたときに、下層の半導体素子の素子形成面からのびるボンディングワイヤ等が上層の半導体素子と干渉することのないような膜厚を有する。これにより、複数のフィルム付き半導体素子を積層した場合に、互いに電気的な干渉が生じることなく、安定的な積層体を製造することができる。   Here, the film has a thickness such that when a plurality of such semiconductor elements with a film are stacked, bonding wires extending from the element formation surface of the lower semiconductor element do not interfere with the upper semiconductor element. Have. Accordingly, when a plurality of semiconductor elements with a film are stacked, a stable stacked body can be manufactured without causing electrical interference with each other.

本発明によれば、配線基板と、配線基板上に素子形成面が上となるように配置された第一の半導体素子と、第一の半導体素子の素子形成面に接着されたフィルムと、を含み、フィルムは、第一の半導体素子と接着する接着面において、第一の半導体素子よりも小さく形成されたことを特徴とする半導体装置が提供される。   According to the present invention, a wiring substrate, a first semiconductor element disposed on the wiring substrate so that the element formation surface is facing up, and a film adhered to the element formation surface of the first semiconductor element, A semiconductor device is provided, characterized in that the film is formed smaller than the first semiconductor element on an adhesion surface for adhering to the first semiconductor element.

これにより、フィルムの上層に他の半導体素子を積層しても、下層の第一の半導体素子と他の半導体素子とが電気的に干渉することなく、安定的な積層体を製造することができる。ここで、配線基板は、インターポーザーやプリント基板である。   Thereby, even if another semiconductor element is laminated on the upper layer of the film, the first semiconductor element in the lower layer and the other semiconductor element do not electrically interfere with each other, and a stable laminate can be manufactured. . Here, the wiring board is an interposer or a printed board.

本発明の半導体装置は、フィルムを介して第一の半導体素子と接着された第二の半導体素子をさらに含むことができ、第二の半導体素子の素子形成面の反対面がフィルムと接着してよい。   The semiconductor device of the present invention can further include a second semiconductor element bonded to the first semiconductor element via a film, and the surface opposite to the element forming surface of the second semiconductor element is bonded to the film. Good.

ここで、第二の半導体素子は第一の半導体素子以上の大きさとすることができる。本発明の半導体装置において、第一の半導体素子上に形成されたフィルムは、第一の半導体素子よりも小さく形成される。そのため、フィルムがスペーサーの役目を果たし、第二の半導体素子102を第一の半導体素子以上の大きさとしても、第一の半導体素子と第二の半導体素子との間に隙間が生じる。これにより、下層の第一の半導体素子の素子形成面に設けられた電極パッドからのびるボンディングワイヤ等を外部の端子と接続しても、ボンディングワイヤと上層の半導体素子が干渉することなく、半導体装置を安定的に製造することができる。   Here, the second semiconductor element can be larger than the first semiconductor element. In the semiconductor device of the present invention, the film formed on the first semiconductor element is formed smaller than the first semiconductor element. Therefore, even if the film functions as a spacer and the second semiconductor element 102 is larger than the first semiconductor element, a gap is generated between the first semiconductor element and the second semiconductor element. Accordingly, even when a bonding wire or the like extending from an electrode pad provided on the element formation surface of the lower first semiconductor element is connected to an external terminal, the bonding wire and the upper semiconductor element do not interfere with each other, and Can be manufactured stably.

本発明によれば、半導体素子と、半導体素子の素子形成面の反対面に接着され、半導体素子と接着する接着面において、半導体素子よりも小さく形成されたフィルムと、を含むフィルム付き半導体素子を複数積層した半導体装置が提供される。   According to the present invention, a semiconductor device with a film including a semiconductor element and a film bonded to a surface opposite to the element forming surface of the semiconductor element, and a film formed smaller than the semiconductor element on an adhesive surface bonded to the semiconductor element is provided. A stacked semiconductor device is provided.

このように、フィルムを半導体素子よりも小さくすることにより、フィルム付き半導体素子を積層したときに、下層の半導体素子と上層の半導体素子との間に隙間を生じることができ、下層の半導体素子からのびるボンディングワイヤ等が上層の半導体素子と干渉するのを防ぐことができる。   Thus, by making the film smaller than the semiconductor element, when the semiconductor elements with a film are stacked, a gap can be created between the lower semiconductor element and the upper semiconductor element, and the lower semiconductor element It is possible to prevent the extending bonding wire and the like from interfering with the upper semiconductor element.

本発明によれば、複数の素子が形成された半導体基板の素子形成面の反対面全面にフィルムを貼り付ける工程と、素子毎の外縁に沿って所定幅でフィルムを選択的に除去する工程と、フィルムを選択的に除去する工程と同時または当該工程の後に、半導体基板を外縁に沿って切断し、当該外縁で囲まれた領域よりも小さく形成されたフィルムが貼り付けられた複数の半導体素子に分割する工程と、を含むフィルム付き半導体素子の製造方法が提供される。   According to the present invention, a step of attaching a film to the entire surface opposite to the element forming surface of the semiconductor substrate on which a plurality of elements are formed, and a step of selectively removing the film at a predetermined width along the outer edge of each element A plurality of semiconductor elements to which a semiconductor substrate is cut along an outer edge at the same time as or after the step of selectively removing a film, and a film formed smaller than a region surrounded by the outer edge is attached. And a method for producing a semiconductor device with a film.

このように、半導体基板にフィルムを貼り付けた後にフィルムの不要部分を除去し、それと同時またはその後に半導体基板を分割するので、効率よくフィルム付き半導体素子を製造することができる。   As described above, unnecessary portions of the film are removed after the film is attached to the semiconductor substrate, and the semiconductor substrate is divided at the same time or thereafter, so that a semiconductor device with a film can be efficiently manufactured.

本発明のフィルム付き半導体素子の製造方法において、フィルムを選択的に除去する工程において、第一の切断機で半導体基板の反対面側から所定幅のフィルムを除去することができる。   In the method of manufacturing a semiconductor device with a film according to the present invention, in the step of selectively removing the film, the film having a predetermined width can be removed from the opposite surface side of the semiconductor substrate by the first cutter.

本発明のフィルム付き半導体素子の製造方法において、半導体素子に分割する工程において、第一の切断機よりも幅が狭い第二の切断機で半導体基板を切断することができる。なお、この場合、半導体素子に分割する工程は、フィルムを選択的に除去する工程の後に行ってもよいが、これらの工程を同時に行うこともできる。半導体基板の切断は、フィルムを選択的に除去する工程の後に、半導体基板の素子形成面または反対面から行うこともできるが、第一の切断機でフィルムを除去する工程と略同時に、半導体基板の反対面から第二の切断機で行うこともできる。これにより、フィルム付き半導体素子を効率よく製造することができる。また、半導体基板の素子形成面と反対面の両側から切断機を用いて切断を行うことにより、切断面の荒れを防ぎ、切断面を良好な状態にすることができる。   In the method for manufacturing a semiconductor device with a film according to the present invention, in the step of dividing the semiconductor device into semiconductor devices, the semiconductor substrate can be cut by a second cutting machine that is narrower than the first cutting machine. In this case, the step of dividing into semiconductor elements may be performed after the step of selectively removing the film, but these steps may be performed simultaneously. After the step of selectively removing the film, the cutting of the semiconductor substrate can be performed from the element forming surface or the opposite surface of the semiconductor substrate, but substantially simultaneously with the step of removing the film with the first cutting machine, From the opposite side with a second cutting machine. Thereby, a semiconductor element with a film can be manufactured efficiently. Further, by using a cutting machine to cut from both sides opposite to the element forming surface of the semiconductor substrate, roughening of the cut surface can be prevented, and the cut surface can be in a good state.

本発明によれば、半導体素子と、半導体素子の素子形成面の反対面に接着され、半導体素子と接着する接着面において、半導体素子よりも小さく形成されたフィルムと、を含むフィルム付き半導体素子を複数積層する工程を含むことを特徴とする半導体装置の製造方法が提供される。   According to the present invention, a semiconductor device with a film including a semiconductor element and a film bonded to a surface opposite to the element forming surface of the semiconductor element, and a film formed smaller than the semiconductor element on an adhesive surface bonded to the semiconductor element is provided. A method for manufacturing a semiconductor device, comprising a step of stacking a plurality of semiconductor devices, is provided.

以上のように、本発明によれば、収容する半導体素子のサイズに限定されることなく、半導体素子を複数個収容したパッケージを得ることができる。   As described above, according to the present invention, a package accommodating a plurality of semiconductor elements can be obtained without being limited by the size of the semiconductor elements accommodated.

本発明によれば、半導体素子を含む半導体装置を小型化することができる。また、本発明によれば、このような半導体装置を簡易に製造することができる。   According to the present invention, a semiconductor device including a semiconductor element can be reduced in size. Further, according to the present invention, such a semiconductor device can be easily manufactured.

図1は、本発明の実施の形態におけるフィルム付き半導体素子の製造方法を示す工程断面図である。
本実施の形態において、図1(f)に示すように、半導体素子102にフィルム104が貼り付けられたフィルム付き半導体素子106を作製し、フィルム付き半導体素子106を積層して半導体装置を製造する。ここで、フィルム104は、半導体素子102と接着する接着面において、半導体素子102よりも小さく形成される。これにより、フィルム付き半導体素子106を積層した際に、下層の半導体素子102と上層の半導体素子102との間に隙間ができる。そのため、下層の半導体素子102に設けられた電極パッドと外部のインターポーザー等の基板とをボンディングワイヤで接続する際に、ボンディングワイヤと上層の半導体素子102との干渉を防ぐことができる。
FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device with a film according to an embodiment of the present invention.
In this embodiment, as shown in FIG. 1F, a semiconductor element with a film 106 in which a film 104 is attached to a semiconductor element 102 is manufactured, and the semiconductor element with a film is laminated to manufacture a semiconductor device. . Here, the film 104 is formed to be smaller than the semiconductor element 102 on the bonding surface to be bonded to the semiconductor element 102. Thus, when the semiconductor elements with a film 106 are stacked, a gap is formed between the lower semiconductor element 102 and the upper semiconductor element 102. Therefore, when an electrode pad provided on the lower semiconductor element 102 and a substrate such as an external interposer are connected by a bonding wire, interference between the bonding wire and the upper semiconductor element 102 can be prevented.

まず、半導体基板101を準備し(図1(a))、素子形成面の反対面である裏面全面にフィルム104を貼り付ける(図1(b))。ここで、フィルム104は、ダイボンド用の接着フィルムである。フィルム104の膜厚は、フィルム付き半導体素子106を積層した際に、下層の半導体素子102からのびるボンディングワイヤが上層の半導体素子102と接触しないように、下層の半導体素子102の機能面の高さとボンディングワイヤの最頂部の高さの差以上とすることができる。より好ましくは、フィルム104の膜厚は、半導体素子102の機能面の高さとボンディングワイヤの最頂部の高さの差よりさらに50μm以上厚くすることができる。   First, a semiconductor substrate 101 is prepared (FIG. 1A), and a film 104 is attached to the entire back surface opposite to the element formation surface (FIG. 1B). Here, the film 104 is an adhesive film for die bonding. The thickness of the film 104 is determined by the height of the functional surface of the lower semiconductor element 102 so that a bonding wire extending from the lower semiconductor element 102 does not contact the upper semiconductor element 102 when the film-attached semiconductor elements 106 are stacked. It can be greater than or equal to the difference in height at the top of the bonding wire. More preferably, the thickness of the film 104 can be made 50 μm or more larger than the difference between the height of the functional surface of the semiconductor element 102 and the height of the top of the bonding wire.

フィルム104としては、たとえば、DF−402(日立化成工業株式会社製)を用いることができる。フィルム104の膜厚は、とくに限定されないが、たとえば10μm以上200μm以下とすることができる。このようなフィルムを上記高さとなるように、適宜積層させて用いることができる。   As the film 104, for example, DF-402 (manufactured by Hitachi Chemical Co., Ltd.) can be used. The thickness of the film 104 is not particularly limited, but may be, for example, 10 μm or more and 200 μm or less. Such a film can be used by being appropriately laminated so as to have the above height.

フィルム104は、ロールラミネーター、真空弾性体プレス、真空ラミネーター等の既存の方法で半導体基板101に貼り付けることができる。半導体基板101の反りを抑制するためには、ロールでの貼り付けよりも、面圧を用いて、できるだけ低温で貼り付けることが好ましい。   The film 104 can be attached to the semiconductor substrate 101 by an existing method such as a roll laminator, a vacuum elastic body press, and a vacuum laminator. In order to suppress the warpage of the semiconductor substrate 101, it is preferable that the semiconductor substrate 101 is attached at a temperature as low as possible using surface pressure, rather than using a roll.

つづいて、フィルム104を選択的に除去する(図1(c))。フィルム104は、フィルム付き半導体素子106を積層した際に、下層の半導体素子102の電極パッドが露出し、電極パッドからのびるボンディングワイヤが上層の半導体素子102と干渉しないように選択的に除去することができる。フィルム104を除去する方法としては、種々の方法を用いることができるが、たとえば、回転砥石をダイシングマシンに組み付けてフィルム104を部分的に除去する方法を用いることができる。また、フォトリソグラフィー、プラズマ、サンドブラスト、レーザー加工等の他の既知の方法を用いることもできる。なお、フィルム104を部分的に除去する際に、半導体基板101の裏面の一部が同時に除去されてもよい。   Subsequently, the film 104 is selectively removed (FIG. 1C). The film 104 is to be selectively removed so that the electrode pad of the lower semiconductor element 102 is exposed when the semiconductor element 106 with a film is laminated, and the bonding wire extending from the electrode pad does not interfere with the upper semiconductor element 102. Can be. As a method for removing the film 104, various methods can be used. For example, a method for partially removing the film 104 by attaching a rotating grindstone to a dicing machine can be used. Further, other known methods such as photolithography, plasma, sandblasting, and laser processing can also be used. When the film 104 is partially removed, a part of the back surface of the semiconductor substrate 101 may be removed at the same time.

この後、半導体基板101を複数の半導体素子102に分割する(図1(e))。半導体基板101の切断は、たとえばダイシングマシンにより行うことができる。これにより、半導体素子102の素子形成面の反対面に接着面において半導体素子102よりも小さく形成されたフィルム104が貼り付けられたフィルム付き半導体素子106を得ることができる(図1(f))。図2は、フィルム付き半導体素子106を示す斜視図である。   Thereafter, the semiconductor substrate 101 is divided into a plurality of semiconductor elements 102 (FIG. 1E). Cutting of the semiconductor substrate 101 can be performed by, for example, a dicing machine. As a result, a film-equipped semiconductor element 106 can be obtained in which the film 104 formed smaller than the semiconductor element 102 on the adhesive surface is attached to the surface opposite to the element formation surface of the semiconductor element 102 (FIG. 1F). . FIG. 2 is a perspective view showing the semiconductor element 106 with a film.

本実施の形態において、図1(c)に示すように、フィルム104を選択的に除去する工程を含むことにより、複数のフィルム付き半導体素子106を積層したときに、下層の半導体素子102からのびる配線と上層の半導体素子102とが干渉することのないようにできる。これにより、上層の半導体素子102の大きさを考慮することなく、半導体素子の積層体を形成することができる。   In the present embodiment, as shown in FIG. 1C, by including the step of selectively removing the film 104, when a plurality of semiconductor elements 106 with a film are stacked, the semiconductor element 102 extends from the lower semiconductor element 102. The wiring and the upper semiconductor element 102 can be prevented from interfering with each other. Thus, a stacked body of semiconductor elements can be formed without considering the size of the semiconductor element 102 in the upper layer.

図3は、フィルム104が貼り付けられた半導体基板101を裏面から見た平面図である。
図3(a)において、破線120は半導体基板101の素子形成面に形成された素子毎の外縁を示す。図3(b)は、図1(d)で説明したフィルム104を選択的に除去した後の半導体基板101を示す図である。フィルム104は、素子毎の外縁(破線120)に沿って、所定幅で部分的に除去される。その後、素子毎の外縁に沿って半導体基板101が切断される。これにより、図1(f)に示したようなフィルム付き半導体素子106が得られる。
FIG. 3 is a plan view of the semiconductor substrate 101 to which the film 104 is attached, as viewed from the back.
In FIG. 3A, a broken line 120 indicates an outer edge of each element formed on the element formation surface of the semiconductor substrate 101. FIG. 3B is a diagram illustrating the semiconductor substrate 101 after the film 104 described with reference to FIG. 1D is selectively removed. The film 104 is partially removed at a predetermined width along the outer edge (broken line 120) of each element. After that, the semiconductor substrate 101 is cut along the outer edge of each element. Thus, the semiconductor device with film 106 as shown in FIG. 1F is obtained.

図4は、フィルム104を除去する工程および半導体基板101を切断する工程を示す図である。フィルム104を、ダイシングマシンに組み付けた回転砥石122で除去する場合、フィルム104を除去する工程と半導体基板101を切断する工程とは略同時に行うこともできる。この場合、図示したように、半導体基板101の裏面から回転砥石122でフィルム104を除去するとともに、引き続いて半導体基板101の裏面からダイシングマシンの歯124により半導体基板101を切断する。これにより、切断面の荒れを低減するとともに、工程を短縮することもできる。また、半導体基板101の裏面から回転砥石122でフィルム104を除去した後、半導体基板101の裏面に固定用テープを貼り付け、素子形成面からダイシングマシンの歯124により半導体基板101を切断することもできる。固定用テープを用いることにより、半導体基板101を切断した際に、これらがばらばらになるのを防ぐことができる。   FIG. 4 is a diagram showing a step of removing the film 104 and a step of cutting the semiconductor substrate 101. When removing the film 104 with the rotary grindstone 122 assembled to the dicing machine, the step of removing the film 104 and the step of cutting the semiconductor substrate 101 can be performed substantially simultaneously. In this case, as shown in the drawing, the film 104 is removed from the back surface of the semiconductor substrate 101 by the rotating grindstone 122, and the semiconductor substrate 101 is subsequently cut from the back surface of the semiconductor substrate 101 by the teeth 124 of the dicing machine. Thereby, the roughness of the cut surface can be reduced, and the process can be shortened. Alternatively, after removing the film 104 from the back surface of the semiconductor substrate 101 with the rotating grindstone 122, a fixing tape may be attached to the back surface of the semiconductor substrate 101, and the semiconductor substrate 101 may be cut from the element formation surface with the teeth 124 of a dicing machine. it can. By using the fixing tape, it is possible to prevent the semiconductor substrate 101 from being separated when the semiconductor substrate 101 is cut.

図5は、図1(f)および図2に示したフィルム付き半導体素子106を積層して半導体装置を製造する手順を示す工程断面図である。
まず、一つのフィルム付き半導体素子106をインターポーザー108上に載置し、フィルム付き半導体素子106の素子形成面に形成された電極パッド(不図示)とインターポーザー108とをボンディングワイヤ110で電気的に接続する(図5(a))。ボンディングワイヤ110としては、金やアルミニウム等の金属を用いることができる。
FIG. 5 is a process cross-sectional view showing a procedure for manufacturing a semiconductor device by laminating the semiconductor elements with a film 106 shown in FIGS. 1F and 2.
First, one semiconductor element with film 106 is placed on the interposer 108, and an electrode pad (not shown) formed on the element forming surface of the semiconductor element with film 106 and the interposer 108 are electrically connected with the bonding wire 110. (FIG. 5A). As the bonding wire 110, a metal such as gold or aluminum can be used.

つづいて、フィルム付き半導体素子106上に別のフィルム付き半導体素子106を積層し、上層のフィルム付き半導体素子106の素子形成面に形成された電極パッド(不図示)とインターポーザー108とをボンディングワイヤ110で電気的に接続する(図5(b))。   Subsequently, another semiconductor element with a film 106 is laminated on the semiconductor element with a film 106, and an electrode pad (not shown) formed on the element forming surface of the semiconductor element with a film 106 in the upper layer is bonded to an interposer 108 with a bonding wire. Electrical connection is made at 110 (FIG. 5B).

その後、トランスファモールド等により、封止材114で積層されたフィルム付き半導体素子106を封止してパッケージ化する。封止材114としては、たとえばEME−G770(住友ベークライト株式会社製)等のエポキシ封止樹脂を用いることができる。この後、インターポーザー108の裏面(フィルム付き半導体素子106の搭載面と反対の面)に、半田ボール112を形成する。これにより、構成の半導体装置100が得られる(図5(c))。   Thereafter, the semiconductor element with film 106 laminated with the sealing material 114 is sealed and packaged by transfer molding or the like. As the sealing material 114, for example, an epoxy sealing resin such as EME-G770 (manufactured by Sumitomo Bakelite Co., Ltd.) can be used. Thereafter, a solder ball 112 is formed on the back surface of the interposer 108 (the surface opposite to the mounting surface of the semiconductor element 106 with a film). Thereby, the semiconductor device 100 having the configuration is obtained (FIG. 5C).

以下、実施例により本発明を具体的に説明するが、本発明はこれに限定されるものではない。   Hereinafter, the present invention will be described specifically with reference to Examples, but the present invention is not limited thereto.

複数の素子が形成された半導体基板(厚さ200μm)の素子形成面の反対面全面にロールラミネーターにより、厚さ83μmのダイボンド用フィルム(DF−402、日立化成工業株式会社)を貼り付けた。次に、回転砥石により半導体基板に形成された素子毎の外縁に沿って、外縁から幅500μmのフィルムを除去した。ここで、回転砥石の幅は1mmのものを用いた。   A die bonding film (DF-402, Hitachi Chemical Co., Ltd.) having a thickness of 83 μm was attached by a roll laminator to the entire surface opposite to the element formation surface of the semiconductor substrate (200 μm thick) on which a plurality of elements were formed. Next, a film having a width of 500 μm was removed from the outer edge along the outer edge of each element formed on the semiconductor substrate by the rotating grindstone. Here, the width of the rotating grindstone was 1 mm.

この後、ダイシングマシンにより半導体素子(7mm×8mm)を個片化した。ここで、ダイシングマシンの歯の幅は35μmのものを用いた。   Thereafter, the semiconductor elements (7 mm × 8 mm) were singulated by using a dicing machine. Here, a dicing machine having a tooth width of 35 μm was used.

このフィルム付き半導体素子を、表面にボンディングフィンガーが形成され、裏面に半田ボール搭載用のランドが形成されたプリント配線板に搭載し、ウェッジボンディングの手法を用いて金線により半導体素子とプリント配線板を接続した。   The semiconductor element with the film is mounted on a printed wiring board having bonding fingers formed on the front surface and lands for mounting solder balls on the rear surface, and the semiconductor element and the printed wiring board are connected by gold wires using a wedge bonding technique. Connected.

さらに、別のフィルム付き半導体素子を、上記工程によりプリント配線板に搭載されたフィルム付き半導体素子上に搭載した後、ウェッジボンディングの手法を用いて金線により上層の半導体素子とプリント配線板を接続した。   Furthermore, after another semiconductor element with a film is mounted on the semiconductor element with a film mounted on the printed wiring board by the above process, the upper layer semiconductor element and the printed wiring board are connected by a gold wire using a wedge bonding technique. did.

つづいて、2つの半導体素子が積層して搭載されたプリント配線板の表面を封止樹脂により封止し、裏面に半田ボールを搭載し、BGAパッケージを形成した。このようにして得られた半導体装置を、プリント配線板に実装し、動作確認を行った結果、半導体装置として正常に動作することが確認された。   Subsequently, the surface of the printed wiring board on which the two semiconductor elements were stacked and mounted was sealed with a sealing resin, and solder balls were mounted on the back surface to form a BGA package. The semiconductor device obtained in this manner was mounted on a printed wiring board, and operation was confirmed. As a result, it was confirmed that the semiconductor device normally operated.

なお、本発明は、以下の態様も含む。
[1] 半導体素子の機能面の裏面に半導体素子より小さな面積のダイボンド用フィルムを備えてなることを特徴とする半導体素子、
[2] (A)半導体ウエハー機能面の裏面にダイボンド用接着フィルムを全面に貼り付ける工程、(B)該ダイボンド用接着フィルムの所定の部位を除去する工程、(C)該半導体ウエハーを小片化してチップにする工程、を備えてなる特徴とする半導体素子の製造方法、
[3] [2]項に記載の製造方法により得られる半導体素子の機能面の裏面に半導体素子より小さな面積のダイボンド用フィルムを備えてなる半導体素子、
[4] [1]または[3]項に記載の半導体素子の機能面の裏面に半導体素子より小さな面積のダイボンド用フィルムを備えた半導体素子を1つ以上用いて構成された半導体装置。
The present invention also includes the following aspects.
[1] A semiconductor device comprising a die bonding film having an area smaller than that of the semiconductor device on the back surface of the functional surface of the semiconductor device.
[2] (A) a step of attaching an adhesive film for die bonding to the entire back surface of the functional surface of the semiconductor wafer, (B) a step of removing a predetermined portion of the adhesive film for die bonding, and (C) fragmenting the semiconductor wafer. A method of manufacturing a semiconductor device, comprising:
[3] A semiconductor device comprising a die bonding film having a smaller area than the semiconductor device on the back surface of the functional surface of the semiconductor device obtained by the manufacturing method according to [2].
[4] A semiconductor device including at least one semiconductor element including a die bonding film having an area smaller than that of the semiconductor element on the back surface of the functional surface of the semiconductor element according to [1] or [3].

本発明の実施の形態におけるフィルム付き半導体素子の製造方法を示す工程断面図である。It is a process sectional view showing a manufacturing method of a semiconductor device with a film in an embodiment of the invention. フィルム付き半導体素子を示す斜視図である。It is a perspective view which shows the semiconductor element with a film. フィルムが貼り付けられた半導体基板を裏面から見た平面図である。It is the top view which looked at the semiconductor substrate to which the film was stuck from the back. フィルムを除去する工程および半導体基板を切断する工程を示す図である。It is a figure which shows the process of removing a film and the process of cutting a semiconductor substrate. フィルム付き半導体素子を積層して半導体装置の製造方法を示す工程断面図である。It is process sectional drawing which shows the manufacturing method of a semiconductor device by laminating the semiconductor element with a film.

符号の説明Explanation of reference numerals

100 半導体装置
101 半導体基板
102 半導体素子
104 フィルム
106 フィルム付き半導体素子
108 インターポーザー
110 ボンディングワイヤ
112 半田ボール
114 封止材
122 回転砥石
124 ダイシングマシンの歯
Reference Signs List 100 semiconductor device 101 semiconductor substrate 102 semiconductor element 104 film 106 semiconductor element with film 108 interposer 110 bonding wire 112 solder ball 114 sealing material 122 rotating grindstone 124 dicing machine teeth

Claims (8)

半導体素子と、
前記半導体素子の素子形成面の反対面に接着されたフィルムと、
を含み、
前記フィルムは、前記半導体素子と接着する接着面において、前記半導体素子よりも小さく形成されたフィルム付き半導体素子。
A semiconductor element;
A film adhered to the surface opposite to the device forming surface of the semiconductor device,
Including
A semiconductor device with a film, wherein the film is formed to be smaller than the semiconductor element on an adhesion surface to be adhered to the semiconductor element.
配線基板と、
前記配線基板上に素子形成面が上となるように配置された第一の半導体素子と、
前記第一の半導体素子の前記素子形成面に接着されたフィルムと、
を含み、
前記フィルムは、前記第一の半導体素子と接着する接着面において、前記第一の半導体素子よりも小さく形成されたことを特徴とする半導体装置。
A wiring board,
A first semiconductor element disposed on the wiring board such that an element forming surface is on the top,
A film adhered to the element forming surface of the first semiconductor element,
Including
A semiconductor device, wherein the film is formed smaller than the first semiconductor element on an adhesion surface that adheres to the first semiconductor element.
請求項2に記載の半導体装置において、
前記フィルムを介して前記第一の半導体素子と接着された第二の半導体素子をさらに含み、
前記第二の半導体素子の素子形成面の反対面が前記フィルムと接着した半導体装置。
The semiconductor device according to claim 2,
Further comprising a second semiconductor element bonded to the first semiconductor element via the film,
A semiconductor device having a surface opposite to an element forming surface of the second semiconductor element adhered to the film.
半導体素子と、前記半導体素子の素子形成面の反対面に接着され、前記半導体素子と接着する接着面において、前記半導体素子よりも小さく形成されたフィルムと、を含むフィルム付き半導体素子を複数積層した半導体装置。   A plurality of semiconductor elements with a film including a semiconductor element and a film bonded to the opposite surface of the element formation surface of the semiconductor element and bonded to the semiconductor element, and including a film formed smaller than the semiconductor element, were stacked. Semiconductor device. 複数の素子が形成された半導体基板の素子形成面の反対面全面にフィルムを貼り付ける工程と、
前記素子毎の外縁に沿って所定幅で前記フィルムを選択的に除去する工程と、
前記フィルムを選択的に除去する工程と同時または当該工程の後に、前記半導体基板を前記外縁に沿って切断し、前記外縁で囲まれた領域よりも小さく形成されたフィルムが貼り付けられた複数の半導体素子に分割する工程と、
を含むフィルム付き半導体素子の製造方法。
A step of attaching a film to the entire surface opposite to the element forming surface of the semiconductor substrate on which a plurality of elements are formed,
Selectively removing the film at a predetermined width along the outer edge of each element,
Simultaneously with or after the step of selectively removing the film, the semiconductor substrate is cut along the outer edge, and a plurality of films to which a film formed smaller than a region surrounded by the outer edge is attached. Dividing into semiconductor elements;
A method for manufacturing a semiconductor device with a film, comprising:
請求項5に記載のフィルム付き半導体素子の製造方法において、
前記フィルムを選択的に除去する工程において、第一の切断機で前記半導体基板の前記反対面側から前記所定幅の前記フィルムを除去するフィルム付き半導体素子の製造方法。
The method for manufacturing a semiconductor device with a film according to claim 5,
In the step of selectively removing the film, a method for manufacturing a semiconductor device with a film, wherein the film having the predetermined width is removed from the opposite side of the semiconductor substrate by a first cutting machine.
請求項6に記載のフィルム付き半導体素子の製造方法において、
前記半導体素子に分割する工程において、前記第一の切断機よりも幅が狭い第二の切断機で前記半導体基板を切断するフィルム付き半導体素子の製造方法。
The method for manufacturing a semiconductor device with a film according to claim 6,
In the step of dividing into semiconductor elements, a method of manufacturing a semiconductor element with a film, wherein the semiconductor substrate is cut by a second cutting machine narrower than the first cutting machine.
半導体素子と、前記半導体素子の素子形成面の反対面に接着され、前記半導体素子と接着する接着面において、前記半導体素子よりも小さく形成されたフィルムと、を含むフィルム付き半導体素子を複数積層する工程を含むことを特徴とする半導体装置の製造方法。
A plurality of semiconductor elements with a film including a semiconductor element and a film that is bonded to the surface opposite to the element formation surface of the semiconductor element and that is smaller than the semiconductor element on the bonding surface that is bonded to the semiconductor element are stacked. A method for manufacturing a semiconductor device, comprising the steps of:
JP2003421636A 2002-12-27 2003-12-18 Semiconductor element with film, semiconductor device, and method of manufacturing the same Pending JP2004221555A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006253175A (en) * 2005-03-08 2006-09-21 Nec Corp Semiconductor package and manufacturing method thereof
JP2007288003A (en) * 2006-04-18 2007-11-01 Sharp Corp Semiconductor device
JP2008270237A (en) * 2007-04-16 2008-11-06 Nippon Steel Chem Co Ltd Manufacturing method of semiconductor device
JP2009065034A (en) * 2007-09-07 2009-03-26 Renesas Technology Corp Manufacturing method of semiconductor device
JP7655362B2 (en) 2018-09-26 2025-04-02 株式会社レゾナック Semiconductor Device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291061A (en) * 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
JP2000058743A (en) * 1998-07-31 2000-02-25 Sanyo Electric Co Ltd Semiconductor device
JP2001060657A (en) * 1999-08-23 2001-03-06 Matsushita Electronics Industry Corp Semiconductor device and manufacture thereof
JP2001177009A (en) * 1999-12-21 2001-06-29 Hitachi Ltd Semiconductor device and method of manufacturing the same
JP2001308262A (en) * 2000-04-26 2001-11-02 Mitsubishi Electric Corp Resin-sealed BGA type semiconductor device
JP2002093992A (en) * 2000-09-13 2002-03-29 Seiko Epson Corp Semiconductor device and manufacturing method thereof
JP2003204033A (en) * 2002-01-08 2003-07-18 Shinko Electric Ind Co Ltd Method for manufacturing semiconductor device
JP2004140294A (en) * 2002-10-21 2004-05-13 Shinko Electric Ind Co Ltd Spacer forming method, and method of manufacturing semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291061A (en) * 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
JP2000058743A (en) * 1998-07-31 2000-02-25 Sanyo Electric Co Ltd Semiconductor device
JP2001060657A (en) * 1999-08-23 2001-03-06 Matsushita Electronics Industry Corp Semiconductor device and manufacture thereof
JP2001177009A (en) * 1999-12-21 2001-06-29 Hitachi Ltd Semiconductor device and method of manufacturing the same
JP2001308262A (en) * 2000-04-26 2001-11-02 Mitsubishi Electric Corp Resin-sealed BGA type semiconductor device
JP2002093992A (en) * 2000-09-13 2002-03-29 Seiko Epson Corp Semiconductor device and manufacturing method thereof
JP2003204033A (en) * 2002-01-08 2003-07-18 Shinko Electric Ind Co Ltd Method for manufacturing semiconductor device
JP2004140294A (en) * 2002-10-21 2004-05-13 Shinko Electric Ind Co Ltd Spacer forming method, and method of manufacturing semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006253175A (en) * 2005-03-08 2006-09-21 Nec Corp Semiconductor package and manufacturing method thereof
JP2007288003A (en) * 2006-04-18 2007-11-01 Sharp Corp Semiconductor device
JP2008270237A (en) * 2007-04-16 2008-11-06 Nippon Steel Chem Co Ltd Manufacturing method of semiconductor device
JP2009065034A (en) * 2007-09-07 2009-03-26 Renesas Technology Corp Manufacturing method of semiconductor device
JP7655362B2 (en) 2018-09-26 2025-04-02 株式会社レゾナック Semiconductor Device

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