JP2004227517A - Logic synthesis apparatus and logic synthesis method - Google Patents

Abstract

A logic synthesizing apparatus and a logic synthesizing method capable of easily determining whether or not a test point is properly inserted and shortening a design period by making the number of times of logic synthesis one. It is in.
A logic gate circuit generator for generating a plurality of logic gate circuits having equivalent functions based on a register transfer level operation description, and determining whether or not a test point needs to be inserted into each of the logic gate circuits; A test point insertion determination unit 2 that inserts a test point when it is determined that a test point needs to be inserted; an area calculation unit 3 that calculates an area for each logic gate circuit that has been processed by the test point insertion determination unit; And a logic synthesizing unit 4 that selects a logic gate circuit having the smallest value and performs logic synthesis, to constitute a logic synthesis device.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of performing logic synthesis while inserting test points for executing a testability design of a semiconductor integrated circuit.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the development of semiconductor integrated circuit integration technology, a logic LSI having a circuit scale of 2 to 3 million gates has been designed. For this reason, the so-called testability design has become increasingly important. The design for testability refers to a method of establishing a test policy for a semiconductor integrated circuit at the design stage and building a test circuit in the semiconductor integrated circuit.
[0003]
In the design for testability, whether or not the test is easy, that is, whether or not the failure detection rate can be increased can be determined by observability and controllability. Observability means whether it is easy to observe the logical value of a certain node in a circuit from the outside, and controllability means whether it is easy to set the logical value of a certain node by an external input. Say.
[0004]
For this reason, in the design for easy test, in order to enhance the observability and controllability, for example, a technique of finding a location difficult to observe or control and inserting a register called a test point into this location is used.
[0005]
Next, a conventional design for testability will be described with reference to FIG. FIG. 10 is a flowchart showing a conventional logic synthesis method. Insertion of test points is usually performed at the gate level.
[0006]
As shown in FIG. 10, first, logic synthesis is performed based on an RTL (Register Transfer Level) description generated using an HDL (Hardware Description Language), and a netlist is generated (step S41). The RTL description is generated without particularly considering insertion of a test point.
[0007]
Next, a test point is inserted into the netlist generated in step S41, the insertion point is detected, and a test point is inserted (step S42). In this case, since the delay value changes due to the insertion of the test point, it is necessary to optimize the timing. Therefore, after that, the logic is again performed to optimize the logic, and an optimized net list is generated (step S43).
[0008]
As described above, according to the logic synthesis method shown in FIG. 10, a netlist optimized in response to insertion of a test point can be obtained, thereby achieving a testability design. Also, a logic synthesis method is known in which a test point is inserted into an RTL description in order to reduce the design period by performing a single logic synthesis (for example, see Patent Document 1).
[0009]
[Patent Document 1]
JP-A-8-16656
[0010]
[Problems to be solved by the invention]
However, in the above-described conventional logic synthesis method, there is no criterion for judging whether the insertion of a test point is appropriate. For this reason, unnecessary insertion of test points may cause problems such as an increase in chip area, a reduction in processing speed, a delay in test time, and an increase in cost.
[0011]
SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems, to easily determine whether or not test point insertion is appropriate, and to shorten the design period by using only one logic synthesis. It is an object to provide an apparatus and a logic synthesis method.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a first logic synthesis device according to the present invention is a logic synthesis device that generates a netlist based on a register transfer level operation description, and has an equivalent function based on the operation description. A logic gate circuit generating unit for generating a plurality of logic gate circuits, and determining whether a test point needs to be inserted for each of the plurality of logic gate circuits; A test point insertion determination unit for inserting a point, an area calculation unit for calculating an area for each of the plurality of logic gate circuits that have been processed by the test point insertion determination unit, and a logic gate circuit having the smallest area is selected. And a logic synthesis unit that performs logic synthesis by using
[0013]
In order to achieve the above object, a second logic synthesis device according to the present invention is a logic synthesis device that generates a netlist based on a register transfer level operation description, and has an equivalent function based on the operation description. A logic gate circuit generating unit for generating a plurality of logic gate circuits, and determining whether a test point needs to be inserted for each of the plurality of logic gate circuits; A test point insertion determination unit that inserts a point, a circuit speed calculation unit that calculates a circuit speed by performing timing calculation for each of the plurality of logic gate circuits that have been processed by the test point insertion determination unit, It has at least a logic synthesis unit that selects the fastest logic gate circuit and performs logic synthesis. To.
[0014]
To achieve the above object, a third logic synthesizing device according to the present invention is a logic synthesizing device that generates a netlist based on a register transfer level operation description, and has an equivalent function based on the operation description. A logic gate circuit generating unit for generating a plurality of logic gate circuits, and determining whether a test point needs to be inserted for each of the plurality of logic gate circuits; A test point insertion determination unit for inserting a point, a test pattern generation unit for generating a test pattern for each of the plurality of logic gate circuits that have been processed by the test point insertion determination unit, and the number of the generated test patterns At least a logic synthesis unit that selects the logic gate circuit with the least number and performs logic synthesis. Characterized in that it.
[0015]
In order to achieve the above object, a fourth logic synthesis device according to the present invention is a logic synthesis device that generates a netlist based on a register transfer level operation description. A logic gate circuit generating unit for generating a plurality of logic gate circuits, and determining whether a test point needs to be inserted for each of the plurality of logic gate circuits; For each of the plurality of logic gate circuits that have been processed by the test point insertion determination unit that inserts points, and for the plurality of logic gate circuits that have been processed by the test point insertion determination unit, calculate the circuit speed by calculating the timing, and further perform the test. Generating a pattern, based on the area, the circuit speed, and the number of test patterns generated. A cost calculation unit that calculates a cost that changes due to processing by the test point insertion determination unit for each of the logic gate circuits; and a logic synthesis unit that performs logic synthesis by selecting the logic gate circuit with the calculated minimum cost. At least.
[0016]
Next, in order to achieve the above object, a first logic synthesis method according to the present invention is a logic synthesis method for generating a netlist based on an operation description at a register transfer level. Generating a plurality of logic gate circuits having equivalent functions based on the determination of whether the test points need to be inserted into each of the plurality of logic gate circuits, and determining that the test points need to be inserted; (C) calculating an area for each of the plurality of logic gate circuits after the step (b), and (d) a logic gate circuit having the smallest area. And performing logic synthesis by selecting at least one of the following.
[0017]
In order to achieve the above object, a second logic synthesis method according to the present invention is a logic synthesis method for generating a netlist based on an operation description at a register transfer level. Generating a plurality of logic gate circuits having equivalent functions, and (b) determining whether a test point needs to be inserted into each of the plurality of logic gate circuits, and determining that the test point needs to be inserted. (C) calculating a circuit speed by performing a timing calculation for each of the plurality of logic gate circuits after the step (b), and (d) calculating the circuit speed. And a step of selecting the fastest logic gate circuit and performing logic synthesis.
[0018]
In order to achieve the above object, a third logic synthesis method according to the present invention is a logic synthesis method for generating a netlist based on an operation description at a register transfer level. Generating a plurality of logic gate circuits having equivalent functions, and (b) determining whether a test point needs to be inserted into each of the plurality of logic gate circuits, and determining that the test point needs to be inserted. (C) generating a test pattern for each of the plurality of logic gate circuits after the step (b), and (d) generating a test pattern for the test pattern. And selecting a logic gate circuit having the least number to perform logic synthesis.
[0019]
In order to achieve the above object, a fourth logic synthesis method according to the present invention is a logic synthesis method for generating a netlist based on an operation description at a register transfer level. Generating a plurality of logic gate circuits having equivalent functions, and (b) determining whether a test point needs to be inserted into each of the plurality of logic gate circuits, and determining that the test point needs to be inserted. In the case, the step of inserting the test point and (c) calculating the area and calculating the circuit speed for each of the plurality of logic gate circuits after the step (b) are completed, and further performing the test. Generating a pattern; and (f) performing the step (b) based on the area, the circuit speed, and the number of the generated test patterns. Calculating a cost for each of the logic gate circuit for changing I, and having at least a step of performing logic synthesis by selecting the smallest logic gate circuit is the cost calculated (g).
[0020]
Note that the present invention may be a program for realizing the above-described logic synthesis method according to the present invention. By installing and executing this program on a computer, the above-described logic synthesis method according to the present invention can be executed.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
Hereinafter, a logic synthesis device and a logic synthesis method according to the first embodiment of the present invention will be described with reference to FIGS. First, the configuration of the logic synthesis apparatus according to the first embodiment will be described with reference to FIGS. FIG. 1 is a diagram schematically illustrating a configuration of a logic synthesis device according to a first embodiment of the present invention. FIG. 2 is a diagram showing a logic gate circuit generated from the operation description at the register transfer level. Note that the logic gate circuits shown in FIGS. 2A and 2B are circuits based on the same operation description and have equivalent functions.
[0022]
As shown in FIG. 1, the logic synthesis device according to the first embodiment includes a logic gate circuit generation unit 1, a test point insertion determination unit 2, an area calculation unit 3, and a logic synthesis unit 4. With this configuration, the netlist 6 is generated based on the operation description (RTL description) 5 at the register transfer level.
[0023]
The logic gate circuit generation unit 1 generates a plurality of logic gate circuits having equivalent functions based on the RTL description 5, as shown in FIGS. 2A and 2B. The generated logic gate circuits are candidates for selection when the logic synthesis unit 4 performs logic synthesis.
[0024]
The test point insertion determination unit 2 determines whether a test point needs to be inserted for each of the plurality of logic gate circuits generated by the logic gate circuit generation unit 1. Insert a point. The test point insertion determination unit 2 determines whether to insert a test point based on the calculation results of observability and controllability.
[0025]
In the examples of FIGS. 1 and 2, the test point insertion determination unit 2 determines that the test point insertion is not required for the logic gate circuit shown in FIG. On the other hand, the test point insertion determination unit 2 determines that the test point needs to be inserted for the logic gate circuit shown in FIG. 2B, and inserts the test point.
[0026]
After the processing by the test point insertion determination unit 2 ends, the area calculation unit 3 calculates the area for each logic gate circuit generated by the logic gate circuit generation unit 1. For example, since no test point is inserted into the logic gate circuit shown in FIG. 2A, the area without the test point inserted is calculated. On the other hand, since the test point is inserted in the logic gate circuit shown in FIG. 2B, the area with the test point inserted is calculated.
[0027]
The logic synthesis unit 4 selects a logic gate circuit having the smallest area calculated by the area calculation unit 3 from a plurality of logic gate circuits having equivalent functions, and performs logic synthesis using the selected logic gate circuit. , And outputs the netlist 6.
[0028]
Next, a logic synthesis method according to the first embodiment will be described with reference to FIG. However, the logic synthesis method according to the first embodiment is performed by operating the logic synthesis device according to the first embodiment illustrated in FIG. Therefore, the logic synthesis method according to the first embodiment will be described together with the operation of the logic synthesis device shown in FIG. 1 while appropriately referring to FIG. FIG. 3 is a flowchart illustrating an operation of the logic synthesis apparatus according to the first exemplary embodiment of the present invention.
[0029]
As shown in FIG. 3, first, the RTL description 5 is read by the logic gate circuit generation unit 1, and a plurality of logic gate circuits having equivalent functions (see FIG. 2) are generated based on the RTL description 5 (step S1).
[0030]
Next, the test point insertion determination unit 2 determines whether or not a test point needs to be inserted for each of the logic gate circuits generated in step S1. On the other hand, a test point is inserted (step S2).
[0031]
Next, the area calculation unit 3 calculates the area of each logic gate circuit for which step S2 has been completed (step S3), and then compares the area calculated in step S3 with the logic synthesis unit 4 to determine the equivalent function. A logic gate circuit having the smallest area is selected from a plurality of logic gate circuits (step S4).
[0032]
Thereafter, the logic synthesis unit 4 performs logic synthesis using the logic gate circuit selected in step S4, and outputs a netlist 6 (step S5). Although not shown in FIG. 3, when there are a plurality of functions represented in the RTL description 5, steps S1 to S4 are executed for all the functions, and then step S5 is executed.
[0033]
As described above, according to the logic synthesis device and the logic synthesis method according to the first embodiment, a plurality of logic gate circuits are generated as candidates for logic synthesis for the function expressed in the operation description, and each logic gate is generated. After the test points are inserted into the circuit as necessary, the one with the smallest area is selected and the logic synthesis is performed. Therefore, according to the logic synthesizing apparatus and the logic synthesizing method according to the first embodiment, it is possible to easily insert an appropriate test point, and to finish the logic synthesis at one time. Further, according to the first embodiment, the insertion of test points can be minimized, so that an increase in chip area can be suppressed.
[0034]
Note that the logic synthesis apparatus according to the first embodiment can also be realized by installing a program that embodies steps S1 to S5 shown in FIG. 3 in a computer and executing the program. In this case, a CPU (central processing unit) of the computer functions as the logic gate circuit generation unit 1, the test point insertion determination unit 2, the area calculation unit 3, and the logic synthesis unit 4 to perform processing.
[0035]
The RTL description 5 is stored in a storage device such as a hard disk provided in a computer constituting the logic synthesis device, by storing a data file constituting the data file, or by connecting a recording medium storing the data file to the computer. It is provided by mounting on a reading device. Further, the RTL description 5 may be stored in a computer different from the computer constituting the logic synthesis apparatus, and in this case, is provided via a communication line.
[0036]
The destination to which the logic synthesis unit 4 outputs the netlist 6 may be a storage device such as a hard disk provided in a computer constituting the logic synthesis device, or a computer constituting the logic synthesis device. May be a storage device of another computer connected to the computer.
[0037]
(Embodiment 2)
Next, a logic synthesis device and a logic synthesis method according to a second embodiment of the present invention will be described with reference to FIGS. First, the configuration of the logic synthesis apparatus according to the second embodiment will be described with reference to FIG. FIG. 4 is a diagram schematically illustrating a configuration of a logic synthesis device according to a second embodiment of the present invention.
[0038]
As shown in FIG. 4, the logic synthesis device according to the second embodiment includes a circuit speed calculation unit 13 and is different from the logic synthesis device according to the first embodiment in this point. After the processing by the test point insertion determination unit 12 is completed, the circuit speed calculation unit 13 calculates the timing for each of the plurality of logic gate circuits, and calculates the circuit speed of each logic gate circuit. Note that the “circuit speed” in the present invention means a delay time of signal propagation in a logic gate circuit.
[0039]
Therefore, unlike the first embodiment, the logic synthesizing unit 14 is a logic gate circuit having the fastest circuit speed calculated by the circuit speed calculating unit 13 among a plurality of logic gate circuits having equivalent functions, that is, a delay circuit. Select the logic gate circuit with the shortest time.
[0040]
Also in the second embodiment, the logic synthesis unit 14 performs logic synthesis using the selected logic gate circuit, and outputs a netlist 16. The logic gate circuit generator 11 and the test point insertion determiner 12 are the same as those described in the first embodiment.
[0041]
Next, a logic synthesis method according to the second embodiment will be described with reference to FIG. The logic synthesis method according to the second embodiment is also implemented by operating a logic synthesis device, as in the first embodiment. Therefore, the logic synthesis method according to the second embodiment will be described together with the operation of the logic synthesis device shown in FIG. FIG. 5 is a flowchart illustrating the operation of the logic synthesis apparatus according to the second embodiment of the present invention.
[0042]
As shown in FIG. 5, first, a plurality of logic gate circuits having equivalent functions are generated by the logic gate circuit generation unit 11 (step S11), and whether the test point insertion is necessary or not is determined by the test point insertion determination unit 12. Is determined and a test point is inserted (step S12). Steps S11 and S12 are the same steps as steps S1 and S2 shown in FIG.
[0043]
Next, the circuit speed calculation unit 13 calculates the timing of each logic gate circuit for which step S12 has been completed, and calculates the circuit speed of each logic gate circuit (step S13). Next, the logic synthesizer 14 compares the circuit speeds calculated in step S13, and selects a logic gate circuit having the highest circuit speed from a plurality of logic gate circuits having equivalent functions (step S14).
[0044]
Thereafter, the logic synthesis unit 14 performs logic synthesis using the logic gate circuit selected in step S14, and outputs a netlist 16 (step S15). Step S15 is the same step as S5 shown in FIG. Although not shown in FIG. 5, when there are a plurality of functions represented in the RTL description 15, steps S11 to S14 are performed for all the functions, and then step S15 is performed.
[0045]
As described above, according to the logic synthesis device and the logic synthesis method according to the second embodiment, the logic gate circuit having the highest circuit speed is selected from the plurality of logic gate circuits having the equivalent function, and the logic synthesis is performed. Done. Therefore, also in the second embodiment, as in the first embodiment, appropriate test points can be easily inserted, and logic synthesis can be completed at once. Further, according to the second embodiment, it is possible to minimize the speed delay due to the insertion of the test points.
[0046]
The logic synthesizing apparatus according to the second embodiment can also be realized by installing a program for realizing steps S11 to S15 shown in FIG. 5 in a computer and executing the program.
[0047]
(Embodiment 3)
Next, a logic synthesis device and a logic synthesis method according to a third embodiment of the present invention will be described with reference to FIGS. First, the configuration of the logic synthesis apparatus according to the third embodiment will be described with reference to FIG. FIG. 6 is a diagram schematically illustrating a configuration of a logic synthesis device according to a third embodiment of the present invention.
[0048]
As shown in FIG. 6, the logic synthesis device according to the third embodiment includes a test pattern generation unit 23, and differs from the logic synthesis device according to the first embodiment in this point. After the processing by the test point insertion determination unit 22 ends, the test pattern generation unit 23 generates a test pattern for each of the plurality of logic gate circuits.
[0049]
Further, unlike the first embodiment, the logic synthesis unit 24 selects a logic gate circuit having the smallest number of test patterns generated by the test pattern generation unit 23 from a plurality of logic gates having equivalent functions.
[0050]
Also in the third embodiment, the logic synthesis unit 24 performs logic synthesis using the selected logic gate circuit, and outputs a netlist 26. The logic gate circuit generator 21 and the test point insertion determiner 22 are the same as those described in the first embodiment.
[0051]
Next, a logic synthesis method according to the third embodiment will be described with reference to FIG. The logic synthesis method according to the third embodiment is also implemented by operating the logic synthesis device, as in the first embodiment. Therefore, the logic synthesis method according to the third embodiment will be described together with the operation of the logic synthesis apparatus shown in FIG. FIG. 7 is a flowchart illustrating the operation of the logic synthesis apparatus according to the third embodiment of the present invention.
[0052]
As shown in FIG. 7, first, a plurality of logic gate circuits having equivalent functions are generated by the logic gate circuit generation unit 21 (step S21), and whether the test point insertion is necessary is determined by the test point insertion determination unit 22. Is determined and a test point is inserted (step S22). Steps S21 and S22 are the same steps as steps S1 and S2 shown in FIG.
[0053]
Next, the test pattern generation unit 23 generates a test pattern for each logic gate circuit for which the step S22 has been completed (step S23). Next, the number of test patterns generated in step S23 is compared by the logic synthesis unit 24, and a logic gate circuit having the smallest number of test patterns is selected from a plurality of logic gate circuits having equivalent functions (step S24). .
[0054]
Thereafter, the logic synthesis unit 24 performs logic synthesis using the logic gate circuit selected in step S24, and outputs a netlist 26 (step S25). Step S25 is the same step as S5 shown in FIG. Although not shown in FIG. 7, when there are a plurality of functions represented in the RTL description 25, steps S21 to S24 are executed for all the functions, and then step S25 is executed.
[0055]
As described above, according to the logic synthesis device and the logic synthesis method according to the third embodiment, the logic gate circuit having the smallest number of test patterns is selected from the plurality of logic gate circuits having the equivalent function, and Synthesis is performed. Therefore, also in the third embodiment, as in the first embodiment, appropriate test points can be easily inserted, and logic synthesis can be completed at one time. Further, according to the third embodiment, the time required for the test can be reduced, and the development period of the semiconductor integrated circuit can be shortened.
[0056]
The logic synthesizing apparatus according to the third embodiment can also be realized by installing a program for implementing steps S21 to S25 shown in FIG. 7 in a computer and executing this program.
[0057]
(Embodiment 4)
Next, a logic synthesis device and a logic synthesis method according to a fourth embodiment of the present invention will be described with reference to FIGS. First, the configuration of the logic synthesis apparatus according to the fourth embodiment will be described with reference to FIG. FIG. 8 is a diagram schematically illustrating a configuration of a logic synthesis device according to a fourth embodiment of the present invention.
[0058]
As shown in FIG. 8, the logic synthesis device according to the fourth embodiment includes a cost calculation unit 33, and is different from the logic synthesis device according to the first embodiment in this point. After the processing by the test point insertion determination unit 32 ends, the cost calculation unit 33 calculates the area and circuit speed and generates a test pattern for each of the plurality of logic gate circuits. That is, the cost calculator 33 has the same functions as the area calculator (see FIG. 1), the circuit speed calculator (see FIG. 4), and the test pattern generator (see FIG. 6).
[0059]
Further, the cost calculation unit 33 calculates, for each logic gate circuit, a cost that changes by the process performed by the test point insertion determination unit 23 based on the calculated area and circuit speed and the number of generated test patterns. In the fourth embodiment, the cost calculation unit 33 calculates an increase in cost and a decrease in chip price caused by insertion of a test point using an evaluation function, and uses the sum of these as a change in cost to calculate the cost. calculate.
[0060]
Specifically, the cost calculation unit 33 calculates and calculates the manufacturing cost per unit area of the semiconductor integrated device by using an evaluation function indicating the relationship between the area of the logic gate circuit and the manufacturing cost of the semiconductor integrated circuit. By calculating the product of the manufacturing cost and the area increase due to the insertion of the test point, the cost increase due to the area increase is calculated. Further, the cost calculation unit 33 converts the amount of reduction in circuit speed due to insertion of test points into the amount of reduction in chip price using an evaluation function indicating the relationship between circuit speed and chip price, Calculate the price decrease. Further, the cost calculation unit 33 calculates an increase in the test cost due to the increase in the number of test patterns, using an evaluation function indicating the relationship between the number of test patterns and the test cost.
[0061]
Note that, as in the logic gate circuit shown in FIG. 2A, for a logic gate circuit for which it is determined that it is not necessary to insert a test point, no test point is inserted. Since it is considered that no reduction occurs, the change in cost is 0 (zero). Therefore, for a logic gate circuit that is determined not to require insertion of a test point, calculation of the area and circuit speed and generation of a test pattern are not performed, and the change in cost is set to 0 (zero). good.
[0062]
Further, unlike the first embodiment, the logic synthesis unit 34 selects a logic gate circuit having the smallest cost calculated by the cost calculation unit 33 from a plurality of logic gates having equivalent functions.
[0063]
Also in the fourth embodiment, the logic synthesis unit 34 performs logic synthesis using the selected logic gate circuit, and outputs a netlist 36. The logic gate circuit generator 31 and the test point insertion determiner 32 are the same as those described in the first embodiment.
[0064]
Next, a logic synthesis method according to the fourth embodiment will be described with reference to FIG. The logic synthesis method according to the fourth embodiment is also implemented by operating a logic synthesis device, as in the first embodiment. Therefore, the logic synthesis method according to the fourth embodiment will be described together with the operation of the logic synthesis apparatus shown in FIG. FIG. 9 is a flowchart illustrating the operation of the logic synthesis apparatus according to the fourth embodiment of the present invention.
[0065]
As shown in FIG. 9, first, a plurality of logic gate circuits having equivalent functions are generated by the logic gate circuit generation unit 31 (step S31), and whether the test point insertion is necessary is determined by the test point insertion determination unit 32 or not. Is determined and a test point is inserted (step S32). Steps S31 and S32 are the same steps as steps S1 and S2 shown in FIG.
[0066]
Next, the cost calculation unit 33 calculates the area of each logic gate circuit for which step S32 has been completed, calculates the circuit speed by performing timing calculation, and further generates a test pattern (step S33). Next, cost is calculated using the area and circuit speed calculated in step S33 and the number of test patterns generated in step S33 (step S34).
[0067]
Next, the logic synthesis unit 34 compares the costs calculated in step S34, and selects a logic gate circuit having the lowest cost from a plurality of logic gate circuits having equivalent functions (step S35).
[0068]
Thereafter, the logic synthesis unit 34 performs logic synthesis using the logic gate circuit selected in step S35, and outputs a netlist 36 (step S36). Step S36 is the same step as S5 shown in FIG. Although not shown in FIG. 9, when there are a plurality of functions represented in the RTL description 35, steps S <b> 31 to S <b> 35 are performed for all the functions, and then step S <b> 36 is performed.
[0069]
As described above, according to the logic synthesis device and the logic synthesis method according to the fourth embodiment, the logic gate circuit with the smallest loss due to test point insertion is selected from the plurality of logic gate circuits having the equivalent functions. Logic synthesis is performed. Therefore, also in the fourth embodiment, as in the first embodiment, appropriate test points can be easily inserted, and logic synthesis can be completed at once. Further, according to the fourth embodiment, the development cost of the semiconductor integrated circuit can be reduced.
[0070]
The logic synthesizing apparatus according to the second embodiment can also be realized by installing a program for implementing steps S31 to S35 shown in FIG. 9 in a computer and executing this program.
[0071]
【The invention's effect】
As described above, according to the logic synthesis apparatus and the logic synthesis method according to the present invention, it is determined whether or not the inserted test point is appropriate. Therefore, it is possible to easily insert an appropriate test point. Can be. Therefore, unnecessary test points can be prevented from being inserted, and the insertion of the test points causes, for example, an increase in chip area overhead, generation of slack due to a decrease in circuit speed, and development due to an increase in the number of test patterns. It is possible to suppress a prolonged period, an increase in cost and a decrease in chip price.
[Brief description of the drawings]
FIG. 1 is a diagram schematically illustrating a configuration of a logic synthesis device according to a first embodiment of the present invention;
FIG. 2 is a diagram showing a logic gate circuit generated from an operation description at a register transfer level.
FIG. 3 is a flowchart illustrating an operation of the logic synthesis device according to the first exemplary embodiment of the present invention;
FIG. 4 is a diagram schematically illustrating a configuration of a logic synthesis device according to a second embodiment of the present invention;
FIG. 5 is a flowchart illustrating an operation of the logic synthesis apparatus according to the second exemplary embodiment of the present invention;
FIG. 6 is a diagram schematically illustrating a configuration of a logic synthesis device according to a third embodiment of the present invention;
FIG. 7 is a flowchart illustrating an operation of the logic synthesis apparatus according to the third exemplary embodiment of the present invention;
FIG. 8 is a diagram schematically showing a configuration of a logic synthesis device according to a fourth exemplary embodiment of the present invention.
FIG. 9 is a flowchart illustrating an operation of the logic synthesis apparatus according to the fourth exemplary embodiment of the present invention;
FIG. 10 is a flowchart showing a conventional logic synthesis method.
[Explanation of symbols]
1, 11, 21, 31 logic gate circuit generator
2, 12, 22, 32 Test focus insertion determination unit
3 area calculator
4, 14, 24, 34 logic synthesis unit
5, 15, 25, 35 RTL description
6, 16, 26, 36 Netlist
13 Circuit speed calculation unit
23 Test pattern generator
33 Cost calculator

Claims (12)

A logic synthesizer for generating a netlist based on a register transfer level operation description,
A logic gate circuit generation unit that generates a plurality of logic gate circuits having equivalent functions based on the operation description, and determines whether a test point needs to be inserted into each of the plurality of logic gate circuits; A test point insertion determination unit that inserts the test point when it is determined that insertion is necessary, an area calculation unit that calculates an area for each of the plurality of logic gate circuits that have been processed by the test point insertion determination unit, A logic synthesis device comprising at least a logic synthesis unit that selects a logic gate circuit having the smallest area and performs logic synthesis. A logic synthesizer for generating a netlist based on a register transfer level operation description,
A logic gate circuit generation unit that generates a plurality of logic gate circuits having equivalent functions based on the operation description, and determines whether a test point needs to be inserted into each of the plurality of logic gate circuits; A test point insertion determining unit that inserts the test point when it is determined that insertion is necessary, and a timing calculation is performed for each of the plurality of logic gate circuits that have been processed by the test point insertion determining unit to calculate a circuit speed. A logic synthesizing device comprising at least a circuit speed calculating unit and a logic synthesizing unit for selecting a logic gate circuit having the highest circuit speed and performing logic synthesis. A logic synthesizer for generating a netlist based on a register transfer level operation description,
A logic gate circuit generation unit that generates a plurality of logic gate circuits having equivalent functions based on the operation description; and determines whether a test point needs to be inserted into each of the plurality of logic gate circuits. A test point insertion determining unit that inserts the test point when it is determined that insertion is necessary; and a test pattern generating unit that generates a test pattern for each of the plurality of logic gate circuits that have been processed by the test point insertion determining unit. And a logic synthesis unit for selecting a logic gate circuit with the least number of the generated test patterns and performing logic synthesis. A logic synthesizer for generating a netlist based on a register transfer level operation description,
A logic gate circuit generation unit that generates a plurality of logic gate circuits having equivalent functions based on the operation description; and determines whether a test point needs to be inserted into each of the plurality of logic gate circuits. A test point insertion determination unit that inserts the test point when it is determined that insertion is necessary, and an area is calculated for each of the plurality of logic gate circuits that have been processed by the test point insertion determination unit, and the timing calculation is performed. To calculate a circuit speed, further generate a test pattern, and based on the area, the circuit speed, and the number of the generated test patterns, change the cost that is changed by the processing by the test point insertion determination unit. A cost calculator for calculating each logic gate circuit; and a logic circuit having the smallest calculated cost. Logic synthesis apparatus characterized by having at least a logical combining unit for performing a logic synthesis Select and circuits. A logic synthesis method for generating a netlist based on a register transfer level operation description,
(A) generating a plurality of logic gate circuits having equivalent functions based on the operation description;
(B) determining whether a test point needs to be inserted for each of the plurality of logic gate circuits, and inserting the test point when determining that the test point needs to be inserted;
(C) calculating an area for each of the plurality of logic gate circuits after the step (b) has been completed;
(D) selecting a logic gate circuit having the smallest area and performing logic synthesis. A logic synthesis method for generating a netlist based on a register transfer level operation description,
(A) generating a plurality of logic gate circuits having equivalent functions based on the operation description;
(B) determining whether a test point needs to be inserted for each of the plurality of logic gate circuits, and inserting the test point when determining that the test point needs to be inserted;
(C) calculating a circuit speed by performing timing calculation for each of the plurality of logic gate circuits for which the step (b) has been completed;
(D) selecting the logic gate circuit having the fastest circuit speed and performing logic synthesis. A logic synthesis method for generating a netlist based on a register transfer level operation description,
(A) generating a plurality of logic gate circuits having equivalent functions based on the operation description;
(B) determining whether a test point needs to be inserted for each of the plurality of logic gate circuits, and inserting the test point when determining that the test point needs to be inserted;
(C) generating a test pattern for each of the plurality of logic gate circuits after the step (b) has been completed;
(D) selecting a logic gate circuit having the least number of the generated test patterns to perform logic synthesis. A logic synthesis method for generating a netlist based on a register transfer level operation description,
(A) generating a plurality of logic gate circuits having equivalent functions based on the operation description;
(B) determining whether a test point needs to be inserted for each of the plurality of logic gate circuits, and inserting the test point when determining that the test point needs to be inserted;
(C) calculating an area for each of the plurality of logic gate circuits after the step (b), calculating a circuit speed by performing a timing calculation, and further generating a test pattern;
(F) calculating, for each of the logic gate circuits, a cost that changes in the step (b) based on the area, the circuit speed, and the number of the generated test patterns;
(G) selecting a logic gate circuit having the lowest calculated cost and performing logic synthesis. A program for performing logic synthesis based on a register transfer level operation description by a computer,
(A) generating a plurality of logic gate circuits having equivalent functions based on the operation description;
(B) determining whether a test point needs to be inserted into each of the plurality of logic gate circuits, and inserting the test point when determining that the test point needs to be inserted;
(C) calculating an area for each of the plurality of logic gate circuits after the step (b) has been completed;
(D) selecting a logic gate circuit having the smallest area and performing logic synthesis. A program for performing logic synthesis based on a register transfer level operation description by a computer,
(A) generating a plurality of logic gate circuits having equivalent functions based on the operation description;
(B) determining whether a test point needs to be inserted into each of the plurality of logic gate circuits, and inserting the test point when determining that the test point needs to be inserted;
(C) calculating a circuit speed by performing timing calculation for each of the plurality of logic gate circuits for which the step (b) has been completed;
(D) selecting a logic gate circuit having the fastest circuit speed and performing logic synthesis. A program for performing logic synthesis based on a register transfer level operation description by a computer,
(A) generating a plurality of logic gate circuits having equivalent functions based on the operation description;
(B) determining whether a test point needs to be inserted into each of the plurality of logic gate circuits, and inserting the test point when determining that the test point needs to be inserted;
(C) generating a test pattern for each of the plurality of logic gate circuits for which the step (b) has been completed;
(D) selecting a logic gate circuit having the least number of the generated test patterns to perform logic synthesis. A program for performing logic synthesis based on a register transfer level operation description by a computer,
(A) generating a plurality of logic gate circuits having equivalent functions based on the operation description;
(B) determining whether a test point needs to be inserted into each of the plurality of logic gate circuits, and inserting the test point when determining that the test point needs to be inserted;
(C) for each of the plurality of logic gate circuits for which the step (b) has been completed, calculating an area, calculating a circuit speed by performing a timing calculation, and further generating a test pattern;
(F) calculating, for each of the plurality of logic gate circuits, a cost that changes in the step (b) based on the area, the circuit speed, and the number of the generated test patterns;
(G) selecting a logic gate circuit having the lowest calculated cost and performing logic synthesis.

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