JP2004227686A - Semiconductor memory device and data writing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of reducing the number of disturbance occurrences as a worse case, and a data writing method. <P>SOLUTION: A pair of a pulse (WP) of a write level potential and a pulse (NP) of the opposite level potential is applied as voltages in directions different from each other to a nonselected cell (ferroelectric capacitor). Namely, even if a disturbance voltage in a destructive direction is applied, a pair of voltages in the opposite direction (restoration direction) is applied just after the disturbance voltage to prevent the disturbance voltage from being continuously applied repeatedly. In addition, the pulse (NP) of the opposite level potential is applied only when write data are equal to write data to a ferroelectric capacitor accessed just before in a selected memory unit to thereby prevent the pulse of the opposite level potential from acting as a disturbance voltage. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device including a ferroelectric memory and a data writing method.
[0002]
[Prior art]
In a semiconductor memory device, in particular, an FeRAM using a ferroelectric is attracting attention as an easy-to-use device having both high-speed access and nonvolatile storage, and is expected to have a large capacity.
FeRAM is small in size, has low power consumption, and is resistant to impact. If the unit cost per bit is reduced due to the increase in capacity, it is promising as a recording medium for voice and images.
In particular, a technique for improving the degree of integration is described in the following document.
[0003]
[Patent Document 1] JP-A-2000-349248
[Patent Document 2] JP-A-9-121032
[0004]
These documents disclose an FeRAM having a cross-point type cell structure. FIG. 15 shows a circuit example of the FeRAM having the cross-point type cell structure.
In FIG. 15, for example, memory units MU1 and MU2 each having four ferroelectric capacitors, a word line WL1 arranged in a row direction, a pair of bit lines BL1 and BL2 arranged in a column direction, arranged in a row direction. Although the plate lines PL1 to PL4 are shown, these are shown only as a part of the formed memory cell array for simplification of the drawing.
Actually, as is known, a plurality of pairs of word lines WL in the row direction and a plurality of bit lines BL in the column direction are arranged, and a plurality of memory units MU are provided in each direction of the word line and the bit line pair. They are arranged in an array.
[0005]
A voltage is applied to the word line WL1 and each word line (not shown) by the word line decoder / driver 1 according to the address to be accessed.
A voltage is applied to the bit line pair by the bit lines BL1 and BL2 by the sense amplifier 3, and the potential is detected. Sense amplifiers are also provided for other bit line pairs not shown.
[0006]
The memory unit MU1 includes a plurality of capacitors C11 to C14 each connected to the common node electrode 11.
Further, the memory unit MU2 includes a plurality of capacitors C21 to C24 each connected to the common node electrode 12.
In the description, it is assumed that each of the memory units MU1 and MU2 is provided with four ferroelectric capacitors (C11 to C14 and C21 to C24). However, usually, one memory unit MU has a larger number. Are often provided.
[0007]
The memory units MU1 and MU2 are connected from the common node electrodes 11 and 12, respectively, to the bit lines BL1 and BL2 via access transistors T1 and T2 formed by FETs controlled by the word line WL1. The access transistors T1 and T2 have their gate electrodes connected to the word line WL1.
[0008]
Each capacitor C in one memory unit MU stores separate data, and is controlled by independent plate lines PL1 to PL4.
That is, in the memory unit MU1, one end of each of the capacitors C11 to C14 is connected to the common node electrode 11 as described above, and the other end is connected to the plate lines PL1 to PL4, respectively.
In the memory unit MU2, one end of each of the capacitors C21 to C24 is connected to the common node electrode 12 as described above, and the other end is connected to each of the plate lines PL1 to PL4.
A predetermined voltage is applied to each of the plate lines PL1 to PL4 by the plate line decoder / driver 2.
[0009]
In such a cross-point type FeRAM, one bit is complementarily stored using two ferroelectric capacitors. That is, as dielectric capacitors constituting the memory units MU1 and MU2 connected to the pair of bit lines BL1 and BL2, the capacitors C11 and C21, C12 and C22, C13 and C23, and C14 and C24 form a pair, respectively. Data of one bit is stored complementarily depending on the direction.
For example, when writing “1” to the capacitor C11, the word line WL1 is selected, the plate line PL1 is set to 0 V, the plate lines PL1 to PL4 are set to the intermediate potential, and the bit lines BL1 and BL2 are driven to set “1” to the capacitor C11. Is applied. On the other hand, the direction of polarization of the capacitor C21 is set to “0”. In reading, when the word line WL1 is selected and the plate line PL3 is driven with the plate lines PL2 to PL4 fixed at 0 V, charges are released from the capacitors C11 and C21 to the bit line pair BL1 and BL2. . Data can be read by detecting the potential difference generated by the differential sense amplifier 3.
[0010]
In such a cross-point type cell, a plurality of capacitors (a plurality of capacitors constituting the memory unit MU) share one transistor (T1, T2...) Connected to the word line WL. Therefore, the number of elements per bit is effectively reduced, which is effective for cost reduction.
[0011]
Further, as a configuration of a cross-point type FeRAM suitable for further miniaturization, a configuration as shown in FIG. 16 has been proposed. The same parts as those in FIG. 15 are denoted by the same reference numerals.
Also in this case, the memory units MU1 and MU2 are each composed of a plurality of ferroelectric capacitors (C11 to C14, C21 to C24) connected to the common node electrodes 11 and 12, respectively. Data is stored and controlled by independent plate lines PL1 to PL4.
[0012]
In the case of FIG. 16, a word line WL1w for writing and a word line WL1r for reading are provided as word lines WL corresponding to the rows of the memory units MU1 and MU2.
[0013]
The common node electrode 11 of the memory unit MU1 is connected to the bit line BL1 via a write access transistor (FET) T13.
The common node electrode 12 of the memory unit MU2 is connected to the bit line BL2 via a write access transistor (FET) T23.
The gates of the write access transistors T13 and T23 are connected to a write word line WL1w.
At the time of writing to the capacitor C in the memory units MU1 and MU2, the word line WL1w is driven so that the voltages of the bit lines BL1 and BL2 are applied to the common node electrodes 11 and 12.
[0014]
As a configuration for reading data, read access transistors (FETs) T12 and T22 and sense transistors T11 and T21 are further provided.
The gates of the read access transistors T12 and T22 are connected to a read word line WL1r.
The sense transistors T11 and T21 are, for example, depletion type NMOSs. The gates of the sense transistors T11 and T21 are connected to the common node electrodes 11 and 12, respectively. The sense transistors T11 and T21 are connected to the bit lines BL1 and BL2 via read access transistors T12 and T22, respectively.
[0015]
For example, when reading data from the capacitors C11 and C21, the read word line WL1r is selected, and the plate line PL1 is driven with the plate lines PL2 to PL4 fixed at 0V. As a result, electric charges are released from the capacitors C11 and C21 to the common node electrodes 11 and 12. At this time, the write word line WL1w is closed, and the common node electrodes 11 and 12 are disconnected from the bit lines BL1 and BL2. ing. The two common node electrodes 11, 12 do not directly drive the bit lines BL1, BL2, but drive only the gate electrodes of the sense transistors T11, T21.
The sense transistors T11 and T21 drive the bit lines BL1 and BL2 according to the voltage applied to the gates.
[0016]
In the configuration example shown in FIG. 16, the selected capacitor does not need to directly drive the bit line BL at the time of data reading. Therefore, a large signal can be obtained even with a small capacitor, which is suitable for miniaturization.
[0017]
[Problems to be solved by the invention]
The cross-point type ferroelectric memory described above has an improved degree of integration by storing independent data in a plurality of ferroelectric capacitors connected to the same electrode.
However, with this structure, when a voltage is applied to write to a certain selected capacitor in the memory unit MU, a voltage is applied to a non-selected capacitor in the same memory unit MU. In this case, data inversion can be prevented by setting a non-selected plate line connected to the non-selected capacitor to an intermediate potential. However, this voltage application is called disturb and causes data deterioration.
[0018]
For example, in the configuration of FIG. 15, the state of voltage application to each electrode when data “1” is written is illustrated in FIG.
FIG. 18 shows an example in which data “1” is written using the capacitor C11 on the bit line BL1 as a selection capacitor.
In this case, as shown, a voltage Vcc is applied to the bit line BL1, and 0 V is applied to the plate line PL1 serving as a selected plate line.
On the other hand, (1/3) Vcc is applied to the bit line BL2 on the data "0" side, and (2/3) Vcc is applied to the plate line PL2 (and PL3, PL4 not shown) serving as the unselected plate line. Thus, the inversion of the non-selected capacitor is prevented.
[0019]
In this case, the voltage Vcc is applied to the selection capacitor C11 as a potential difference between the bit line BL1 and the plate line PL1, whereby the capacitor C11 has a polarization direction corresponding to data "1".
On the other hand, (１ ／) Vcc is applied to the unselected capacitors C12 and C21, and (− ／) Vcc is applied to the unselected capacitor C22.
The application of the disturb voltage to the non-selected capacitor does not immediately cause data inversion, but if the applied voltage is a voltage in the opposite direction of the stored data, the value is degraded little by little.
[0020]
FIG. 17 shows an example of a timing operation when writing data “1”.
It is assumed that data "0" has been written in advance to the capacitors C11 and C21 on the selection plate line PL1, data "1" has been written to the capacitor C11 on the bit line BL1, and data of the capacitor C21 on the bit line BL2. “0” is a case to be stored.
One cycle of the write operation is indicated by a period of w1 to w7.
[0021]
Period w1: Open the word line WL1 corresponding to the selected memory units MU1, MU2, and connect the memory units MU1, MU2 to the bit lines BL1, BL2.
Period w2: A potential of (１ ／) Vcc is applied to each bit line BL1, BL2.
Period w3: The potentials of the unselected plate lines PL2 to PL4 are raised to (2/3) Vcc. On the other hand, the potential of the selection plate line PL1 is kept at 0V.
Period w4: Here, a write pulse WP of voltage Vcc is applied to the bit line BL1 for writing data “1”. Thereby, as shown in FIG. 18, the voltage Vcc is applied only to the selected capacitor C11 to which the data "1" is written, and the writing is executed. At the same time, a disturb voltage of (１ ／) Vcc is applied to the unselected capacitors according to the stored data.
Period w5: The bit line BL1 is returned to (１ ／) Vcc.
Period w6: Return non-selected plate lines PL2 to PL4 to 0V.
Period w7: The bit lines BL1 and BL2 are returned to 0 V, and the word line WL1 is finally closed to complete the write cycle.
[0022]
The above-mentioned Patent Documents 1 and 2 propose to access a plurality of capacitors in the memory unit MU collectively and continuously in order to limit the frequency of occurrence of such disturb degradation.
Since the ferroelectric memory is a destructive read, rewriting is always performed after the read to refresh the data. If the specification is such that the capacitors in the memory unit MU are accessed all at once, all capacitors are always accessed once and refreshed at the time of unit access. Therefore, assuming that N capacitors are connected to one memory unit MU, the disturb voltage is applied only N times between refreshes in the worst case.
[0023]
Thus, it is very important to define the worst case of disturb occurrence. Here, it is effective to limit the disturb voltage generation to a maximum of N times as described above, but as the number of connected cells, that is, the number of capacitors in the memory unit MU increases, the worst case disturb occurrence frequency increases. I do.
For example, when data “0” is written to only one cell (capacitor) and data “1” is written to all other cells in the same memory unit MU, the cell storing data “0” is disturbed. The worst case occurs. That is, the cell in which the data "0" is stored continuously receives the disturbance in the destruction direction during its own write cycle and while the data "1" is stored in other cells.
[0024]
The operating margin of the memory must be ensured corresponding to such a worst case. For this reason, when the number of occurrences of disturb as a worst case increases due to an increase in the number of cells, it becomes difficult to obtain a sufficient operation margin accordingly, and it may be difficult to secure an operation signal amount and an operation speed. .
In other words, it is required to reduce the worst case disturb occurrence frequency.
[0025]
[Means for Solving the Problems]
Accordingly, an object of the present invention is to reduce the number of times of occurrence of disturb as a worst case for a ferroelectric capacitor.
[0026]
A semiconductor memory device according to the present invention includes N (N is a natural number) ferroelectric capacitors each having one electrode connected to a common node and the other electrode connected to a different plate line, and a column direction along a bit line. And a plurality of memory units arranged in an array in a row direction along the plate line, and a plurality of memory units having gates connected to word lines and connected between the respective common nodes and the corresponding bit lines. A semiconductor memory comprising: a selection transistor, a word line driving means for selecting a memory unit to be accessed by selectively driving the word line, and a plate line driving means for selectively driving the plate line. Device. Then, by selectively driving the bit line, the ferroelectric capacitor to be accessed is selected, and at the time of data writing, a first level having a write level potential with respect to the selected bit line is provided. And a bit line driving means for applying a second pulse having a polarity opposite to that of the writing level potential, and the plate line driving means applies a first pulse and a second pulse during the application period of the first and second pulses. In the above, an unselected plate line in the selected memory unit is set to an intermediate potential between the first and second pulses.
The first and second pulses have substantially the same pulse width.
The bit line driving means applies the second pulse only when the write data is the same as the write data to the ferroelectric capacitor accessed immediately before in the selected memory unit.
[0027]
Further, the present invention includes N (N is a natural number) ferroelectric capacitors each having one electrode connected to a common node and the other electrode connected to different plate lines, respectively. A plurality of memory units arranged in an array in a row direction along a line, and a plurality of select transistors each having a gate connected to a word line and connected between each of the common nodes and the corresponding bit line A word line driving means for selecting a memory unit to be accessed by selectively driving the word lines; a plate line driving means for selectively driving the plate lines; and selectively driving the bit lines. A data write method in a semiconductor memory device, comprising: a bit line driving means for selecting the ferroelectric capacitor to be accessed by driving. A. At the time of data writing, a first pulse having a writing level potential and a second pulse having a potential opposite in polarity to the writing level potential are applied to the selected bit line. During the application period of the first and second pulses, the non-selected plate line in the selected memory unit is set to an intermediate potential between the first and second pulses.
The second pulse is applied only when the write data is the same as the data written to the ferroelectric capacitor accessed immediately before in the selected memory unit.
[0028]
According to the present invention, in writing in a cross-point type ferroelectric memory, an opposite pulse is applied to a bit line before and after a write voltage pulse, and the plate potential of a non-selection capacitor in the same memory unit is set to both. It is set near the middle of the pulse. As a result, a pair of the write level potential pulse and the opposite level potential pulse are applied to unselected cells (ferroelectric capacitors) as voltages in different directions. That is, the disturb voltage in the destruction direction and the voltage in the opposite direction are applied in pairs. Therefore, in the relationship between the data held in a certain cell and the write data to another cell, even if a disturb voltage in the destruction direction is applied to a certain cell, the voltage in the recovery direction is applied immediately after the disturb voltage is applied to the certain cell. Become.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor memory device and a data writing method according to the present invention will be described. First, the operating principle for improving the worst-case disturbance will be described, and then the first and second embodiments will be described.
[0030]
<Operation principle for worst-case improvement of disturbance>
In the present invention, when a voltage is applied to the ferroelectric capacitor in the disturb direction, if the same voltage is applied in the opposite direction immediately after that, the state is restored via a minor loop on the hysteresis curve. We paid attention to the phenomenon of returning.
[0031]
FIG. 1 shows a schematic diagram thereof. FIG. 1 shows the relationship between the voltage Vr applied to the capacitor and the polarization amount P of the ferroelectric film generated according to the voltage Vr.
The polarization direction of the ferroelectric film is changed by applying a pulse of the power supply voltage Vcc between the two poles, and the state changes from (h0) through (h1) to (h2) on the hysteresis curve shown in the figure. It changes to. This polarization amount of (h2) corresponds to the stored data “1”.
Further, when a −Vcc pulse is further applied, the state returns from (h2) to (h0) through (h3). The polarization amount of (h0) becomes the stored data “0”.
That is, the ferroelectric memory normally stores different data in the states (h0) and (h2).
[0032]
Here, a case where a pulse of the intermediate voltage Vm is initially applied to a capacitor whose both electrodes have the same potential and whose polarization state is at the position (h0).
Then, the state of the capacitor changes to (h5) via (h4), and the amount of polarization temporarily deteriorates.
However, if a pulse of -Vm is applied immediately thereafter, the state returns to the original (h0) via (h6).
On the other hand, when the same Vm pulse is continuously applied from the state of (h5), the state further deteriorates through (h7) and reaches (h8).
[0033]
The above indicates that the disturb voltage does not immediately deteriorate the data, and that it is a more essential problem that disturb is continuously applied in the same direction.
Therefore, if the phenomenon is used, the worst case of the occurrence of the disturbance can be improved.
More specifically, for example, immediately after the disturb voltage from (h0) to (h5) via (h4) is applied, the disturbance is reversed from (h5) to (h0) via (h6). If a voltage in the direction (recovery pulse) is applied, the degradation due to the disturb voltage does not occur. By utilizing this, it is possible to minimize the generation of a disturbance voltage that is continuous in the same direction.
[0034]
<First embodiment>
This embodiment relates to a semiconductor memory device as a cross-point type ferroelectric memory. The basic configuration is as shown in FIG. 15 or FIG.
[0035]
That is, a memory in which each one end of N (four in FIG. 15 and FIG. 16) ferroelectric capacitors C for storing independent data is connected to the common node electrodes (11, 12,...). A plurality of units MU (MU1, MU2,...) Are arranged in an array in each direction of the bit lines BL arranged in the column direction and the word lines WL arranged in the row direction.
In addition, the common node electrodes (11, 12) of each memory unit MU are connected to the bit line via at least a select transistor (T1, T2 in FIG. 15, T13, T23 in FIG. 16, etc.) connected to the gate of the word line WL. It is connected to BL.
The other ends of the N ferroelectric capacitors C in each memory unit MU are respectively connected to N plate lines PL arranged in the same direction as the word lines WL.
The word line decoder / driver 1 for selecting a memory unit MU in a specific row by applying a voltage to a specific word line WL, and the voltage application state to each plate line PL corresponding to the specific row, And a plate line decoder / driver 2 for selecting a specific ferroelectric capacitor C in the memory unit MU, and a specific pair of memory units by applying a voltage to a specific pair of bit lines (BL1, BL2) in the bit line BL. By selecting (MU1, MU2), the sense amplifier 3 is provided which accesses a specific pair of ferroelectric capacitors in accordance with the voltage application state to the word line WL and the plate line PL.
[0036]
In this embodiment, the basic configuration is the same as that of FIGS. 15 and 16 except that the voltage application method to the bit line BL by the sense amplifier 3 and the voltage application to the plate line PL by the plate line decoder 2. The method is characterized.
That is, at the time of data writing, the sense amplifier 3 applies a pulse of the write level potential and a pulse of the opposite level potential to the pair of bit lines BL1 and BL2 before and after. In addition, during the application period of both these pulses, the plate line decoder / driver 2 sets the non-selected plate line PL for the selected memory units MU1 and MU2 to an intermediate potential between the two pulses.
[0037]
FIG. 2 shows a voltage application operation during data writing. FIG. 3 shows a part of the cross-point type ferroelectric memory as in FIG. 18 described above.
First, the write operation of FIG. 2 which characterizes the present embodiment will be described with reference to FIG.
[0038]
Now, in FIG. 3A, a case where data “1” is written to the capacitor C11 is taken as an example.
In this case, it is assumed that data “0” is written in advance to each capacitor (C11, C21...) On the plate line PL1 serving as a selected plate line, and in that case, the data is stored in the capacitor C11 on the bit line BL1. "1" is written so that data "0" of the capacitor C21 on the bit line BL2 is stored.
In FIG. 2, one cycle of the write operation is shown in a period of w1 to w9.
[0039]
FIG. 2A shows a voltage applied state to the word line WL1. This voltage application is executed by the word line decoder / driver 1 shown in FIG.
FIG. 2B shows a voltage applied state to a plate line PL1 serving as a selected plate line, and FIG. 2C shows a voltage applied state to a plate line PL2 (and PL3 and PL4 not shown) serving as a non-selected plate line. . The voltage application to these plate lines PL is executed by the plate line decoder / driver 2.
FIG. 2D shows a voltage applied state to the bit line BL1, and FIG. 2E shows a voltage applied state to the bit line BL2. The voltage application to these bit lines BL1 and BL2 is executed by the sense amplifier 3.
[0040]
Period w1: The word line WL1 corresponding to the selected memory unit (MU1, MU2) is opened, and the memory units MU1, MU2 are connected to the bit lines BL1, BL2.
Period w2: A potential of (１ ／) Vcc is applied to each bit line BL1, BL2.
Period w3: The potentials of the unselected plate lines PL2 to PL4 are raised to (2/3) Vcc. On the other hand, the potential of the selection plate line PL1 is kept at 0V.
Period w4: Write pulse WP of voltage Vcc is applied to bit line BL1 in which data “1” is written. For the bit line BL2, the write pulse WP remains (１ ／) Vcc in order to store data “0”.
As a result, the state shown in FIG. That is, the voltage Vcc is applied only to the selected capacitor C11 to which the data “1” is written, and the writing is executed. At the same time, a voltage of (1/3) Vcc or-(1/3) Vcc is applied to the non-selected capacitors (C12, C21, C22, etc.). Depending on the data stored in each capacitor, (1/3) Vcc or-(1/3) Vcc is a disturbance voltage that degrades data. That is, if (1/3) Vcc or-(1/3) Vcc is a voltage directed in the opposite polarization direction as viewed from the stored data, it becomes the disturb voltage.
[0041]
Period w5: The write pulse WP ends. That is, the bit line BL1 is returned to (１ ／) Vcc. At this time, the select plate line PL1 is raised to (2/3) Vcc.
[0042]
Period w6: Invert pulse NP is applied to each bit line BL1, BL2. That is, the bit line BL1 for writing the data “1” is kept at (３) Vcc, and the pulse of the voltage Vcc is applied to the bit line BL2 for storing the data “0”.
As a result, the state shown in FIG. That is,-(1/3) Vcc is applied to the selected capacitor C11 to which data "1" is written, and (1/3) Vcc or-is applied to the non-selected capacitors (C12, C21, C22, etc.) at the same time. A voltage of (１ ／) Vcc is applied.
In this case, focusing on the unselected capacitor C12 in FIGS. 3A and 3B,-(1/3) Vcc in the period w6 immediately after (1/3) Vcc is applied in the period w4. Is applied. Looking at the unselected capacitor C22, (1/3) Vcc is applied in the period w6 immediately after-(1/3) Vcc is applied in the period w4. That is, the capacitors C12 and C22 are recovered in the period w6 even if the applied voltage in the period w4 becomes a disturb voltage in the opposite polarization direction to the stored data and data is deteriorated.
In this case, (例) Vcc is applied to the capacitor C21 in both the periods w4 and w6. Therefore, when the capacitor C21 stores data "0" as in this example, the disturbance is continuously received. That is, the capacitor C21 does not recover from the degradation due to the disturbance which is intended in this example. If attention is paid only to a certain capacitor in only one write cycle, some capacitors whose deterioration is not recovered occur as described above. However, when viewed as a whole and in time series, the application of the inversion pulse NP during the period w6 causes The disturb worst case is a significant improvement. The worst case improvement will be described later.
[0043]
Period w7: The inversion pulse NP ends. That is, the bit line BL2 is returned to (１ ／) Vcc.
Period w8: The selected plate line PL1 and the unselected plate lines PL2 to PL4 are returned to 0V.
Period w8: The bit lines BL1 and BL2 are returned to 0 V, and the word line WL1 is finally closed to complete the write cycle.
[0044]
As described above, in the sequence of the write cycle in this example, the inversion pulse NP which is the reverse of the write pulse WP is applied to each of the bit lines BL1 and BL2 as the period w6.
With the application of the inversion pulse NP, an intermediate voltage in a direction opposite to that at the time of application of the write pulse WP is applied to many non-selected capacitors.
The capacitor that has been disturbed in the destruction direction when the write pulse WP is applied recovers its deterioration when it receives a pulse in the opposite direction, so that it is easy for such a pulse application to contribute to the reduction of data deterioration. It can be understood.
Further, the period lengths of the periods w4 and w6 are equal, that is, the pulse widths of the write pulse WP and the inversion pulse NP are equal. When the write pulse WP has a disturb voltage in the destruction direction, it is easily understood that the inversion pulse NP having the same pulse width is appropriate for deterioration recovery.
Although the present embodiment describes a case where one bit is stored complementarily by a pair of capacitors, a case where one bit is stored by one capacitor can be handled by the same operation. That is, when writing an independent bit to each capacitor, the bit line BL1 is used for the operation of a selected bit line connected to an arbitrary capacitor on which a “1” is to be written on the selected plate line, and the bit line BL2 is used for other operations. (I.e., to store "0") should correspond to the operation of the non-selected bit line connected to the capacitor.
[0045]
By the way, the following points need to be noted. That is, when the reverse inversion pulse NP is applied to the capacitor which has been receiving a pulse in the forward direction at the time of application of the write pulse WP, deterioration is newly caused by the inversion pulse NP.
Further, there is a capacitor to which the opposite potential is not always applied, such as the capacitor C21 described above.
However, according to this example, as will be described later, the dependence of the deterioration due to the write pattern can be averaged, and the amount of deterioration in the worst case can be alleviated. The effect is enormous.
[0046]
Here, the configuration and operation of the plate line decoder / driver 2 and the sense amplifier 3 for realizing the write cycle of FIG. 2 will be described.
In other words, this is a configuration example that realizes the voltage application operation shown in FIGS.
[0047]
FIG. 4 shows a configuration example of the plate line decoder / driver 2.
The plate line decoder / driver 2 shown in FIGS. 15 and 16 adopts the configuration shown in FIG. 4 in the present embodiment, and as shown in FIGS. Is realized.
[0048]
In this case, the plate line decoder / driver 2 includes a decoder unit 21, driver units 22-1, 22-2,... Provided corresponding to each plate line PL, and a signal generation unit 23.
The decoder unit 21 outputs a signal D = "1" to the driver unit 22 corresponding to the selected plate line, and outputs a signal D = "0" to the driver unit 22 corresponding to the non-selected plate line.
When the plate line PL1 is the selected plate line as in the examples of FIGS. 2 and 3, "1" is output as the signal D1 to the driver unit 22-1 for the plate line PL1 as shown in FIG. Are output as signals D2, D3,... To the driver units 22-2,.
[0049]
Each of the driver sections 22 (22-1, 22-2,...) Has the same configuration, and has an inverter 24 (24-1, 24-2,...) And an AND gate 25 (25-1, 25-2, respectively). ...), NOR gates 26 (26-1, 26-2 ...), depletion type (NMOS) transistors (QP11, QP21 ...), enhancement type (PMOS) transistors (QP12, QP22 ...) have.
[0050]
Describing the driver section 22-1, the signal D1 from the decoder section 21 is inverted by the inverter 24-1 and input to the AND gate 25-1. The signal SP1 is input from the signal generator 23 to the other end of the AND gate 25-1.
The logical product output from the AND gate 25-1 is supplied to the NOR gate 26-1. The signal SP2 is input from the signal generator 23 to the other end of the NOR gate 26-1. The output of the NOR gate 26-1 is applied to each gate of the transistors QP11 and QP12.
The drain of the transistor QP11 is connected to a voltage (2/3) Vcc line, and the source of the transistor QP11 is connected to the drain of the transistor QP12. The source of transistor QP12 is grounded.
The connection point between the source of transistor QP11 and the drain of transistor QP12 is connected to plate line PL1.
The other driver units 22-2 have the same configuration.
[0051]
The driving operation of the plate line by the plate line decoder / driver 2 will be described with reference to FIG. FIGS. 5A and 5F similarly show the voltages applied to the plate lines PL1 and PL2 shown in FIGS. 2B and 2C as they are.
That is, this is an example in which the plate line PL1 is a selected plate line and the plate line PL2 (and PL3, PL4, not shown) is a non-selected plate line in accordance with FIG.
[0052]
In this write cycle, since the plate line PL1 is used as the selected plate line, the signal D1 output from the decoder unit 21 becomes "1" as shown in FIG.
On the other hand, since the plate line PL2 is an unselected plate line, the signal D2 output from the decoder unit 21 becomes “0” as shown in FIG.
During the write cycle, the signal generator 23 generates the signals SP1 and SP2 in the sequence shown in FIGS. That is, the signal SP1 is generated as a signal that becomes “1” in the periods w3 and w4. On the other hand, the signal SP2 is generated as a signal that becomes “1” in the periods w5, w6, and w7.
[0053]
As described with reference to FIG. 2, the voltage applied to the non-selected plate line PL2 in FIG. 5F is (2/3) Vcc in the periods w3, w4, w5, w6, and w7.
In the periods w3 and w4, the output of the NOR gate 26-2 is "0" because the signal SP1 is "1". In the periods w5, w6, and w7, the output of the NOR gate 26-2 is "0" because the signal SP2 is "1".
As a result, the voltage applied to the unselected plate line PL2 becomes (2/3) Vcc in the periods w3, w4, w5, w6, and w7.
The same applies to other unselected plate lines PL3 and PL4 not shown.
[0054]
On the other hand, the voltage applied to the selection plate line PL1 shown in FIG. 5A is (2/3) Vcc in the periods w5, w6, and w7.
In the periods w3 and w4, the signal SP1 is “1”, but the output of the NOR gate 26-2 is “1” because the output signal D1 of the decoder unit 21 is “1”. The output of the NOR gate 26-2 is "0" only during the periods w5, w6, and w7 during which the signal SP2 is "1".
Thus, the voltage applied to the selection plate line PL1 becomes (2/3) Vcc in the periods w5, w6, and w7.
[0055]
Next, a configuration example of the sense amplifier 3 will be described with reference to FIG.
In the present embodiment, the sense amplifier 3 shown in FIGS. 15 and 16 adopts the configuration as shown in FIG. 6A, and as shown in FIGS. , BL2.
[0056]
As shown in FIG. 6A, the sense amplifier 3 has a latch circuit 31-1, enhancement type (PMOS) transistors QB11 and QB12, and a switch SW1 corresponding to the bit line BL1. Further, it has a latch circuit 31-2, enhancement type (PMOS) transistors QB21 and QB22, and a switch SW2 corresponding to the bit line BL2.
Further, a signal generation unit 32 that generates signals SB1 and SB2 for controlling the transistors QB11, QB12, QB21, and QB22 is provided.
[0057]
The drive circuit for such bit lines BL1 and BL2 operates between the voltage Vcc and (１ ／) Vcc.
The switches SW1 and SW2 are provided to set the potentials of the bit lines BL1 and BL2 to 0V.
That is, the bit line BL1 is at 0 V while the switch SW1 is on. While the switch SW1 is off, the reference potential of the bit line BL1 is (１) Vcc. The same applies to the potential state of the bit line BL2 by the switch SW2.
[0058]
Write data DT is input to the latch circuits 31-1 and 31-2.
That is, when writing data "1" to the capacitor on the bit line BL1, the input data DT to the latch circuit 31-1 becomes "1", while the input data DT to the latch circuit 31-2 becomes "0". Become.
Since this circuit system operates between voltage Vcc and (1/3) Vcc, as shown in FIG. 6B, when data DT = "1" is input, latch circuits 31-1, 31- 2 has a voltage Vcc, and the inverted output Q # has a (1/3) Vcc. When data DT = "0" is input, the output Q of latch circuits 31-1 and 31-2 becomes voltage (1/3) Vcc, and inverted output Q # becomes Vcc.
[0059]
The operation of driving the bit lines BL1 and BL2 by the sense amplifier 3 will be described with reference to FIG. FIGS. 7A and 7D similarly show the voltages applied to the bit lines BL1 and BL2 shown in FIGS. 2D and 2E.
[0060]
That is, in the write cycle shown in FIG. 7, an operation of writing data "1" to the capacitor C11 on the bit line BL1 and holding data "0" of the capacitor C21 on the bit line BL2 as described with reference to FIG. Is shown.
Therefore, "1" is input as data DT to the latch circuit 31-1 corresponding to the bit line BL1, and "0" is input to the latch circuit 31-2 corresponding to the bit line BL2.
[0061]
In this write cycle, the switches SW1 and SW2 connected to the bit lines BL1 and BL2 are turned off in the periods w2, w3, w4, w5, w6, w7, and w8.
The signal generator 32 generates the signals SB1 and SB2 in the sequence shown in FIGS. 7B and 7C. That is, the signal SB1 is generated as a signal that becomes “1” in the period w4, and the signal SB2 is generated as a signal that becomes “1” in the period w6.
[0062]
In the periods w2 and w3, the signals SB1 and SB2 are “0” and “0”, and the transistors QB11, QB12, QB21, and QB22 are all off. Since the switches SW1 and SW2 are off, the bit lines BL1 and BL2 are both at (１ ／) Vcc.
In the period w4, the signals SB1 and SB2 are “1” and “0”, and the transistors QB11 and QB21 are turned on. Therefore, each latch output Q of the latch circuits 31-1 and 31-2 is applied to the bit lines BL1 and BL2, respectively. Since the latch output Q of the latch circuit 31-1 is Vcc and the latch output Q of the latch circuit 31-2 is (１ ／) Vcc, the potentials of the bit lines BL1 and BL2 are shown in FIG. State. That is, Vcc is applied to the bit line BL1 and (１ ／) Vcc is applied to the bit line BL2 as the write pulse WP.
In the period w5, the signals SB1 and SB2 are "0" and "0", the transistors QB11, QB12, QB21, and QB22 are all off, and the bit lines BL1 and BL2 are all at (1/3) Vcc.
In the period w6, the signals SB1 and SB2 are “0” and “1”, and the transistors QB12 and QB22 are turned on. Therefore, inverted outputs Q # of latch circuits 31-1 and 31-2 are applied to bit lines BL1 and BL2, respectively. Since inverted output Q # of latch circuit 31-1 is (1/3) Vcc and inverted output Q # of latch circuit 31-2 is Vcc, the potentials of bit lines BL1 and BL2 are The state shown in FIG. That is, (１ ／) Vcc is applied to the bit line BL1 and Vcc is applied to the bit line BL2 as the inversion pulse NP.
In the periods w7 and w8, the signals SB1 and SB2 are "0" and "0", the transistors QB11, QB12, QB21, and QB22 are all off, and the bit lines BL1 and BL2 are all at (1/3) Vcc. .
Then, in a period w9, the switches SW1 and SW2 connected to the bit lines BL1 and BL2 are turned on, and the bit lines BL1 and BL2 become 0V.
[0063]
As described above, by configuring the plate line decoder / driver 2 and the sense amplifier 3, the write operation described with reference to FIG. 2 is realized. That is, the inversion pulse NP is applied immediately after the write pulse WP, and during the application period of both pulses, the non-selected plate line is set to an intermediate potential between both pulses WP and NP.
[0064]
The worst case of disturb generation according to the present embodiment will be described with reference to FIGS.
Here, an example is described in which one memory unit is provided with eight cells (ferroelectric capacitors).
[0065]
FIG. 8A shows a conventional example, that is, the worst case of occurrence of disturbance to “0” data in the case of the write operation described with reference to FIG.
In the case of the conventional example, the disturb occurrence to the “0” data is as follows. First, “0” is written to the first cell (C0), and “1” is written to all the remaining cells. On the other hand, the largest disturbance degradation occurs.
That is, as shown in the upper case in FIG. 8A, when the first cell (C0) is accessed, the voltage applied state to the cell (C0) corresponds to the capacitor (C21) in FIG. + Voltage in the direction is applied.
Further, when "1" is written to the remaining cells, the voltage applied state to the cell (C0) corresponds to the capacitor (C12) in FIG. 18, and the + voltage in the deterioration direction is also applied.
Therefore, a total of eight disturbances are continuously applied to the cell (C0). As described above, in the worst case of the conventional example, generally, when the number of connected cells of the memory unit MU is N, disturb degradation occurs N times.
[0066]
On the other hand, FIG. 8A shows a case where “0” is similarly written in the first cell (C0) and “1” is written in all remaining cells in the case of the present embodiment.
In this case, when the first cell (C0) is accessed, the voltage applied state to the cell (C0) corresponds to the capacitor (C21) in FIG. 3, and the deterioration direction is caused by both the write pulse WP and the inversion pulse NP. + Voltage is applied. This is as described in the description of FIGS. 2 and 3 as to the case where the application of the inversion pulse NP does not result in the application of the inverse voltage to the capacitor.
However, when writing data "1" to the remaining cells, a positive voltage in the deterioration direction and a negative voltage in the recovery direction are applied to the first cell (C0) as a pair as indicated by a broken line. Will be. That is, the deterioration due to the + voltage application is recovered immediately by the − voltage application.
As a result, the substantial disturb deterioration is only twice.
[0067]
However, in the case of the present embodiment, the worst case occurs in a different pattern from the conventional worst case. This is shown in FIG.
FIG. 8B shows a case where "0" and "1" are alternately written in each cell. In this case, in the case of the conventional example shown in the upper part, the disturbance degradation is twice.
[0068]
In the case of the present embodiment, as shown in the lower part, disturb degradation occurs five times. That is, two degradations occur at the time of writing to the first cell (C0). Thereafter, when “1” data is written in the subsequent cell, the deterioration due to the application of the + voltage due to the write pulse WP is recovered by the application of the − voltage due to the immediately following inversion pulse NP.
However, when "0" data is written in the subsequent cell, the negative voltage due to the first write pulse WP does not become in the disturb deterioration direction, but the inverted pulse NP immediately after the negative voltage causes the disturb is generated. As a result, deterioration occurs. That is, the application of the inversion pulse NP causes the occurrence of the disturbance on the contrary.
Therefore, in this case, disturb deterioration occurs five times due to five positive voltage applications not surrounded by the broken line.
[0069]
As can be seen from FIG. 8, when eight cells are connected to the memory unit MU, the disturb deterioration is eight at the worst in the conventional example, but is five at the worst in the present embodiment. .
Generally speaking, when N cells are connected to the memory unit MU, the disturb deterioration is worst at N times in the conventional example, but is (N / 2) +1 at worst in the present embodiment. Times, which is almost half of the worst case in the past.
[0070]
Next, FIG. 9 similarly shows an example of occurrence of disturbance to “1” data.
FIG. 9A shows the worst case in the conventional example. In this case, when "1" is first written in the first cell (C0) and "0" is written in all remaining cells, the maximum disturb degradation occurs in the first cell (C0).
In this case, at the time of the first access, there is no disturbance because the cell (C0) itself is written. However, when "0" is written to another cell, the voltage applied state to the cell (C0) corresponds to the capacitor (C22) in FIG. 18, and a negative voltage in the deterioration direction is applied.
Therefore, a total of seven disturbances are continuously applied to the cell (C0). As described above, in the worst case of the conventional example, when the number of cells connected to the unit is generally N, disturb degradation occurs (N-1) times.
[0071]
On the other hand, in the case of the present embodiment in the lower part of FIG. 9A, the state of voltage application to the cell (C0) is such that the capacitor (C11) of FIG. Is applied, which results in disturb degradation. However, when "0" is written to other cells thereafter, the first cell (C0) becomes equivalent to the capacitor (C22) in FIG. 3, that is, immediately after the application of the-voltage during the write pulse WP, The + voltage at the time of the inversion pulse NP is applied to recover the immediately preceding deterioration. Therefore, the substantial disturbance degradation is limited to one time.
[0072]
In the case of the present embodiment, the worst case of the occurrence of the disturbance to the “1” data is a case where “1” and “0” are alternately written as shown in FIG. 9B.
In this case, as shown in the upper part of FIG. 9B, in the conventional example, the disturbance degradation is one time, but in the present embodiment shown in the lower part, the unrecovered disturbance degradation is four times. That is, the application of the negative voltage by the inversion pulse NP at the time of writing "1" to the cell (C0) and other cells thereafter causes disturb deterioration.
Generally, it is (N / 2) times.
[0073]
As can be seen from FIGS. 8 and 9, in the case of the conventional example, the disturb degradation is N times or (N−1) times in the worst case. / 2) +1 times or (N / 2) times, which means that the number of disturbances can be reduced to about half. That is, the intended purpose of reducing the number of disturbance occurrences as the worst case is sufficiently achieved.
[0074]
<Second embodiment>
According to the above-described first embodiment, the worst case of disturb is greatly reduced. However, the application of the inversion pulse NP may cause an extra disturbance, and if this portion is improved, the number of times of disturbance degradation can be further reduced.
Thus, in the second embodiment, the inversion pulse NP is applied only when the same data as the immediately preceding data is written, thereby minimizing extra disturbance.
That is, as can be seen from the worst case of the first embodiment shown in FIGS. 8 and 9, when “0” and “1” are written alternately, the inversion pulse NP does not function as a recovery pulse. Conversely, disturb degradation may occur. Considering this, if the inversion pulse NP is applied only when the same data as the immediately preceding data is written, it is possible to minimize the case where the disturbance occurs due to the inversion pulse NP.
[0075]
Also in the second embodiment, the operation of the write cycle at the time of data writing is basically the same as that of FIG. 2 described above.
However, the inversion pulse NP is applied as shown in FIG. 2 when writing the same data as the immediately preceding data.
When writing data different from the immediately preceding data, the operation in the write cycle is as shown in FIG. That is, as shown in FIGS. 10D and 10E, the inversion pulse NP is not applied in the period w6. Here, instead of the inversion pulse NP of the voltage Vcc, an adjustment pulse NNP of the voltage (2/3) Vcc is applied to each of the bit lines BL1 and BL2.
[0076]
In the example of FIG. 10, the adjustment pulse NNP is applied in place of the inversion pulse NP in the period w6. However, in this period w6, the adjustment pulse NNP is not applied, and the bit lines BL1 and BL2 are set to ( (１ ／) Vcc may be maintained. However, in this case, it is necessary to change the potential of the plate line in order to optimize the voltage application state to each cell (capacitor). That is, the plate line driving method is different between the case where the inversion pulse NP is applied as shown in FIG. 2 and the case where the inversion pulse NP is not applied as shown in FIG. You have to change it.
In this embodiment, by applying the adjustment pulse NNP of (2/3) Vcc, the driving of each plate line PL by the plate line decoder / driver 2 can be the same as in FIG. It is.
[0077]
FIG. 11 shows a voltage application state in a write cycle in which the adjustment pulse NNP is applied without applying the inversion pulse NP as shown in FIG.
The application of the write pulse WP in the period w4 is the same as the cycle in FIG. 2, that is, the voltage application state in FIG. 11A is the same as that in FIG.
When the adjustment pulse NNP is applied during the period w6 (when the inversion pulse NP is not applied), the voltage application state is as shown in FIG.
That is, since the bit lines BL1 and BL2 are each set to (2/3) Vcc, and all the plate lines PL are also set to (2/3) Vcc, the potential difference applied to the capacitors C11, C12, C21 and C22 is 0V. .
[0078]
A configuration for switching and executing the write cycle in FIG. 2 and the write cycle in FIG. 10 depending on whether the immediately preceding write data and the current write data are the same will be described.
Since the driving method of the plate line PL is the same in each cycle of FIGS. 2 and 10, the plate line decoder / driver 2 may have the configuration and operation described with reference to FIGS.
In this case, in order to switch between the write cycles shown in FIGS. 2 and 10, the sense amplifier 3 may be configured as shown in FIG. 12, for example.
[0079]
In the present embodiment, the sense amplifier 3 shown in FIGS. 15 and 16 adopts the configuration as shown in FIG. 12, and determines whether each bit line BL1 and BL2 is identical to the immediately preceding write data. Thus, the voltage application shown in FIGS. 2D and 2E or the voltage application shown in FIGS. 10D and 10E is realized.
[0080]
That is, in this case, the sense amplifier 3 includes a latch circuit 31-1, enhancement-type (PMOS) transistors QB11, QB12, QB13, a switch SW1, a latch circuit 34-1 and an EX-OR gate 35 corresponding to the bit line BL1. -1, an inverter 36-1, and NOR gates 37-1 and 38-1. The terminal 33-1 is supplied with a voltage of (2/3) Vcc.
The sense amplifier 3 includes a latch circuit 31-2, enhancement type (PMOS) transistors QB21, QB22, QB23, a switch SW2, a latch circuit 34-2, an EX-OR gate 35-2, corresponding to the bit line BL2. It has an inverter 36-2 and NOR gates 37-2 and 38-2. The terminal 33-2 is supplied with a voltage of (2/3) Vcc.
Further, a signal generation unit 32 that generates signals SB1 and SB2 for controlling the transistors QB11, QB12, QB13, QB21, QB22, and QB23 is provided. Inverter 39 is provided for signal SB2 output from signal generation unit 32.
[0081]
Similar to the sense amplifier 3 of the first embodiment described with reference to FIG. 6, the drive system circuit for the bit lines BL1 and BL2 as shown in FIG. 12 operates between the voltage Vcc and (（) Vcc. . The switches SW1 and SW2 are provided to set the potentials of the bit lines BL1 and BL2 to 0V. That is, the bit line BL1 is at 0 V while the switch SW1 is on. While the switch SW1 is off, the reference potential of the bit line BL1 is (１) Vcc. The same applies to the potential state of the bit line BL2 by the switch SW2.
[0082]
Write data DT is input to the latch circuits 31-1 and 31-2.
When writing data "1" to the capacitor on bit line BL1, input data DT to latch circuit 31-1 becomes "1", while input data DT to latch circuit 31-2 becomes "0". .
Similarly, the potentials as the output Q and the inverted output Q # of the latch circuits 31-1 and 31-2 become as shown in FIG. 6B according to the value of the input data DT.
[0083]
The values of the output Q of the latch circuits 31-1 and 31-2 are input to the latch circuits 34-1 and 34-2, respectively. That is, the latch circuits 34-1 and 34-2 latch and output the value of the write data in the immediately preceding write cycle.
The EX-OR gates 35-1 and 35-2 store the write data input to the latch circuits 31-1 and 31-2 as the output Q in the current write cycle and the latch circuits 34-1 and 34-2. , And outputs the exclusive OR of the values of the write data in the immediately preceding write cycle.
[0084]
The transistors QB11 and QB21 are controlled by a signal SB1 applied to the gate.
The transistor QB12 is controlled by applying the signal SB2 inverted by the inverter 39 and the output of the NOR gate 38-1 that inputs the EX-OR gate 35-1 to the gate. The transistor QB22 is controlled by applying the signal SB2 inverted by the inverter 39 and the output of the NOR gate 38-2 that inputs the EX-OR gate 35-2 to the gate.
The transistor QB13 has its gate applied with the signal SB2 inverted by the inverter 39 and the output of the NOR gate 37-1 for inputting the signal obtained by inverting the output of the EX-OR gate 35-1 by the inverter 36-1. Is controlled by
The transistor QB23 has its gate receiving the signal SB2 inverted by the inverter 39 and the output of the NOR gate 37-2 inputting the signal inverted from the output of the EX-OR gate 35-2 by the inverter 36-2. Is controlled by
[0085]
The driving operation of the bit lines BL1 and BL2 by the sense amplifier 3 is as shown in FIG. 7 or FIG.
FIGS. 13A and 13D show the voltages applied to the bit lines BL1 and BL2 shown in FIGS. 10D and 10E as they are.
[0086]
First, a case where the write data of the current write cycle is the same as the write data of the previous write cycle will be described.
For example, the last time, the operation of writing data “1” to the capacitor C11 on the bit line BL1 and holding the data “0” of the capacitor C21 on the bit line BL2 as it is, this time, the operation of the next capacitor C12 on the bit line BL1 , And the operation of holding the data “0” of the capacitor C22 on the bit line BL2 as it is is performed.
[0087]
In this case, the bit lines BL1 and BL2 are driven as shown in FIG.
The input data DT to the latch circuit 31-1 is "1", and the latch data of the latch circuit 34-1 is also "1".
The input data DT to the latch circuit 31-2 is "0", and the latch data of the latch circuit 34-2 is also "0".
Therefore, in this write cycle, the outputs of the EX-OR gates 35-1 and 35-2 are "0".
[0088]
In the write cycle, the signal generator 32 generates the signals SB1 and SB2 in the sequence shown in FIGS. 7B and 7C (FIGS. 13B and 13C). That is, the signal generator 32 generates the signal SB1 as a signal that becomes “1” in the period w4, and generates the signal SB2 as a signal that becomes “1” in the period w6.
[0089]
In this write cycle, the switches SW1 and SW2 connected to the bit lines BL1 and BL2 are turned off in the periods w2, w3, w4, w5, w6, w7, and w8.
[0090]
In the periods w2 and w3, the signals SB1 and SB2 are “0” and “0”. In this case, the transistors QB11, QB12, QB13, QB21, QB22, and QB13 are all off. Since the switches SW1 and SW2 are off, the bit lines BL1 and BL2 are both at (１ ／) Vcc.
In the period w4, the signals SB1 and SB2 are “1” and “0”, and the transistors QB11 and QB21 are turned on. Therefore, each latch output Q of the latch circuits 31-1 and 31-2 is applied to the bit lines BL1 and BL2, respectively. Therefore, Vcc is applied to the bit line BL1 and (１ ／) Vcc is applied to the bit line BL2 as the write pulse WP.
In the period w5, the signals SB1 and SB2 are "0" and "0", the transistors QB11, QB12, QB13, QB21, QB22, and QB23 are all off, and the bit lines BL1 and BL2 are all (1/3) Vcc. It becomes.
[0091]
In the period w6, the signals SB1 and SB2 are “0” and “1”, and the outputs of the EX-OR gates 35-1 and 35-2 are “0”, so that the transistors QB12 and QB22 are turned on. Therefore, inverted outputs Q # of latch circuits 31-1 and 31-2 are applied to bit lines BL1 and BL2, respectively. That is, (１ ／) Vcc is applied to the bit line BL1 and Vcc is applied to the bit line BL2 as the inversion pulse NP.
In the periods w7 and w8, the signals SB1 and SB2 are “0” and “0”, the transistors QB11, QB12, QB13, QB21, QB22, and QB23 are all turned off, and the bit lines BL1 and BL2 are all (1/3). ) Vcc.
Then, in a period w9, the switches SW1 and SW2 connected to the bit lines BL1 and BL2 are turned on, and the bit lines BL1 and BL2 become 0V.
[0092]
Next, a case where the write data of the current write cycle is different from the write data of the previous write cycle will be described.
For example, the previous operation performed to hold data “0” in the capacitor C11 on the bit line BL1 and write data “1” to the capacitor C21 on the bit line BL2. , And the operation of holding the data “0” of the capacitor C22 on the bit line BL2 as it is is performed.
[0093]
In this case, the bit lines BL1 and BL2 are driven as shown in FIG.
The input data DT to the latch circuit 31-1 is “0”, and the latch data of the latch circuit 34-1 is “1”.
The input data DT to the latch circuit 31-2 is "1", and the latch data of the latch circuit 34-2 is "0".
Therefore, in this write cycle, the outputs of the EX-OR gates 35-1 and 35-2 are "1".
In the write cycle, the signal generator 32 generates the signals SB1 and SB2 in the same sequence as described above.
[0094]
Also in this write cycle, in the periods w2, w3, w4, w5, w6, w7, w8, the switches SW1, SW2 connected to the bit lines BL1, BL2 are turned off.
[0095]
In the periods w2 and w3, the signals SB1 and SB2 are “0” and “0”. In this case, the transistors QB11, QB12, QB13, QB21, QB22, and QB13 are all off. Since the switches SW1 and SW2 are off, the bit lines BL1 and BL2 are both at (１ ／) Vcc.
In the period w4, the signals SB1 and SB2 are “1” and “0”, and the transistors QB11 and QB21 are turned on. Therefore, each latch output Q of the latch circuits 31-1 and 31-2 is applied to the bit lines BL1 and BL2, respectively. Accordingly, (１ ／) Vcc is applied to the bit line BL1 and Vcc is applied to the bit line BL2 as the write pulse WP.
In the period w5, the signals SB1 and SB2 are "0" and "0", the transistors QB11, QB12, QB13, QB21, QB22, and QB23 are all off, and the bit lines BL1 and BL2 are all (1/3) Vcc. It becomes.
[0096]
In the period w6, the signals SB1 and SB2 are “0” and “1”, and the outputs of the EX-OR gates 35-1 and 35-2 are “1”, so that the transistors QB13 and QB23 are turned on. Therefore, the voltage (2/3) Vcc applied to the terminals 33-1 and 33-2 is applied to the bit lines BL1 and BL2. That is, the adjustment pulse NNP is applied.
In the periods w7 and w8, the signals SB1 and SB2 are “0” and “0”, the transistors QB11, QB12, QB13, QB21, QB22, and QB23 are all turned off, and the bit lines BL1 and BL2 are all (1/3). ) Vcc.
Then, in a period w9, the switches SW1 and SW2 connected to the bit lines BL1 and BL2 are turned on, and the bit lines BL1 and BL2 become 0V.
[0097]
With the configuration of the sense amplifier 3 as described above, the write operation of FIG. 2 or FIG. 10 is realized depending on whether or not it is the same as the immediately preceding write data.
That is, when the same write data continues, the inversion pulse NP is applied immediately after the write pulse WP, and during the application period of both pulses, the non-selected plate line is connected to the intermediate potential of both pulses WP and NP. To be. On the other hand, in the case of write data different from the last time, the inversion pulse NP is not applied immediately after the write pulse WP, and the adjustment pulse NNP is applied instead.
[0098]
By doing so, it is possible to minimize the extra disturbance generated due to the inversion pulse NP. This will be described with reference to FIG.
As described with reference to FIG. 8B, the worst case of “0” disturbance in the first embodiment is a case where “0” and “1” are alternately written, and the number of cells is set to eight. In this case, disturb degradation occurred five times. The number of cells N is (N / 2) -1 times.
However, in the case of the second embodiment, as shown in FIG. 14A, the disturb degradation occurs three times.
In other words, if the write data is different from the immediately preceding value, the inversion pulse NP is not applied, and therefore, as shown in the figure, the disturbance is only disturbed three times, ie, two times at the time of the initial + voltage application and one time at the end of the + voltage application. .
This does not change even if the number N of cells connected to the unit is increased, and is always three times.
[0099]
On the other hand, the worst case of the second embodiment is the case of FIGS.
FIG. 14B shows the worst case of the “0” disturbance, in which the write data sequentially advances as shown.
However, in this case as well, substantial disturb degradation occurs only at the time of the first three + voltage applications and the last + voltage application at the beginning of writing, and occurs four times irrespective of the number N of cells connected to the memory unit. is there.
FIG. 14C shows the worst case of the “1” disturbance, in which the write data sequentially advances as shown.
In this case as well, substantial disturb degradation occurs only at the time of one voltage application at the beginning of writing and at the time of one voltage application at the end of writing, and is only two times regardless of the number N of cells connected to the memory unit. .
[0100]
As can be seen from the above, according to the second embodiment, the worst case of disturbance is further reduced.
In addition, in this case, there is a remarkable merit that even if the number N of cells connected to the memory unit is increased, substantial disturbance degradation does not increase.
Therefore, it is possible not only to improve the operation margin, but also to increase the number of connected cells of the memory unit and reduce the overhead of the area occupied by the transistors and the contact portions provided for each memory unit MU.
[0101]
Although the embodiment has been described above, the configuration of the sense amplifier 3 and the plate line decoder / driver 2 or the voltage application operation as a write cycle is not limited to the above example, but is within the scope of the present invention. Various modifications are possible.
[0102]
【The invention's effect】
As can be understood from the above description, according to the present invention, the first pulse of the write level potential and the first pulse of the opposite level potential are applied to the non-selected cells (ferroelectric capacitors) as voltages in different directions. Two pulses are applied in pairs. In other words, even if the disturb voltage in the destruction direction is applied, the voltage in the recovery direction is immediately applied as a pair, so that the disturb voltage can be prevented from being applied many times continuously. This has the effect that the worst case of disturb occurrence can be greatly reduced. The effect also has an advantage that the effect becomes more remarkable as the number of cells (the number of ferroelectric capacitors) in the memory unit increases.
By making the first pulse and the second pulse have substantially the same pulse width, the first pulse and the second pulse are suitable for the degradation due to the disturbance and its recovery.
[0103]
The application of the second pulse is performed only when the write data is the same as the write data to the ferroelectric capacitor accessed immediately before in the selected memory unit. Can be prevented from acting as a disturb voltage, whereby the worst case of disturb generation can be further alleviated.
By alleviating the worst case, design for obtaining a required operation margin is facilitated, which is advantageous for higher performance in terms of the amount of operation signals and operation speed and further higher integration.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of an operation principle of an embodiment of the present invention.
FIG. 2 is an explanatory diagram of operation waveforms at the time of data writing according to the first embodiment.
FIG. 3 is an explanatory diagram of a state of application of a write pulse and an inversion pulse during data writing according to the first embodiment;
FIG. 4 is a block diagram of a plate line decoder / driver according to the embodiment;
FIG. 5 is an explanatory diagram of operation waveforms of the plate line decoder / driver of the embodiment.
FIG. 6 is a block diagram illustrating a configuration of a sense amplifier according to the first embodiment;
FIG. 7 is an explanatory diagram of operation waveforms of the sense amplifier according to the first embodiment.
FIG. 8 is an explanatory diagram of a worst case of “0” disturbance in the first embodiment.
FIG. 9 is an explanatory diagram of a worst case of “1” disturbance according to the first embodiment.
FIG. 10 is an explanatory diagram of operation waveforms at the time of data writing according to the second embodiment.
FIG. 11 is an explanatory diagram of an ON state of a write pulse and a non-application state of an inversion pulse during data writing according to the second embodiment;
FIG. 12 is a block diagram illustrating a configuration of a sense amplifier according to a second embodiment;
FIG. 13 is an explanatory diagram of operation waveforms of the sense amplifier according to the second embodiment.
FIG. 14 is an explanatory diagram of the worst disturbance improvement of the second embodiment.
FIG. 15 is an explanatory diagram of a configuration of a cross-point type ferroelectric memory.
FIG. 16 is an explanatory diagram of a configuration of a cross-point type ferroelectric memory.
FIG. 17 is an explanatory diagram of operation waveforms at the time of writing data to the cross-point type ferroelectric memory.
FIG. 18 is an explanatory diagram of a voltage application state at the time of data writing to a cross-point ferroelectric memory.
[Explanation of symbols]
1 word line decoder / driver, 2 plate line decoder / driver, 3 sense amplifier, MU, MU1, MU2 memory unit, WL, WL1 word line, BL, BL1, BL2 bit line, PL, PL1, PL2 plate line

Claims (5)

One electrode includes N (N is a natural number) ferroelectric capacitors in which one electrode is connected to a common node and the other electrode is connected to different plate lines, respectively, in a column direction along a bit line and a row along the plate line. A plurality of memory units arranged in an array in two directions, a plurality of selection transistors having gates connected to word lines and connected between the respective common nodes and the corresponding bit lines, and the word lines. A word line drive unit for selectively selecting a memory unit to be accessed by selectively driving a memory cell, and a plate line drive unit for selectively driving the plate line,
By selectively driving the bit line, the ferroelectric capacitor to be accessed is selected, and at the time of data writing, a first pulse having a write level potential with respect to the selected bit line is written. And a bit line driving means for applying a second pulse having a potential opposite in polarity to the write level potential,
The plate line driving means sets a non-selected plate line in a selected memory unit to an intermediate potential between the first and second pulses during the application period of the first and second pulses. Semiconductor storage device. 2. The semiconductor memory device according to claim 1, wherein the first and second pulses have substantially the same pulse width. The bit line driving means applies the second pulse only when the write data is the same as the write data to the ferroelectric capacitor accessed immediately before in the selected memory unit. The semiconductor memory device according to claim 1, wherein: One electrode includes N (N is a natural number) ferroelectric capacitors in which one electrode is connected to a common node and the other electrode is connected to different plate lines, respectively, in a column direction along a bit line and a row along the plate line. A plurality of memory units arranged in an array in two directions, a plurality of selection transistors having gates connected to word lines and connected between the respective common nodes and the corresponding bit lines, and the word lines. , A word line driving means for selecting a memory unit to be accessed by selectively driving, a plate line driving means for selectively driving the plate line, and an access by selectively driving the bit line. A bit line driving means for selecting the target ferroelectric capacitor, a data writing method in a semiconductor memory device,
At the time of data writing, a first pulse having a writing level potential and a second pulse having a potential having a polarity opposite to the writing level potential are applied to the selected bit line. A data writing method, wherein during the application period of the first and second pulses, the unselected plate line in the selected memory unit is set at an intermediate potential between the first and second pulses. The second pulse is applied only when the write data is the same as the data written to the ferroelectric capacitor accessed immediately before in the selected memory unit. 5. The data writing method according to item 4.

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