JP2004355679A - Memory device, memory control method, and information processing system - Google Patents

Abstract

An object of the present invention is to provide a non-destructive read type memory device using a ferroelectric capacitor, which can prevent deterioration and destruction of data at the time of reading and can improve data reading speed.
According to one embodiment, a memory device stores a binary code according to a polarization state of a ferroelectric capacitor, and applies a read voltage to the ferroelectric capacitor to generate a voltage signal corresponding to the polarization state. A read driving unit that outputs from the memory cell, a voltage holding unit that holds the output voltage signal, a determination unit that monitors the held voltage signal and determines the binary code stored in the memory cell. A switching element inserted in a voltage signal transmission path between the output unit of the memory cell and the voltage holding unit, the switching element is turned on when a voltage signal is output from the memory cell, Is in a non-conducting state until the determination is made.
[Selection diagram] Fig. 1

Description

[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device using a ferroelectric capacitor, and more particularly to a non-destructive read of stored contents.
[0002]
2. Description of the Related Art Conventionally, in a non-destructive read type memory device using a ferroelectric capacitor, reading of stored data is mainly performed by applying a read voltage to a ferroelectric capacitor and generating a read voltage on a bit line. A method is used in which the detected potential is read by a detection circuit to determine whether the data is binary or not (see Patent Document 1).
[0003]
[Patent Document 1] Japanese Patent Application Laid-Open No. 2002-157878
[0004]
[Problems to be solved by the invention]
However, at the time of reading, when the potential of the bit line rises, the voltage of the electrode of the ferroelectric capacitor is reduced by the coupling between the bit line and the electrode of the ferroelectric capacitor and the wiring connected to the electrode. When the read voltage is removed in this state, a voltage opposite to the read voltage is applied to the ferroelectric capacitor, the amount of polarization of the recorded ferroelectric capacitor is reduced, and the data is deteriorated. Or destruction occurs.
[0005]
Until the detection circuit discriminates the binary data and transfers it to the output circuit, reset processing of the memory cell such as removal of the read voltage and precharge of the bit line cannot be performed. This hinders time savings.
In view of the above problems, an object of the present invention is to provide a non-destructive read type memory device using a ferroelectric capacitor, which can prevent data deterioration and destruction at the time of reading and can improve data reading speed. And
[0006]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention provides a memory cell that stores a binary code according to the polarization state of a ferroelectric capacitor, a read voltage applied to the ferroelectric capacitor, and a voltage signal corresponding to the polarization state. A read driving unit that outputs from the memory cell, a voltage holding unit that holds the output voltage signal, a determination unit that monitors the held voltage signal and determines the binary code stored in the memory cell. Wherein a switching element is inserted in a voltage signal transmission path between an output unit of the memory cell and a voltage holding unit, and the switching element is used when a voltage signal is output from the memory cell. It is characterized in that the conductive state is established, and the state is transited to the non-conductive state before the determination unit determines.
[0007]
In order to solve the above-mentioned problem, the present invention is an information processing system including an information processing device for performing information processing, and a memory device for storing a binary code in accordance with an instruction from the information processing device. The processing device transmits a binary code input / output request to the memory device. The memory device stores a binary code according to a polarization state of a ferroelectric capacitor, and receives an output request. A read driving unit that applies a read voltage to the ferroelectric capacitor and outputs a voltage signal according to a polarization state from the memory cell, a voltage holding unit that holds the output voltage signal, and A determination unit that monitors the voltage signal and determines a binary code stored in the memory cell; and a switch inserted in a voltage signal transmission line between an output unit of the memory cell and a voltage holding unit. And switching element, the switching element, and a conductive state when the output of the voltage signal from the memory cell, and a control unit judging unit is a non-conductive state until it is determined.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an information processing system according to an embodiment of the present invention will be described with reference to the drawings.
<1. Configuration>
FIG. 1 is a diagram showing a configuration of a memory system according to an embodiment of the present invention.
[0009]
The memory device 10 is electrically connected to an information processing device 20 that requests processing.
The information processing apparatus 20 is a computer as hardware, and includes a CPU, a ROM, a display, a hard disk, a keyboard, and the like.A computer program is stored in the ROM, and the CPU operates according to the computer program. Implement that function.
[0010]
The memory device 10 includes a memory cell 105 to which a value “0” is assigned as an address and a memory cell 106 to which a value “1” is assigned.
The memory cell 105 stores binary information under the control of the control unit 107.
Similarly, the memory cell 106 stores binary information under the control of the control unit 107.
[0011]
The information processing device 20 transmits a command to request the memory device 10 for data processing.
The commands include a write command and a read command.
The write command is composed of a write instruction, the address, and write data that is one of binary values that require writing.
[0012]
When receiving the write command, the memory device 10 stores the write data in a memory cell corresponding to the address.
The read command includes a read instruction and the address.
When receiving the read command, the memory device 10 reads data stored in a memory cell corresponding to the address and transmits the data to the information processing device 20.
<1.1. Memory device 10>
<1.1.1. Ferroelectric capacitor>
Each of the ferroelectric capacitors 101 to 104 is formed by encapsulating a ferroelectric film with an electrode to form a capacitor. When a voltage is applied, the ferroelectric capacitors 101 to 104 exhibit polarization characteristics having hysteresis.
[0013]
Since the ferroelectric capacitors 101 to 104 have the same polarization characteristics except for individual differences, only the ferroelectric capacitor 101 will be described.
The control unit 107 controls the polarization of the ferroelectric capacitor 101 by applying a voltage to the ferroelectric capacitor by operating a control signal.
FIG. 2 is a diagram illustrating polarization characteristics of the ferroelectric capacitor 101 with respect to voltage application.
[0014]
The hysteresis curve 201 is a hysteresis curve.
When the control unit changes the voltage applied to the ferroelectric capacitor 101 from VCPW to 0, from 0 to −VRST, from −VRST to 0, and from 0 to VRST, the polarization of the ferroelectric capacitor 101 is changed. The state transitions from point 211 to point 212, from point 212 to point 213, from point 213 to point 214, and from point 214 to point 211 along the hysteresis curve 201.
[0015]
A point 212 indicates a value “1” of the binary data, and a point 214 indicates a value “0”.
<1.1.2. Memory Cell>
The memory cell 105 includes ferroelectric capacitors 101 and 102 and field effect transistors (hereinafter, referred to as FETs) 113 and 114.
[0016]
The memory cell 106 includes ferroelectric capacitors 103 and 104, and FETs 115 and 116.
Each of the memory cells 105 and 106 stores a binary value.
The memory cell 105 has a configuration using two ferroelectric capacitors to store binary values. The state in which the memory cell 105 stores a value “1” means that the ferroelectric capacitor 101 has a value of “1”. This is a state in which polarization according to “1” is performed and the ferroelectric capacitor 102 performs polarization according to the value “0”.
[0017]
Similarly, the state where the memory cell 105 stores the value “0” means that the ferroelectric capacitor 101 performs polarization according to the value “0” and the ferroelectric capacitor 102 responds to the value “1”. This is a state in which the polarization is performed.
<1.1.3. Control unit 107>
The control unit 107 transmits signals WL1, WL2, RE, TCP1, TCP2, TRSTT, TRSTB, SS, SAP, and SAN to control writing and reading of data to and from the memory cells 105 and 106. Control.
[0018]
Each signal of WL1, WL2, RE, TCP1, TCP2, TRSTT, TRSTB, SS, SAP, SAN, and BP is a word line 171, a word line 172, a read selection line 173, a plate control line 174, a plate control line 175, respectively. The data is transmitted by a reset control line 176, a reset control line 177, a switch control line 178, a switch control line 179, a switch control line 180, and a signal line 190.
[0019]
VDD, VCPW, and VCPR in FIG. 1 are each 1.8 volts, and VRST is 1.0 volts.
VCPR is not limited to 1.8 volts. The voltage applied to the ferroelectric film at the time of reading is a voltage at which the ferroelectric film returns to the polarization state before reading when the application is stopped after the reading is completed. I just need.
[0020]
The signal CP1 appearing on the plate line 183 changes when the control unit 107 controls RE and TCP1.
Inverter 139 inverts and outputs RE.
When the control unit 107 sets TCP1 to the high level, the FET 131 turns off and the FET 132 turns on, so that CP1 has the ground potential.
[0021]
When the control unit 107 sets TCP1 to low level, the FET 131 is turned on and the FET 132 is turned off, so that CP1 is determined by RE.
When the control unit 107 sets TCP1 to low level and sets RE to high level, the FETs 137 and 138 are turned on and the FETs 135 and 136 are turned off, so that CP1 becomes VCPW.
[0022]
When the control unit 107 sets TCP1 to low level and sets RE to low level, the FETs 137 and 138 are turned off and the FETs 135 and 136 are turned on, so that CP1 becomes VCPR.
The signal CP2 appearing on the plate line 184 changes when the control unit 107 controls RE and TCP2.
[0023]
When the control unit 107 sets TCP2 to the high level, the FET 133 is turned off and the FET 134 is turned on, so that CP2 is at the ground potential.
When the control unit 107 sets TCP2 to low level, the FET 133 is turned on and the FET 134 is turned off, so that CP2 is determined by RE.
When the control unit 107 sets TCP2 to low level and sets RE to high level, the FETs 137 and 138 are turned on and the FETs 135 and 136 are turned off, so that CP2 becomes VCPW.
[0024]
When the control unit 107 sets TCP2 to low level and sets RE to low level, the FETs 137 and 138 are turned off and the FETs 135 and 136 are turned on, so that CP2 becomes VCPR.
The signal RSTT appearing on the reset line 185 changes when the control unit 107 controls TRSTT.
[0025]
When the control unit 107 sets TRSTT to a low level, the FET 141 is turned on and the FET 142 is turned off, so that RSTT becomes VRST.
When the control unit 107 sets TRSTT to a high level, the FET 141 is turned off and the FET 142 is turned on, so that RSTT is at the ground potential.
The signal RSTB appearing on the reset line 186 changes when the control unit 107 controls TRSTB.
[0026]
When the control unit 107 sets TRSTB to a low level, the FET 143 turns on and the FET 144 turns off, so that RSTT becomes VRST.
When the control unit 107 sets TRSTB to a high level, the FET 143 turns off and the FET 144 turns on, so that RSTT becomes the ground potential.
<1.1.4. Sense amplifier 108>
The sense amplifier 108 amplifies and holds the difference between the voltages output to the bit lines 181 and 182, respectively.
[0027]
The sense amplifier 108 has FETs 151 to 156 connected as shown in FIG.
The FETs 152 to 155 are turned on when a voltage equal to or higher than the threshold voltage of 0.65 volt is applied to the gate.
The sense amplifier 108 turns on the FET 156 in a state where the FET 151 is turned on, a voltage higher than the threshold voltage is applied to the bit line 181, and a voltage lower than the threshold voltage is applied to the bit line 182. VDD appears on line 181, and ground potential appears on bit line 182.
<2. Operation>
<2.1. Write operation>
An operation of writing data to the memory cell 105 will be described.
[0028]
FIG. 3 is a diagram illustrating timings of signals controlled by the processing unit 107 when the value “1” is stored in the memory cell 105.
Times t1 to t5 in FIG. 3 are times, and the right side of the drawing indicates a later time.
In FIG. 3, the numbers in parentheses next to the signal names are the numbers shown in FIG. 1, and indicate the signal lines transmitting the signals.
[0029]
The control unit 107 controls WL1, WL2, RE1, TCP1, TCP2, TRSTT, TRSTB, SS, SAP, SAN, and BP.
At a time before t1, the control unit 107 sets RE, TCP1, TCP2, TRST, TRSTB, and SAP to high level, and sets WL1, WL2, SS, SAN, and BP to low level.
[0030]
As a result, SBLT, SBLB, BLTC, and BLBC go low, respectively, and BLTM and BLBM go high.
The voltages applied to the ferroelectric capacitors 101 and 102, VFET and VFEB, are each 0 volt.
At t1, the control unit 107 sets WL1 to a high level.
[0031]
As a result, the FET 113 and the FET 114 are turned on.
At t2, the control unit 107 sets TCP1 to low level.
Since RE is at the high level and TCP1 is at the low level, CP1 becomes VCPW, and the voltage applied to the ferroelectric capacitors 101 and 102 rises to VCPW, and the ferroelectric capacitors 101 and 102 State.
[0032]
At t3, the control unit 107 sets TCP1 to the high level.
Since RE is at the high level and TCP1 is at the high level, CP1 is at the ground potential, the voltage applied to the ferroelectric capacitors 101 and 102 drops to 0 volt, and the ferroelectric capacitors 101 and 102 The state shifts to the state of the point 212.
[0033]
At t4, the control unit 107 sets TRSTB to a low level.
When TRSTB becomes low level, the potential of SBLB rises to VRST, the voltage applied to the ferroelectric capacitor 102 falls to -VRST, and the ferroelectric capacitor 102 shifts to the state at the point 213. .
At t5, the control unit 107 sets TRSTB to a high level.
[0034]
Since RE is at the high level and TCP1 is at the high level, CP1 is at the ground potential, the ferroelectric capacitor 102 is in a state where no voltage is applied, and the ferroelectric capacitor 102 shifts to the state at the point 214.
As described above, after t5, the ferroelectric capacitor 101 indicates the value “1” and the ferroelectric capacitor 102 indicates the value “0”, and thus the memory cell 105 stores the value “1”. It is in the state of doing.
[0035]
FIG. 4 is a diagram illustrating timings of signals controlled by the processing unit 107 when a value “0” is stored in the memory cell 105.
Times t11 to t15 in FIG. 4 are times, and the right side in the drawing indicates a later time.
In FIG. 4, the numbers in parentheses next to the signal names are the numbers shown in FIG. 1, and indicate the signal lines transmitting the signals.
[0036]
At a time before t11, the control unit 107 sets RE, TCP1, TCP2, TRST, TRSTB, and SAP to high level, and sets WL1, WL2, SS, SAN, and BP to low level.
As a result, SBLT, SBLB, BLTC, and BLBC go low, respectively, and BLTM and BLBM go high.
[0037]
The voltages applied to the ferroelectric capacitors 101 and 102, VFET and VFEB, are each 0 volt.
At t11, the control unit 107 sets WL1 to the high level.
As a result, the FET 113 and the FET 114 are turned on.
At t12, the control unit 107 sets TCP1 to low level.
[0038]
Since RE is at the high level and TCP1 is at the low level, CP1 becomes VCPW, and the voltage applied to the ferroelectric capacitors 101 and 102 rises to VCPW, and the ferroelectric capacitors 101 and 102 State.
At t13, the control unit 107 sets TCP1 to the high level.
Since RE is at the high level and TCP1 is at the high level, CP1 is at the ground potential, the voltage applied to the ferroelectric capacitors 101 and 102 drops to 0 volt, and the ferroelectric capacitors 101 and 102 The state shifts to the state of the point 212.
[0039]
At t14, the control unit 107 sets TRSTT to a low level.
When TRSTT goes to a low level, the potential of SBLT rises to VRST, the voltage applied to the ferroelectric capacitor 101 falls to −VRST, and the ferroelectric capacitor 101 shifts to the state at the point 213. .
At t15, the control unit 107 sets TRSTT to a high level.
[0040]
Since RE is at the high level and TCP1 is at the high level, CP1 is at the ground potential, the ferroelectric capacitor 101 is in a state where no voltage is applied, and the ferroelectric capacitor 101 shifts to the state at the point 214.
As described above, after t15, the ferroelectric capacitor 101 indicates the value “0”, and the ferroelectric capacitor 102 indicates the value “1”. Therefore, the memory cell 105 stores the value “0”. It is in the state of doing.
<2.2. Read operation>
Next, an operation of reading data from memory cell 105 will be described.
[0041]
FIG. 5 is a diagram illustrating timings of signals controlled by the processing unit 107 when a value is read from the memory cell 105.
Times t21 to t27 in FIG. 5 are times, and the right side in the drawing indicates a later time.
In FIG. 5, the numbers in parentheses next to the signal names are the numbers shown in FIG. 1, and indicate the signal lines transmitting the signals.
[0042]
The control unit 107 controls WL1, WL2, RE1, TCP1, TCP2, TRSTT, TRSTB, SS, SAP, SAN, and BP.
At time before t21, the control unit 107 sets RE, TCP1, TCP2, TRSTT, TRSTB, and SAP to the high level, and sets WL1, WL2, SS, SAN, and BP to the low level.
[0043]
As a result, SBLT, SBLB, BLTC, and BLBC go low, respectively, and BLTM and BLBM go high.
The voltages applied to the ferroelectric capacitors 101 and 102, VFET and VFEB, are each 0 volt.
At t21, the control unit 107 sets WL1 and SS to the high level.
[0044]
When the WL1 goes high, the FETs 113 and 114 are turned on.
When SS goes high, the FETs 157 and 158 turn on.
When the FET 157 is turned on, the bit line 181 and the bit line 187 are electrically connected, and BLTC rises to VDD.
When the FET 158 is turned on, the bit line 182 and the bit line 188 are electrically connected, and the BLBC rises to VDD.
[0045]
At t22, the control unit 107 sets RE and SAP to low level and sets BP to high level.
When RE goes low, FET 117 and FET 118 are turned off.
When RE goes low, the FET 135 and the FET 136 are turned on, and the FET 137 and the FET 138 are turned off.
[0046]
When the SAP goes low, the FET 151 turns on.
When BP goes high, the FETs 159 and 160 are turned off.
At t23, the control unit 107 sets TCP1 to low level.
When TCP1 goes low, CP1 rises to VCPR.
When CP1 becomes VCPR, the ferroelectric capacitor 101 and the gate capacitance of the read transistor 111 are connected in series, and the voltage of CP1 is changed to the capacitance value of the ferroelectric capacitor 101 and the read transistor 111. Is applied to the gate electrode of the readout transistor 111.
[0047]
Similarly, when CP1 becomes VCPR, the ferroelectric capacitor 102 and the gate capacitance of the read transistor 112 are connected in series, and the voltage of CP1 becomes the capacitance value of the ferroelectric capacitor 102, A voltage divided according to the gate capacitance value of the read transistor 112 is applied to the gate electrode of the read transistor 112.
[0048]
Since the direction of polarization of the ferroelectric film of the ferroelectric capacitor is different between the case where the value “1” is stored in the ferroelectric capacitor and the case where the value “0” is stored, the shape of the hysteresis line is different. Are different, the magnitude of the voltage applied to the gate electrode of the read transistor is different.
Therefore, the gate potential of the reading transistor differs depending on the stored data.
[0049]
Hereinafter, this will be described with reference to FIG.
FIG. 6 is a diagram for explaining the relationship between the respective partial voltages of the ferroelectric capacitor and the gate capacitance of the read transistor when a read voltage is applied to a series circuit in which the ferroelectric capacitor and the read transistor are connected in series. It is.
The horizontal axis is the voltage applied to the ferroelectric capacitor.
[0050]
The vertical axis indicates the respective polarization amounts of the ferroelectric capacitor and the gate capacitance of the read transistor.
A curve 611 is a part of the hysteresis curve 201 in FIG. 2 corresponding to the value “1”.
A curve 612 is a part of the hysteresis curve 201 in FIG. 2 corresponding to the value “0”.
[0051]
The load line 601 is a load line corresponding to the value “1” and indicating the relationship between the voltage applied to the ferroelectric capacitor of the gate capacitance of the read transistor and the amount of polarization of the gate capacitance.
The load line 602 is a load line corresponding to the value “0” and indicating the relationship between the voltage applied to the ferroelectric capacitor and the amount of polarization of the gate capacitance of the read transistor.
[0052]
When the value “1” is stored in the ferroelectric capacitor and CP1 reaches VCPR of 1.8 volts, the distribution between the voltage applied to the ferroelectric capacitor and the voltage applied to the gate electrode is distributed. Is obtained from the intersection 621 of the curve 611 and the load line 601 corresponding to the gate capacitance.
Since the intersection 621 corresponds to about 1.2 volts, the voltage applied to the gate electrode is 0.6 volt, which is the voltage between the intersections 625 and 623.
[0053]
At this time, the voltage applied to the ferroelectric capacitor is 1.2 volts.
Similarly, when the value “0” is stored in the ferroelectric capacitor and CP1 reaches VCPR of 1.8 volts, the voltage applied to the ferroelectric capacitor and the voltage applied to the gate electrode Is determined from the intersection 622 of the curve 612 and the load line 602 corresponding to the gate capacitance.
[0054]
Intersection 622 corresponds to approximately 1.1 volts, so the voltage applied to the gate electrode is 0.7 volts, which is the voltage between intersections 625 and 624.
At this time, the voltage applied to the ferroelectric capacitor is 1.1 volt.
As described above, the signal SBLT on the signal line 191 starts to rise to 0.6 volt, which is the divided voltage.
[0055]
As the potential of SBLT rises, a current starts to flow between the drain and source of the read transistor 111, and BLTC and BLTM start to fall.
Further, the signal SBLB on the signal line 192 starts rising to 0.7 volt, which is the divided voltage.
As the potential of the SBLB rises, a current starts to flow between the drain and the source of the read transistor 112, and the BLBC and the BLBM start falling.
[0056]
The ferroelectric capacitors 101 and 102 show polarizations corresponding to mutually different values among the two values, and the voltages applied to the respective gate electrodes of the read transistor 111 and the read transistor 112 are different.
Therefore, the magnitude of the current flowing through the read transistor 111 is different from the magnitude of the current flowing through the read transistor 112, so that a potential difference is generated between the bit line 181 and the bit line 182.
[0057]
t24 is a time when one of BLTM and BLBM is equal to or higher than the threshold voltage and the other is lower than the threshold voltage.
At t24, the control unit 107 sets SS to a low level and sets SAN to a high level.
When SS goes low, the FETs 157 and 158 are turned off, the bit lines 181 and 187 are electrically disconnected, and the bit lines 182 and 188 are electrically disconnected.
[0058]
When the SAN goes high, the FET 156 turns on.
When the FET 156 is turned on, the sense amplifier 108 operates, and BLTM which is higher than the threshold voltage becomes VDD, and BLBM which is lower than the threshold voltage becomes 0 volt.
The control unit 107 compares BLTM and BLBM, and determines that the value stored in the memory cell 105 is “1” when BLTM is larger than BLBM.
[0059]
Conversely, if BLTM is smaller than BLBM, control unit 107 determines that the value stored in memory cell 105 is “0”.
After determining the value stored in the memory cell 105, the control unit 107 transmits the value to the information processing device 20.
At t25, the control unit 107 sets TCP1 to the high level.
[0060]
When TCP1 goes high, CP1 goes to 0 volts, and SBLT, SBLB, VFET, and VFEB each drop to 0 volts.
At t26, the control unit 107 sets RE and SAP to high level, and sets SAN and BP to low level.
Thereby, SBLT, SBLB, BLTC, BLBC, BLTM, and BLBM are in the state at t21.
[0061]
At t27, the control unit 107 sets WL1 to low level.
When WL1 goes low, the states of WL1, WL2, RE, CP1, CP2, RSTT, RSTB, SS, SAP, SAN, BP, SBLT, SBLB, BLTC, BLBC, BLTM, BLBM, VFET, and VFEB are The state returns to the state before t21 before the execution of the read operation.
<3. Summary>
As described above, when data is read from the memory cell, the FETs 157 and 158 are turned off to electrically disconnect the memory cell and the signal amplifier.
[0062]
Therefore, the operation of judging data on the signal amplifier side and the process after reading on the memory cell side can be performed simultaneously, and the data reading process as a memory device can be performed at high speed.
Further, since the disconnection operation is performed before the data determination operation on the signal amplifier side, the voltage applied to the bit lines 187 and 188 related to the memory cell does not swing between VDD and 0 volt, Noise to a memory cell can be reduced.
[0063]
When VDD is applied to the bit lines 187 and 188, a voltage opposite to the read voltage is applied to the ferroelectric capacitor due to the coupling between the bit line and the signal lines 191 and 192, and the voltage is accumulated in the ferroelectric capacitor. However, the above-described separation operation eliminates such an adverse effect, thereby reducing data retention failure.
<4. Other Modifications>
The present invention is not limited only to the above-described embodiments, and it goes without saying that various changes can be made without departing from the spirit of the present invention.
(1) In the memory cell for storing binary information, two ferroelectric capacitors are used. However, other configurations such as a 1T1C (one transistor and one capacitor) configuration may be used.
[0064]
In this case, the sense amplifier compares the voltage appearing on one bit line instead of the two bit lines with the threshold voltage, and if the voltage appearing on the bit line is equal to or higher than the threshold voltage, the voltage signal on the bit line is changed to VDD. When the voltage appearing on the bit line is lower than the threshold voltage, the voltage signal on the bit line is reduced to the ground potential.
(2) The memory device is not limited to the configuration using two memory cells, but may be a configuration using two or more memory cells.
[0065]
In this case, the number of control lines such as word lines, plate control lines, and reset control lines is increased or decreased based on the number of memory cells.
(3) The transistor switch is not limited to the FET, but may be a switch such as a bipolar transistor that can be electrically connected and disconnected by control.
(4) In the present embodiment, VDD, VCPR, and VCPW are set to 1.8 volts and VRST is set to 1.0 volt. However, the present invention is not limited to these voltage values, and a ferroelectric capacitor is used. Any voltage value can be used for the memory cell so that the function described in the embodiment can be realized.
(5) The information processing device is not limited to a computer, and may be a device using the memory device of the present invention, such as a workstation, a digital broadcast receiver, a digital camera, a mobile phone, or a PDA.
[0066]
【The invention's effect】
(1) A memory device according to the present invention includes a memory cell that stores a binary code according to the polarization state of a ferroelectric capacitor, and a memory cell that applies a read voltage to the ferroelectric capacitor to store a voltage signal corresponding to the polarization state. A read driving unit that outputs from the cell, a voltage holding unit that holds the output voltage signal, and a determining unit that monitors the held voltage signal and determines the binary code stored in the memory cell. A memory device, comprising: a switching element inserted into a voltage signal transmission path between an output unit and a voltage holding unit of the memory cell, wherein the switching element conducts when a voltage signal is output from the memory cell. State, and transitions to the non-conductive state until the determination unit makes the determination.
[0067]
According to this configuration, the switching element is turned off after the voltage signal corresponding to the polarization state of the ferroelectric capacitor output from the memory cell by applying the read voltage is held by the voltage holding unit. The operation of determining the binary code in the determination unit and the operation of stopping the application of the read voltage to the memory cell can be performed in parallel without affecting each other, so that data deterioration and destruction are prevented, and the data read speed is reduced. Can be improved.
[0068]
(2) In the memory device according to (1), the read driver connects the voltage signal transmission line to a ground or a low voltage source after the switching element transits to a non-conductive state, and reads the read voltage. May be stopped.
According to this configuration, the voltage signal transmission line is grounded to eliminate the influence of the coupling between the voltage signal transmission line and the electrode of the ferroelectric capacitor and the wiring connected to the electrode, and then to remove the read voltage. In addition, a voltage opposite to the read voltage is not applied to the ferroelectric capacitor, the amount of polarization of the recorded ferroelectric capacitor does not decrease, and data deterioration or destruction can be prevented.
[0069]
(3) In the memory device of (1), the memory cell is configured to store a 1-bit binary code in a polarization pattern of a pair of ferroelectric capacitors, and the read driving unit includes: A field effect transistor connected in series with the ferroelectric capacitor; and a voltage application unit for applying a read voltage to the series circuit. The voltage holding unit obtains a source voltage of the pair of field effect transistors through the voltage signal transmission path, and based on the voltage, controls the current flowing between the source and the drain. An operating sense amplifier circuit, wherein the determination unit determines a pair of ferroelectric capacitors based on the magnitude of the two voltage signals held by the voltage holding unit. It may be a circuit for determining a binary code corresponding to the polarization pattern.
[0070]
According to this configuration, since the binary code is determined from the magnitude of the two voltage signals, the determination of the binary code is easy, and the ferroelectric capacitor output from the memory cell by applying the read voltage is applied. Since the switching element is turned off after the voltage signal corresponding to the polarization state is held by the voltage holding unit, the operation of determining the binary code in the determination unit and the operation of stopping the application of the read voltage to the memory cell are mutually performed. Can be performed in parallel without affecting the data, so that data deterioration and destruction can be prevented, and the data reading speed can be improved.
[0071]
(4) The memory control method according to the present invention includes a memory cell that stores a binary code according to the polarization state of a ferroelectric capacitor, and a read voltage applied to a ferroelectric capacitor to generate a voltage signal according to the polarization state. A read driving unit that outputs from the memory cell, a voltage holding unit that holds the output voltage signal, a determination unit that monitors the held voltage signal and determines the binary code stored in the memory cell. A memory control method used in a memory device including a switching element inserted in a voltage signal transmission path between an output unit of the memory cell and the voltage holding unit, wherein the switching element is a memory cell A connection step of making a conductive state when a voltage signal is output from the switch, and a disconnecting step of making the switching element in the conductive state non-conductive state by the determination unit. Including the door.
[0072]
According to this configuration, the switching element is turned on, a voltage signal corresponding to the polarization state of the ferroelectric capacitor output from the memory cell by applying a read voltage is held by the voltage holding unit, and then the switching element is turned on. Because of the non-conduction state, the operation of determining the binary code in the determination unit and the operation of stopping the application of the read voltage to the memory cell can be performed in parallel without affecting each other, thereby preventing data deterioration and destruction. The data reading speed can be improved.
[0073]
(5) The information processing system according to the present invention is an information processing system including an information processing device that performs information processing and a memory device that stores a binary code in accordance with an instruction from the information processing device. The processing device transmits a binary code input / output request to the memory device. The memory device stores a binary code according to a polarization state of a ferroelectric capacitor, and receives an output request. A read driving unit that applies a read voltage to the ferroelectric capacitor and outputs a voltage signal according to a polarization state from the memory cell, a voltage holding unit that holds the output voltage signal, and A determination unit that monitors the voltage signal and determines a binary code stored in the memory cell; and a switch inserted in a voltage signal transmission line between an output unit of the memory cell and a voltage holding unit. And switching element, the switching element, and a conductive state when the output of the voltage signal from the memory cell, and a control unit judging unit is a non-conductive state until it is determined.
[0074]
According to this configuration, the information processing apparatus transmits a binary code input / output request, and the memory device turns on the switching element based on the request and outputs a ferroelectric signal from the memory cell by applying a read voltage. After the voltage signal corresponding to the polarization state of the body capacitor is held by the voltage holding unit and the switching element is turned off, the determination unit determines the binary code and stops the application of the read voltage to the memory cell. Can be executed in parallel without affecting each other, so that data deterioration and destruction can be prevented, and the data reading speed can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a memory system according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating polarization characteristics of a ferroelectric capacitor with respect to voltage application.
FIG. 3 is a diagram illustrating timings of signals controlled by a processing unit when a value “1” is stored in a memory cell.
FIG. 4 is a diagram illustrating timings of signals controlled by a processing unit when a value “0” is stored in a memory cell.
FIG. 5 is a diagram illustrating timings of signals controlled by a processing unit when a value is read from a memory cell.
FIG. 6 is a view for explaining a relationship between respective partial voltages of a ferroelectric capacitor and a gate capacitance of a read transistor when a read voltage is applied to a series circuit in which a ferroelectric capacitor and a read transistor are connected in series; It is.
[Explanation of symbols]
10 Memory device
20 Information processing device
101 to 104 Ferroelectric capacitor
105, 106 memory cells
107 control unit
108 sense amplifier
111 to 112 read transistor
113 to 118 Field Effect Transistor (FET)
131 to 138 Field Effect Transistor (FET)
139 Inverter
141 to 144 Field Effect Transistor (FET)
151 to 160 Field Effect Transistor (FET)
171 and 172 word lines
173 Read select line
174, 175 plate control line
176, 177 Reset control line
178 to 180 switch control line
181 and 182 bit lines
183, 184 Plate wire
185, 186 Reset line
187, 188 bit line
190 to 192 signal line
201 Hysteresis curve
601, 602 Load line
611,612 curves
621 to 625 intersection

Claims (5)

A memory cell for storing a binary code according to the polarization state of the ferroelectric capacitor;
A read driver that applies a read voltage to the ferroelectric capacitor and outputs a voltage signal according to the polarization state from the memory cell;
A voltage holding unit that holds the output voltage signal,
A determination unit that monitors the held voltage signal and determines a binary code stored in the memory cell,
A switching element is inserted into a voltage signal transmission path between the output unit of the memory cell and the voltage holding unit, and the switching element is turned on when a voltage signal is output from the memory cell, and the determination unit determines A memory device which is changed to a non-conducting state by the time of execution. 2. The read driver according to claim 1, wherein, after the switching element transits to a non-conducting state, the voltage signal transmission path is connected to a ground or a low voltage source to stop applying the read voltage. A memory device as described. The memory cell is configured to store a 1-bit binary code in a polarization pattern of a pair of ferroelectric capacitors,
The read driver includes a field effect transistor connected in series with each ferroelectric capacitor, and a voltage application unit that applies a read voltage to the series circuit.
When a read voltage is applied, a voltage corresponding to the polarization state of the ferroelectric capacitor is applied to the gate of the field effect transistor, and the current flowing between the source and the drain is controlled.
The voltage holding unit is a sense amplifier circuit that obtains a source voltage of the pair of field effect transistors through the voltage signal transmission path and operates based on the voltage.
2. The circuit according to claim 1, wherein the determination unit is a circuit that determines a binary code corresponding to a polarization pattern of a pair of ferroelectric capacitors from a magnitude of two voltage signals held by the voltage holding unit. A memory device according to claim 1. A memory cell for storing a binary code according to the polarization state of the ferroelectric capacitor;
A read driver that applies a read voltage to the ferroelectric capacitor and outputs a voltage signal according to the polarization state from the memory cell;
A voltage holding unit that holds the output voltage signal,
A determining unit that monitors the held voltage signal and determines a binary code stored in the memory cell;
A memory control method used for a memory device including a switching element inserted in a voltage signal transmission path between an output unit of the memory cell and the voltage holding unit,
A connection step of making the switching element conductive when a voltage signal is output from a memory cell;
A disconnecting step of setting the switching element in the conductive state to a non-conductive state before the determination unit makes a determination. An information processing system comprising: an information processing device that performs information processing; and a memory device that stores a binary code in accordance with an instruction from the information processing device,
The information processing device transmits a binary code input / output request to the memory device,
The memory device,
A memory cell for storing a binary code according to the polarization state of the ferroelectric capacitor;
When receiving an output request, a read driver that applies a read voltage to the ferroelectric capacitor and outputs a voltage signal corresponding to a polarization state from the memory cell,
A voltage holding unit that holds the output voltage signal,
A determining unit that monitors the held voltage signal and determines a binary code stored in the memory cell;
A switching element inserted in a voltage signal transmission path between an output unit and a voltage holding unit of the memory cell;
An information processing system, comprising: a control unit that sets the switching element to a conductive state when a voltage signal is output from the memory cell, and sets a non-conductive state until a determination unit determines.

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