JP2004356254A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device including a high-performance bipolar transistor suitable for high-speed operation including an epitaxial layer is provided.
In a semiconductor device including a bipolar transistor having a base layer formed on a semiconductor substrate by epitaxial growth and using a part of the base layer as a base extraction region, a silicon layer is formed on the base extraction region. A silicide layer was formed on the silicon layer.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device equipped with a bipolar transistor suitable for high-speed operation, and a method for manufacturing the same.
[0002]
[Prior art]
In bipolar integrated circuits in recent years, research and development of a structure including an epitaxial base layer using SiGe (silicon-germanium mixed crystal) has been performed in order to increase the speed and the performance (for example, see Patent Document 1). ).
[0003]
In the bipolar transistor including the epitaxial base layer, a silicide layer is formed in a self-aligned manner on each of the extraction electrodes (emitter, base, and collector) in order to realize higher speed performance.
[0004]
This is because the maximum oscillation frequency (fmax), which serves as a guide for the transistor characteristics, is dramatically improved by reducing the resistance of the electrode, particularly the base extraction resistance.
[0005]
Here, an example of the related art will be described with reference to FIG.
[0006]
FIG. 11 is a completed cross-sectional view of a semiconductor device on which a conventional bipolar transistor is mounted, and is manufactured by the following steps.
[0007]
First, an N ⁺ buried region 110 is formed in an NPN / transistor formation region on a silicon substrate 100, and thereafter, an N− epitaxial layer 120 and a field oxide film 200 are formed, and a P ⁺ element isolation region (not shown) is formed. The plug-in layer 300 is formed.
[0008]
Then, after an oxide film having a thickness of several nm is formed by thermal oxidation, a first SiO ₂ film 400 is formed on the entire surface by a CVD method. Thereafter, a region for forming an epitaxial base layer (hereinafter, referred to as “SiGe epilayer”) made of SiGe (silicon-germanium mixed crystal) is formed in the first SiO ₂ film 400 by using a resist pattern.
[0009]
Next, a SiGe epi layer 500 is formed in the epitaxial base layer forming region, and the SiGe epi layer 500 is processed by dry etching using a resist pattern. The SiGe epi layer 500 has a three-layer structure including a buffer layer made of only silicon, a SiGe layer, and a cap layer made of only silicon from the bottom.
[0010]
Thereafter, a second SiO ₂ film 600 is formed on the entire surface by CVD to separate the emitter and base regions, and a region for forming the emitter is opened by dry etching using a resist pattern.
[0011]
Next, a polysilicon (Poly-Si) layer 700 as a polycrystalline semiconductor layer is formed on the entire surface, arsenic (As) is ion-implanted, and As in the polysilicon is activated by annealing. Is diffused from the substrate to form an emitter layer.
[0012]
After that, dry etching of the polycrystalline silicon layer 700 is performed using a resist pattern to form an emitter of the NPN transistor.
[0013]
Further, by using the resist pattern, the base region and the second SiO ₂ film 600, the collector region is processed SiO ₂ film 400, 600 of the first and second to open the area for silicide formation. Thereafter, after forming a metal film, a heat treatment is performed to form a silicide layer 800 in an emitter, base, and collector extraction electrode region in a self-aligned manner. Thereafter, a metal electrode, a multilayer wiring, a protective film and the like are formed to obtain a semiconductor device.
[0014]
[Patent Document 1]
JP 2002-289834 A
[Problems to be solved by the invention]
Through the above-described steps, a semiconductor device mounted with a bipolar transistor including an epitaxial base layer using SiGe (silicon-germanium mixed crystal) is manufactured. However, such a conventional manufacturing method still has the following problems. Was left.
[0016]
That is, there is a maximum cutoff frequency (f _T max) as a guideline indicating the transistor characteristics. It is very important that the impurity profile in the vertical direction is made shallow, that is, shallow.
[0017]
As described above, in the structure using the SiGe epi layer as the base, the emitter-base junction is formed closer to the surface than the SiGe epi layer. For this purpose, a silicon epitaxial layer (hereinafter referred to as “Si epi layer”) as the cap layer is formed after forming a SiGe epi layer for an emitter-base junction. Here, the emitter - base junction becomes important to optimize the maximum cut-off frequency (f T _max) to form the SiGe epitaxial / Si epitaxial interface. Therefore, to make the impurity profile in the vertical direction shallow means to make the emitter, base and collector regions shallow, so that it is necessary to reduce the thickness of the Si epi layer where the emitter-base junction is formed.
[0018]
On the other hand, a SiGe and a polycrystalline silicon layer are formed on the first SiO ₂ film simultaneously with the formation of the SiGe epi layer, and a silicide layer for reducing the base resistance is formed in this region. The maximum oscillation frequency (fmax), which serves as a guide for high-speed operation, is improved.
[0019]
With the miniaturization of the element, cobalt that can avoid the thin wire effect is used as the metal used for silicide formation. However, in the silicide reaction of cobalt, cobalt diffuses into silicon and reacts with silicon. Therefore, a silicon polycrystalline layer sufficient for silicide formation is required.
[0020]
The problem here is that it is important to optimize the maximum cutoff frequency (f _T max) by reducing the thickness of the Si epi layer, but the silicide for improving the maximum oscillation frequency (fmax) is important. The point is that it is necessary to make the Si epi layer (silicon polycrystalline layer) thicker for the formation.
[0021]
In addition, when there is not enough silicon polycrystalline layer necessary for silicide formation, if the reaction reaches the SiGe layer, the reaction is rate-determined by germanium (Ge), and the problem such as an increase in resistance becomes significant. On the other hand, if the thickness of cobalt is reduced to avoid this, it is known that a sufficient silicide layer is not formed, and a problem such as a fine wire effect (resistance rise / variation) occurs.
[0022]
The present invention solves such a problem, and provides a semiconductor device mounted with a bipolar transistor having a structure including an epitaxial base layer using SiGe (silicon-germanium mixed crystal) for high speed and high performance, and the semiconductor device. The purpose of the present invention is to provide a manufacturing method.
[0023]
Means for Solving the Invention
In order to solve the above problem, according to the present invention, there is provided a semiconductor device including a bipolar transistor in which a base layer is formed on a semiconductor substrate by epitaxial growth and a part of the base layer is used as a base extraction region. A silicon layer was formed on the base extraction region, and a silicide layer was formed on the silicon layer.
[0024]
In the present invention, the base layer is made of SiGe (silicon-germanium mixed crystal).
[0025]
According to the third aspect of the present invention, there is provided a semiconductor device in which a base layer made of SiGe (silicon-germanium mixed crystal) is formed on a semiconductor substrate by epitaxial growth, and a bipolar transistor having a part of the base layer as a base extraction region is provided. In the manufacturing method, a silicon layer is formed on the base extraction region, and a silicide layer is formed on the silicon layer.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention is directed to a semiconductor device including a bipolar transistor in which a base layer is formed on a semiconductor substrate by epitaxial growth and a part of the base layer is used as a base extraction region, wherein a silicon layer is formed on the base extraction region. And a silicide layer formed on the silicon layer.
[0027]
With this configuration, shallow (Shallow) of longitudinal impurity profile for optimizing the maximum cut-off frequency _(f T max), and a silicide is formed in a thickness necessary for improving the maximum oscillation frequency (fmax) As a result, the base resistance can be reduced, and a high-quality semiconductor device can be obtained. Here, the silicon layer includes at least a layer containing silicon in addition to a layer composed of only silicon.
[0028]
As described above, a method for manufacturing a semiconductor device in which a silicon layer is formed on the base layer and a silicide layer is formed on the silicon layer may include the following steps.
[0029]
That is, (a) a step of forming a first insulating film on the semiconductor substrate, and (b) a region for forming an epitaxial layer by patterning the first insulating film is formed. Forming a polycrystalline semiconductor layer on the first insulating film at the same time as forming a single crystal semiconductor layer serving as a base layer; and (c) forming a second polycrystalline semiconductor layer on the single crystal semiconductor layer and the polycrystalline semiconductor layer. Depositing an insulating film and processing it into a pattern for forming an emitter; and (d) forming a first silicon layer on the single-crystal semiconductor layer and the polycrystalline semiconductor layer and the first insulating film to be the silicon layer. Depositing the polycrystalline semiconductor layer and processing the first polycrystalline semiconductor layer until the second insulating film is exposed; and (e) removing the second insulating film to form an emitter formation region. Opening, and (f) opening Depositing a third insulating film in the emitter region, and (g) depositing a second polycrystalline semiconductor layer on the third insulating film and removing the same by etching to open an emitter forming region. (H) forming a third polycrystalline semiconductor layer in the emitter formation region and forming an emitter extraction electrode; and (i) the entire surface of the semiconductor substrate including the first polycrystalline semiconductor layer serving as a base extraction electrode And (j) causing a silicidation reaction between the first polycrystalline semiconductor layer and the metal film by heat treatment to form a base extraction electrode made of a silicide layer. is there.
[0030]
In depositing the first polycrystalline semiconductor layer to be the silicon layer, a non-selective epitaxial technique can be used. Preferably, the silicide layer is made of cobalt silicide.
[0031]
According to the above method, the base extraction region of the bipolar transistor can be formed by the base layer made of a polycrystalline semiconductor layer and the silicon layer, that is, the first polycrystalline semiconductor layer. The crystal layer (consisting of the base layer and the first polycrystalline semiconductor layer) becomes thicker, so that the base resistance can be further reduced.
[0032]
Further, when the base layer is made of SiGe (silicon-germanium mixed crystal), the bipolar transistor can be operated at high speed, and a high-speed, high-performance semiconductor device can be obtained.
[0033]
Hereinafter, embodiments of a semiconductor device according to the present invention and a manufacturing method thereof will be described more specifically with reference to the drawings.
[0034]
FIG. 1 is a completed cross-sectional view of the semiconductor device according to the present embodiment, and FIGS. 2 to 10 are explanatory views showing the manufacturing steps.
[0035]
As shown in FIG. 1, the semiconductor device according to the present embodiment has a semiconductor substrate in which an N-type epitaxial layer (hereinafter referred to as an N-epi layer 11) is formed on the upper surface of a P-type silicon substrate 10 by vapor phase growth. 1 is used.
[0036]
Then, a bipolar transistor including a base B, an emitter E, and a collector C is formed in the transistor formation region, and the base region is formed on the upper surface of the N-epi layer 11 with a SiO ₂ oxide film as the first insulating film 9. An opening is formed, a silicon-germanium mixed crystal layer is formed on the base region opening by epitaxial growth to provide an epitaxial base layer 3, and an emitter layer E1 is formed at a predetermined position on the epitaxial base layer 3. ing.
[0037]
Then, a polysilicon layer 4 which is a polycrystalline semiconductor layer is formed on the epitaxial base layer 3 except for the emitter layer E1, and this is used as a base extraction electrode portion 40, and a silicide layer is formed on the polysilicon layer 4. 5 are formed. Reference numeral 6 denotes an N ⁺ buried region, and 7 denotes a plug-in layer. The plug-in layer 7 is formed to reach the N ⁺ buried region 6 and serves as a collector electrode take-out region. Reference numeral 8 denotes a field oxide film.
[0038]
As described above, since the polysilicon layer 4 as a silicon layer is formed on the epitaxial base layer 3 and the silicide layer 5 is formed on the polysilicon layer 4, the maximum cutoff frequency (f _T max) is obtained. ) To realize a shallow impurity profile in the vertical direction for optimizing) and to reduce the base resistance by forming the silicide layer 5 with a thickness necessary for improving the maximum oscillation frequency (fmax). It becomes possible and it becomes a high quality semiconductor device.
[0039]
Hereinafter, a method for manufacturing the semiconductor device will be described in detail with reference to FIGS.
[0040]
First, in the first step, as shown in FIG. 2, a Sb gas phase using Sb ₂ O ₃ at 1200 ° C. is formed in a transistor formation region on a silicon substrate 10 having a P-type substrate surface orientation of (100). An N ⁺ buried region 6 is formed by diffusion. Thereafter, an N-epi layer 11 of 1 to 5 Ωcm and 0.5 to 1.5 μm is grown and formed on the silicon substrate 10 to form the semiconductor substrate 1.
[0041]
Next, after the entire surface of the semiconductor substrate 1 is thermally oxidized with a thickness of 50 nm, a Si ₃ N ₄ film (not shown) is formed with a thickness of 100 nm by a CVD method. After this _{the Si} 3 _{N 4} film on forming a pattern for exposing the active region, to remove the _{the Si} 3 _{N 4} film and the thermal oxide film (SiO ₂ film), the thickness by steam oxidation of from 1,000 to 1,050 ° C. of A field oxide film 8 having a thickness of 300 to 800 nm is formed. Then, after removing the Si ₃ N ₄ film, boron (B) ion implantation in the range of 100 to 720 keV, 1 × 10 ^{12 to} 5 × 10 ¹³ / cm ² is performed a plurality of times, and the P ⁺ element isolation region ( (Not shown). In addition, as the N-type impurity, phosphorus ion implantation in the range of 150 to 720 keV and 1 × 10 ^{13 to} 5 × 10 ¹⁵ / cm ² is performed a plurality of times to form the plug-in layer 7 in the transistor formation region.
[0042]
Next, after forming an oxide film having a thickness of 7 to 10 nm by thermal oxidation at 800 to 900 ° C., a first SiO ₂ film 9 having a thickness of 100 to 200 nm is formed on the entire surface by a CVD method.
[0043]
As shown in FIG. 3, in the second step, an opening is formed in the epitaxial base layer forming region 30 by using a resist pattern in the first SiO ₂ film 9, and the epitaxial base layer forming region 30 is doped with boron. The epitaxial base layer 3 is formed from the obtained SiGe (silicon germanium mixed crystal).
[0044]
In the third step, as shown in FIG. 4, an SiO ₂ film is formed as a _second insulating film 92 on the entire surface of the semiconductor substrate 1 by a CVD method, and an emitter E is formed by dry etching using a resist pattern. Auxiliary patterns are formed. Note that the thickness of the second insulating film 92 is about 100 to 200 nm.
[0045]
Next, in a fourth step, as shown in FIG. 5, a first polysilicon layer 4 is formed on the entire surface with a thickness of 300 to 500 nm, and the second insulating film 92 is exposed by a CMP method until the second insulating film 92 is exposed. It is processed, and then is recessed from the surface of the SiO ₂ film forming the second insulating film 92 by dry etching. The thickness of the processed polysilicon layer 4 is about 50 to 100 nm. When the first polysilicon layer 4 is formed, boron or gallium is doped.
[0046]
In the fifth step, as shown in FIG. 6, a silicon nitride (Si ₃ N ₄ ) film 12 having a thickness of 100 to 200 nm is formed, and the SiO 2 serving as the second insulating film 92 is formed in the same manner as in the fourth step. Processing is performed by the CMP method until the surface of the _two films is exposed, and the second insulating film 92 is etched away by wet processing. The processed silicon nitride (Si ₃ N ₄ ) film 12 has a thickness of about 50 to 100 nm. The silicon nitride film 12 becomes an auxiliary film for forming a step for preventing a short circuit between the emitter and the base when the silicide layer 5 is formed later.
[0047]
As shown in FIG. 7, in the sixth step, a SiO ₂ film serving as the third insulating film 93 is formed on the entire surface of the substrate with a thickness of about 30 to 100 nm by a CVD method.
[0048]
Next, as shown in FIG. 8, in a seventh step, a second polysilicon layer, which is a polycrystalline semiconductor layer, is formed with a thickness of about 100 nm, and is etched by a dry etching technique to form an emitter region. Here, by etching back the entire surface, a sidewall film 42 of the second polysilicon layer is formed. An opening can be formed.
[0049]
As shown in FIG. 9, in the eighth step, the third polysilicon layer 43 is formed on the entire surface of the substrate is a polycrystalline semiconductor layer of 300～50Nm, the silicon nitride _(Si 3 _{N 4)} film 12 is exposed Until the process is performed, it is processed by CMP. Here, the third polysilicon layer 43 is doped with arsenic (As) or phosphorus (P).
[0050]
Then, as shown in FIG. 10, in a ninth step, the silicon nitride (Si ₃ N ₄ ) film 12 is etched away by wet processing.
[0051]
Thereafter, after forming cobalt on the entire surface of the substrate, heat treatment is performed to form a silicide layer 5 in a self-aligned manner in the extraction electrode regions of the emitter E, base B, and collector C, and a silicon oxide (SiO ₂ ) film is formed by LPCVD. After the formation of 13, the metal contacts 14, 15, 16 and the multilayer wirings 17, 18, 19, and a protective film (not shown) are formed, and a semiconductor device in which a transistor having a shape shown is processed is formed.
[0052]
Incidentally, the silicide layer 5 is formed through the following steps.
[0053]
First, after removing the natural oxide film on the surfaces of the first polysilicon layer 4 and the third polysilicon layer 43, cobalt and titanium nitride are formed by sputtering, and then heat treatment is performed to react the cobalt with silicon. A layer (CoSi) is formed. Thereafter, unreacted cobalt and titanium nitride adhering to the silicon oxide film other than the first polysilicon layer 4 and the third polysilicon layer 43 are removed, and then a mixed solution of ammonia and hydrogen peroxide is used. The cobalt is removed using. Thereafter, a heat treatment is performed again to form a cobalt silicide layer (silicide layer 5).
[0054]
As described above, according to the semiconductor device and the method of manufacturing the same according to the present embodiment, a bipolar transistor having a structure including an epitaxial base layer using SiGe (silicon-germanium mixed crystal) for high speed and high performance is provided. It is possible to realize means for making, and to provide a high-performance semiconductor device using these.
[0055]
As described above, the present invention has been described through the embodiments, but the present invention is not limited to the above embodiments. For example, an integrated circuit does not necessarily consist of a bipolar transistor alone, but can be applied to a semiconductor integrated circuit in which a capacitor, a resistor, a MOS transistor, and the like are mixed, and can be appropriately applied if it is within the spirit of the present invention. can do.
[0056]
【The invention's effect】
The present invention is implemented in the form described above, and has the following effects.
[0057]
(1) In the semiconductor device according to the first aspect of the present invention, there is provided a semiconductor device including a bipolar transistor in which a base layer is formed on a semiconductor substrate by epitaxial growth and a part of the base layer is used as a base extraction region. Forming a silicon layer on the silicon layer, and forming a silicide layer on the silicon layer, a shallow impurity profile in the vertical direction for optimizing the maximum cutoff frequency (f _T max); and It is possible to reduce the base resistance by forming silicide with a thickness necessary to improve the maximum oscillation frequency (fmax), and a high-quality semiconductor device having excellent performance can be obtained. Further, the thickness of the polycrystalline layer in the base electrode formation region is increased, so that the base resistance can be further reduced.
[0058]
(2) According to the second aspect of the present invention, since the base layer is made of SiGe (silicon-germanium mixed crystal), a semiconductor device including a transistor that operates at high speed can be provided.
[0059]
(3) According to the third aspect of the present invention, a bipolar transistor is formed on a semiconductor substrate by forming a base layer made of SiGe (silicon-germanium mixed crystal) by epitaxial growth and using a part of the base layer as a base extraction region. In the method for manufacturing a semiconductor device, a silicon layer is formed on the base extraction region, and a silicide layer is formed on the silicon layer. Accordingly, shallow (Shallow) of longitudinal impurity profile for optimizing the maximum cut-off frequency _(f T max), and to form a silicide with a thickness necessary for improving the maximum oscillation frequency (fmax) Base The resistance can be reduced, and a high-quality semiconductor device that operates at high speed and has excellent performance can be provided.
[Brief description of the drawings]
FIG. 1 is a completed sectional view of a semiconductor device according to the present embodiment.
FIG. 2 is an explanatory diagram showing a manufacturing process of the semiconductor device according to the present embodiment.
FIG. 3 is an explanatory diagram illustrating a manufacturing process of the semiconductor device according to the present embodiment;
FIG. 4 is an explanatory diagram illustrating a manufacturing process of the semiconductor device according to the present embodiment;
FIG. 5 is an explanatory diagram illustrating a manufacturing process of the semiconductor device according to the present embodiment;
FIG. 6 is an explanatory diagram illustrating a manufacturing process of the semiconductor device according to the present embodiment;
FIG. 7 is an explanatory diagram illustrating a manufacturing process of the semiconductor device according to the present embodiment;
FIG. 8 is an explanatory diagram illustrating a manufacturing process of the semiconductor device according to the present embodiment;
FIG. 9 is an explanatory diagram illustrating a manufacturing process of the semiconductor device according to the present embodiment;
FIG. 10 is an explanatory diagram illustrating a manufacturing process of the semiconductor device according to the present embodiment;
FIG. 11 is a completed sectional view of a conventional semiconductor device.
[Explanation of symbols]
Reference Signs List 1 semiconductor substrate 3 epitaxial base layer 4 polycrystalline silicon layer (silicon layer)
5 Silicide layer

Claims (3)

A semiconductor device comprising a bipolar transistor having a base layer formed on a semiconductor substrate by epitaxial growth and having a part of the base layer as a base extraction region.
A semiconductor device, wherein a silicon layer is formed on the base extraction region, and a silicide layer is formed on the silicon layer. 2. The semiconductor device according to claim 1, wherein the base layer is made of SiGe (silicon germanium mixed crystal). A method of manufacturing a semiconductor device, comprising: forming a base layer made of SiGe (silicon-germanium mixed crystal) on a semiconductor substrate by epitaxial growth; and providing a bipolar transistor having a part of the base layer as a base extraction region.
A method for manufacturing a semiconductor device, comprising: forming a silicon layer on the base extraction region; and forming a silicide layer on the silicon layer.

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