JP2004304332A - Oscillation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillation circuit which oscillates a desired frequency regardless of surrounding states and provides a stable oscillation frequency with a satisfactory response. <P>SOLUTION: The oscillation circuit has an oscillation means (11) for oscillating in a frequency matching the control voltage, a compensation means (12) for generating a compensation signal for compensating the control voltage so that the oscillation frequency of the oscillation means (11) becomes a prescribed frequency and an averaging means (13) for supplying an average value between a peak value and a bottom value of the compensation signal generated by the compensation means (12) as control voltage for the oscillation means (11). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an oscillation circuit, and more particularly, to an oscillation circuit that oscillates at a desired frequency regardless of surrounding conditions.
[0002]
[Prior art]
In recent years, the frequency band of usable radio waves has been narrowed with the development of communication technology. For this reason, high precision is required for the frequency of the oscillation output of the oscillation circuit mounted on the communication device or the like. However, a vibrator used in an oscillation circuit has a so-called temperature characteristic in which the characteristic of vibration changes according to temperature.
[0003]
For this reason, in the oscillation circuit, correction is performed so that the oscillation frequency does not change due to the change in the oscillation frequency of the vibrator (for example, see Patent Document 1).
[0004]
[Patent Document 1]
JP-A-10-290118 (FIG. 1, paragraphs 0040 to 0054)
[0005]
[Problems to be solved by the invention]
However, in the conventional oscillation circuit, the output analog signal of the temperature sensor is converted into digital data, and the converted digital data is subjected to arithmetic processing to remove noise and the like, so that the circuit configuration becomes complicated. With it, it becomes expensive. In addition, since the arithmetic processing is performed, there is a problem that a response to a rise at the time of startup is poor, and further, it is not possible to rapidly respond to a sudden change in an analog signal from a sensor. In addition, if control is directly performed using analog signals without converting to digital data, frequency fluctuations due to voltage noise cannot be ignored, and this is not suitable for high precision.
[0006]
The present invention has been made in view of the above points, and has as its object to provide an oscillation circuit capable of obtaining a stable oscillation frequency in a state of good responsiveness.
[0007]
[Means for Solving the Problems]
According to the present invention, an oscillating means (11) oscillating at a frequency corresponding to a control voltage and a correction signal for correcting the control voltage so that the oscillating frequency of the oscillating means (11) becomes a predetermined frequency are generated. A correcting unit (12), and an averaging unit (13) that supplies an average value of a peak value and a bottom value of the correction signal generated by the correcting unit (12) as a control voltage of the oscillation unit (11). It is characterized by having.
[0008]
Further, according to the present invention, the averaging means (13) includes a peak value detection means (41) for detecting a peak value of the correction signal from the correction means (12), and the correction from the correction means (12). A bottom value detecting means for detecting a bottom value of the signal; and an average value of a peak value detected by the peak value detecting means and a bottom value detected by the bottom value detecting means. And an average output means (43).
[0009]
According to the present invention, the average value of the peak value and the bottom value of the correction signal for correcting the oscillation frequency of the oscillation means (11) to a predetermined frequency is supplied as the control voltage of the oscillation means (11). Thereby, the noise component superimposed on the correction signal can be removed. Thereby, the accuracy of the oscillation frequency of the oscillation means (11) can be improved.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a circuit configuration diagram of an embodiment of the present invention.
[0011]
The oscillating circuit 1 of this embodiment is configured to include a voltage-controlled oscillating circuit 11, a correction circuit 12, and an averaging circuit unit 13.
[0012]
The voltage-controlled oscillation circuit 11 is configured by, for example, a voltage-controlled crystal oscillation circuit, and has a configuration in which the output oscillation frequency changes according to the control voltage.
[0013]
FIG. 2 shows an example of a block diagram of the voltage controlled oscillation circuit 11.
[0014]
The voltage controlled oscillation circuit 11 includes an oscillator 21, an inverter 22, a feedback resistor Rf, DC cut capacitors C1, C2, variable capacitance diodes Cv1, Cv2, and a buffer amplifier 23.
[0015]
The oscillator 21 is composed of, for example, a crystal oscillator, and is connected to the inverter 22 in parallel. The feedback resistor Rf is connected to the inverter 22 in parallel. A variable capacitance diode Cv1 is connected to one end of a parallel circuit composed of the crystal oscillator 21, the inverter 22, and the feedback resistor Rf via a capacitor C1 with a reverse polarity. Further, a variable capacitance diode Cv2 is connected to the other end of the parallel circuit including the crystal oscillator 21, the inverter 22, and the feedback resistor Rf via the capacitor C2 with the opposite polarity. The control voltage Vcnt is applied to the anode of the variable capacitance diode Cv1 via the input resistance Rin1, and the control voltage Vcnt is applied to the anode of the variable capacitance diode Cv2 via the input resistance Rin2. The capacitance of the variable capacitance diodes Cv1 and Cv2 changes according to the control voltage Vcnt. As a result, the capacitance component of the oscillation circuit viewed from the crystal oscillator 21 changes, so that oscillation occurs at an oscillation frequency corresponding to the control voltage.
[0016]
The other end of the parallel circuit of the crystal oscillator 21, the inverter 22, and the feedback resistor Rf is connected to the output terminal Tout via the buffer amplifier 23. The buffer amplifier 23 amplifies an oscillation signal generated at the other end of the parallel circuit of the crystal oscillator 21, the inverter 22, and the feedback resistor Rf, and supplies the amplified signal to the output terminal Tout.
[0017]
At this time, the oscillation frequency of the voltage controlled oscillation circuit 11 has a so-called temperature characteristic that changes according to the temperature. Generally, the oscillation frequency f is
f = αT ＾ 3 + βT + γ (1)
It is known to have a temperature characteristic approximated by
[0018]
The correction circuit 12 is a circuit for correcting the temperature characteristics of the oscillation frequency, reducing the temperature dependence of the oscillation frequency, and outputting a constant oscillation frequency.
[0019]
The correction circuit 12 includes a reference voltage generation circuit 31, a temperature sensor 32, a cubic function generation circuit 33, conductance amplifiers 34 to 36, and an adder 37. The reference voltage generation circuit 31 is a circuit that generates a reference voltage Vref. The γ component of equation (1) is adjusted by the reference voltage generation circuit 31.
[0020]
The temperature sensor 32 is a circuit that is driven by a reference voltage Vref that is stable with respect to the temperature generated by the reference voltage generation circuit 31 and that generates an output that is a linear function with respect to temperature. The β component of equation (1) is adjusted by the output of the temperature sensor 32.
[0021]
Further, the cubic function generating circuit 33 is a circuit that changes the output of the temperature sensor 32 into a cubic function and outputs the result. The α component of equation (1) is adjusted by the output of the cubic function generation circuit 33.
[0022]
The reference voltage Vref generated by the reference voltage generation circuit 31 is supplied to the adder 37 after gain adjustment by the conductance amplifier 34. The output of the temperature sensor 32 is supplied to an adder 37 after gain adjustment by a conductance amplifier 35. The output of the cubic function generating circuit 33 is supplied to an adder 37 after gain adjustment by a conductance amplifier 36.
[0023]
The adder 37 adds the output of the conductance amplifier 34, the output of the conductance amplifier 35, and the output of the conductance amplifier 36, and outputs the sum. The output of the adder 37 is a signal that corrects the frequency variation according to the temperature in the equation (1). The output of the adder 37 is supplied to the averaging circuit unit 13.
[0024]
FIG. 3 shows a block diagram of the averaging circuit unit 13.
[0025]
The averaging circuit unit 13 includes a peak value detection circuit 41 for detecting a peak value of the correction signal from the correction circuit 12, a bottom value detection circuit 42 for detecting a bottom value of the correction signal from the correction circuit 12, and a peak value detection circuit. The averaging circuit 43 outputs an average value of the peak value detected by the circuit 41 and the bottom value detected by the bottom value detection circuit 42.
[0026]
The peak value detection circuit 41 includes an amplifier 51, an output transistor Q1, a peak value holding capacitor C1, a current source 52, a buffer amplifier 53, and a resistor R1.
[0027]
The correction signal from the correction circuit 12 is supplied to a non-inverting input terminal of the amplifier 51. The charging potential of the peak value holding capacitor C1 is applied to the inverting input terminal of the amplifier 51. The amplifier 51 outputs a signal corresponding to the difference between the correction signal and the potential of the peak value holding capacitor C1.
[0028]
The output of the amplifier 51 is supplied to the base of the output transistor Q1. The output transistor Q1 is formed of an NPN transistor, and supplies a current corresponding to the output of the amplifier 51 to the peak value holding capacitor C1. The amplifier 51 and the output transistor Q1 constitute a voltage follower type amplifier circuit.
[0029]
For example, when the potential of the correction signal becomes higher than the potential of the peak value holding capacitor C1 due to noise or the like, the output potential of the amplifier 51 increases, and the emitter current of the output transistor Q1 increases. As a result, the charge of the peak value holding capacitor C1 increases, and the charging potential of the peak value holding capacitor C1 increases.
[0030]
When the charging potential of the peak value holding capacitor C1 becomes about the potential of the correction signal, that is, about the peak value of the correction signal, the output transistor Q1 is turned off, and charging of the peak value holding capacitor C1 is stopped. The peak value holding capacitor C1 is connected to the current source 52, is gradually discharged by the current source 52 even after the charging is stopped, and the potential gradually decreases from the peak value. The charged potential of the peak value holding capacitor C1 is supplied to the averaging circuit 43 via the buffer amplifier 53 and the resistor R1.
[0031]
The bottom value detection circuit 42 includes an amplifier 61, an output transistor Q2, a bottom value holding capacitor C2, a current source 62, a buffer amplifier 63, and a resistor R2.
[0032]
The correction signal from the correction circuit 12 is supplied to a non-inverting input terminal of the amplifier 61. The charging potential of the bottom value holding capacitor C2 is applied to the inverting input terminal of the amplifier 61. The amplifier 61 outputs a signal corresponding to the difference between the correction signal and the potential of the bottom value holding capacitor C2.
[0033]
The output of the amplifier 61 is supplied to the base of the output transistor Q2. The output transistor Q2 is composed of a PNP transistor, and draws a current corresponding to the output of the amplifier 61 from the bottom value holding capacitor C2.
[0034]
For example, when the potential of the correction signal becomes smaller than the potential of the bottom value holding capacitor C2, the output potential of the amplifier 61 decreases, and the current drawn into the emitter of the output transistor Q2 increases. As a result, the charge of the bottom value holding capacitor C1 decreases, and the charging potential of the bottom value holding capacitor C1 decreases.
[0035]
When the charging potential of the bottom value holding capacitor C2 becomes about the potential of the correction signal, that is, about the bottom value of the correction signal, the output transistor Q2 is turned off, and discharging from the bottom value holding capacitor C2 is stopped. The bottom value holding capacitor C2 is connected to the current source 62. After the discharge is stopped, the capacitor C2 is gradually charged by the current source 62, and the potential gradually increases from the bottom value. The charged potential of the bottom value holding capacitor C2 is supplied to the averaging circuit 43 via the buffer amplifier 63 and the resistor R2.
[0036]
Note that the buffer amplifiers 53 and 63 are circuits for preventing the charge of the peak value holding capacitor C1 and the bottom value holding capacitor C2 from being discharged, and are not limited thereto, and are not limited to the source-follower type. May be used.
[0037]
Further, during the hold operation, the output transistors Q1 and Q2 act as an emitter follower circuit for the peak value holding capacitor C1 and the bottom value holding capacitor C2. Charging time is short. Therefore, the rise of the correction signal is not delayed at the time of startup, and the time required for the oscillation output of the oscillation circuit 11 to reach a desired frequency is not delayed at the time of startup, and the peak value holding capacitor C1 and the bottom value holding capacitor C2 are not delayed. Does not affect the starting characteristics.
[0038]
The averaging circuit 43 includes an adder 71 and an amplifier 72. The adder 71 is supplied with the peak value output from the peak value detection circuit 41 and the bottom value output from the bottom value detection circuit 42. The adder 71 outputs a signal obtained by adding the peak value output from the peak value detection circuit 41 and the bottom value output from the bottom value detection circuit 42. The output of the adder 71 is supplied to the amplifier 72. The amplifier 72 outputs the output of the adder 71 by 倍 times.
[0039]
At this time, if the peak value output from the peak value detection circuit 41 is Vp and the bottom value Vb output from the bottom value detection circuit 42 is:
The output Vout of the amplifier 72 is
Vout = (Vp + Vb) / 2
And this corresponds to the average value of the peak value and the bottom value. Note that the averaging method of the averaging circuit unit 13 is not limited to the above method. For example, the signal from the correction circuit unit 12 is divided by resistors R1 and R2, and the output is divided by a buffer amplifier. It may be a format that is output via a PC.
[0040]
FIG. 4 is a diagram illustrating the operation of the averaging circuit unit 13. Here, in order to make the operation easy to understand, two kinds of sine wave signals are used instead of noise components. In FIG. 4, the solid line indicates the correction signal, the one-dot chain line indicates the output of the peak value detection circuit 41, the two-dot chain line indicates the output of the bottom value detection circuit 42, and the broken line indicates the average value.
[0041]
By averaging the peak value indicated by the one-dot chain line in FIG. 4 and the bottom value indicated by the two-dot chain line, an output substantially indicated by a broken line in FIG. 4 can be obtained. This is a signal obtained by removing the noise component on the high frequency side from the correction signal shown by the solid line in FIG.
[0042]
As described above, according to the present embodiment, since the noise component included in the correction signal can be removed by averaging the peak value and the bottom value, an arbitrary cutoff frequency can be set.
[0043]
According to the present embodiment, the hold time of the peak value or the bottom value can be easily adjusted by adjusting the currents of the current sources 52 and 62.
[0044]
【The invention's effect】
As described above, according to the present invention, the average value of the peak value and the bottom value of the correction signal for correcting the oscillating frequency of the oscillating means to be a predetermined frequency is supplied as the control voltage of the oscillating means. And the noise component of the correction signal can be removed, and the accuracy of the oscillation frequency of the oscillation means can be improved.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an embodiment of the present invention.
FIG. 2 is a block diagram of a voltage controlled oscillation circuit 11;
FIG. 3 is a block diagram of an averaging circuit unit 13;
FIG. 4 is an explanatory diagram of an operation of the averaging circuit unit 13;
[Explanation of symbols]
REFERENCE SIGNS LIST 1 oscillation circuit 11 voltage-controlled oscillation circuit, 12 correction circuit, 13 averaging circuit circuit section 21 oscillator, 22 inverter, 23 output amplifier 31 reference voltage generation circuit, 32 temperature sensor, 33 cubic function generation circuit 34, 35, 36 Amplifier, 37 adder 41 peak value detection circuit, 42 bottom value detection circuit, 43 averaging circuit 51, 61 amplifier, 52, 62 current source, 53, 63 buffer amplifier 71 adder, 72 amplifier Q1, Q2 output transistor,
C1 Peak value holding capacitor, C2 Bottom value holding capacitor R1, R2 Resistance

Claims (5)

Oscillating means for oscillating at a frequency according to the control voltage;
Correction means for generating a correction signal for correcting the control voltage so that the oscillation frequency of the oscillation means is a predetermined frequency,
An oscillating circuit comprising averaging means for supplying an average value of a peak value and a bottom value of the correction signal generated by the correction means as a control voltage of the oscillating means. The averaging means, peak value detection means for detecting the peak value of the correction signal from the correction means,
Bottom value detection means for detecting a bottom value of the correction signal from the correction means,
2. The oscillation circuit according to claim 1, further comprising an average value output unit that outputs an average value of a peak value detected by the peak value detection unit and a bottom value detected by the bottom value detection unit. The peak value detection means, a capacitor that holds a charge according to the peak value of the correction signal,
Charge and discharge control means for charging and discharging the capacitor according to the difference between the correction signal and the potential of the capacitor,
3. The oscillation circuit according to claim 2, further comprising peak value output means for outputting a voltage corresponding to the potential of said capacitor. The bottom value detection means, a capacitor that holds a charge according to the bottom value of the correction signal,
Charge and discharge control means for charging and discharging the capacitor according to the difference between the correction signal and the potential of the capacitor,
4. The oscillation circuit according to claim 2, further comprising a bottom value output unit that outputs a voltage corresponding to a potential of the capacitor. The average value output unit, an addition unit that adds the peak value detected by the peak value detection unit and the bottom value detected by the bottom value detection unit,
5. The oscillation circuit according to claim 2, further comprising: means for halving the addition result by said addition means.

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