JP2004317691A - Mask group, method for manufacturing mask group and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decrease the manufacture cost of a mask group comprising a plurality of mask sheets having a plurality of kinds of layers arranged in one sheet. <P>SOLUTION: In the mask group comprising a plurality of mask sheets having a plurality of kinds of layers arranged in one sheet, the layers are allocated in each mask sheet M1 to M3 corresponding to the sequence according to prescribed specifications of the layers for the manufacture of the mask. The method for manufacturing the mask group includes: a process of sequencing a plurality of kinds of layers according to the prescribed specifications for the manufacture of the mask; and a process of constituting the plurality of mask sheets M1 to M3 by allocating a plurality of layers in one mask sheet corresponding to the sequence of the layers. The mask group is used for exposure in the method for manufacturing a semiconductor device. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a mask group including a plurality of masks each having a plurality of types of layers arranged thereon, a method of manufacturing the mask group, and a method of manufacturing a semiconductor device using the mask group.
[0002]
[Prior art]
When a device such as a semiconductor device or a liquid crystal display device is manufactured by a photolithography process, a pattern image of an optical mask or a reticle is reduced to, for example, about 1/4 through a projection optical system, and a photosensitive material (photoresist or the like) is formed. There is used a projection exposure apparatus for exposing a substrate (a wafer, a glass plate, etc.) on which is coated. As the degree of integration of semiconductor elements and the like increases, the resolution required for a projection optical system used in a projection exposure apparatus has been increasing.
[0003]
Also, the pattern of the optical mask used has been miniaturized, and in the 90 nm generation, a pattern of 0.3 μm or less has been used even on the optical mask. In order to manufacture such a high-precision optical mask, it is necessary to use a more expensive drawing apparatus and inspection apparatus.
[0004]
Furthermore, with the increase in the number of patterns, the improvement in throughput of the mask drawing apparatus cannot keep up, and the productivity of the mask has been greatly reduced. Therefore, the manufacturing cost of the mask is inevitably rising.
[0005]
Conventionally, only one layer of a pattern (chip) of one process (eg, an element isolation layer, a gate layer, a wiring layer, a contact hole layer, etc.) is arranged on one mask. In order to suppress this, Patent Literature 1 introduces a concept including a plurality of steps in one optical mask.
[0006]
By using this technique, for example, if a semiconductor that has conventionally been manufactured using 30 optical masks is manufactured using 5 masks (6 layers are arranged on one mask), the cost of the mask is simply 1 unit. / 6, which can be greatly reduced. However, since the exposure area is reduced, the efficiency of processing one wafer is reduced. Therefore, the method of using one photomask including a plurality of processes is effective when only a small number of wafers are required, such as when manufacturing a small amount or verifying a design circuit.
[0007]
[Patent Document 1]
Japanese Utility Model Laid-Open No. 5-8935 [0008]
[Problems to be solved by the invention]
However, in general, mask configurations for fabricating devices use masks of various specifications. For example, the specifications of a mask are completely different between a critical layer (for example, a gate layer) that requires high accuracy in line width and uniformity and a rough layer (for example, a pad layer) that does not require much accuracy. Here, the higher the mask specification, the higher the mask manufacturing cost.
[0009]
[Means for Solving the Problems]
The present invention has been made to solve such a problem. That is, according to the present invention, in a mask group including a plurality of masks each having a plurality of types of layers arranged thereon, each mask is provided with an order in accordance with a predetermined specification in mask manufacturing for each layer. Each layer is assigned correspondingly.
[0010]
Further, the present invention provides a step of assigning an order in accordance with a predetermined specification in mask manufacturing in a plurality of types of layers, and allocating a plurality of layers to one mask in accordance with the order assigned to each layer. And forming a plurality of masks. The present invention is also a method for manufacturing a semiconductor device using the above mask group for exposure.
[0011]
In the present invention, in a mask group in which a plurality of types of layers are arranged on one mask, the layers are assigned to the masks in an order corresponding to a predetermined specification in mask manufacturing for each layer. (1) Since a layer having close manufacturing specifications is arranged collectively on one mask, manufacturing corresponding to the manufacturing specifications can be performed for each mask.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram illustrating a mask group according to the present embodiment, and FIG. 2 is a schematic diagram illustrating a conventional mask group. That is, the mask group according to the present embodiment includes a plurality of masks (three masks M1 to M3 in FIG. 1), and a plurality of types of layers are arranged on each of the masks M1 to M3. Here, the layer is, for example, an exposure pattern used for forming a certain layer (gate layer or wiring layer) in a semiconductor device. In addition, the mask described in this embodiment includes a reticle.
[0013]
In the example shown in FIG. 1, four types of layers are arranged on one mask. In each layer, four identical layers are arranged to form four chips with the same exposure. The types of layers arranged on the masks M1 to M3 and the number of the same layers arranged are not limited thereto.
[0014]
Here, in the conventional mask group shown in FIG. 2, four masks M′1 to M′4 corresponding to the layers A to D are supported by one mask M ′. The same mask is assigned. That is, A to D correspond to the exposure order. For example, when there are 12 layers corresponding to the 12 exposure orders of A to L, the first to fourth layers of A to D in the exposure order are set to one sheet. Assigned to the mask, the next fifth to eighth E to H layers are assigned to another mask, and the next ninth to twelfth IL layers are assigned to another mask. We are trying to assign.
[0015]
On the other hand, in the mask group of the present embodiment shown in FIG. 1, when allocating twelve types of layers A to L to three masks M1 to M3, the layers are not arranged in the order of exposure but in the order of specifications in mask manufacturing. Assigned.
[0016]
For example, it is assumed that the layers A to L have different specifications in mask manufacturing (for example, the minimum line width of a pattern, the allowable line width variation of a pattern, the positional accuracy of a pattern, and the allowable size of dust) for each layer. . For example, a layer for forming a gate has strict specifications (accuracy), and a layer for forming a pad has loose specifications. It should be noted that there are actually layers having the same specifications, but in the present embodiment, description will be made assuming that all the specifications are different.
[0017]
Here, it is assumed that the specifications of each layer are A → E → D → L → F → G → B → H → C → I → J → K in order of high accuracy (strict specifications). According to the order of this specification, in the example shown in FIG. 1, four layers of A, E, D, and L are assigned to one mask M1 in order of strict specifications, and four layers of F, G, B, and H are next ordered in strict order. Layers are assigned to one mask M2, and then four layers of C, I, J, and K are assigned to one mask M3 in order of strictness.
[0018]
In this mask group, a mask M1 to which four layers of A, E, D, and L are assigned is a Critical Layer, and a mask M2 to which four layers of F, G, B, and H are assigned is a Middle Layer. The mask M3 to which the next four layers of C, I, J, and K are assigned is grouped as a Rough Layer, the Critical Layer mask M1 is manufactured by the most accurate mask manufacturing apparatus, and the Middle Layer mask M2 is manufactured. The mask M3 of the Rough Layer is manufactured by a mask manufacturing apparatus with a lower accuracy than the normal accuracy.
[0019]
Note that this grouping is not necessarily three, and may be set according to the ranking of the mask pattern forming accuracy by the mask manufacturing apparatus. By using a mask group based on such layer assignment, each of the masks M1 to M3 can be formed in accordance with the specifications of the mask manufacturing, and the cost for manufacturing the mask as a whole mask group can be reduced.
[0020]
For example, in the conventional mask group, if 12 layers A to L are allocated to three masks in the same manner as above, layers A to D are allocated to the first mask in correspondence with the exposure order, and E to H is assigned to the second mask, and I to L are assigned to the third mask.
[0021]
Assuming that these layers have the same specification order as the present embodiment, the first mask includes layers A and D corresponding to the Critical Layer, a layer B corresponding to the Middle Layer, and a layer C corresponding to the Rough Layer. It becomes a mixed state. In order to manufacture such a mask, the layers A and D cannot be formed according to the specifications unless the mask is manufactured with the most accurate mask manufacturing apparatus in accordance with the critical layer. In other words, it is necessary to use a mask manufacturing apparatus that meets the strictest specifications among the layers.
[0022]
Similarly, in the conventional second mask, four layers E to H are allocated. However, since there is a layer E corresponding to the Critical Layer, the second mask is also the mask with the highest accuracy. Must be manufactured on manufacturing equipment.
[0023]
In the conventional third mask, four layers I to L are allocated. However, since there is a layer L corresponding to the critical layer, the third mask is also manufactured with the most accurate mask. Must be manufactured on equipment. That is, in the conventional mask group, all the masks must be manufactured by the mask manufacturing apparatus with the highest accuracy, which causes an increase in manufacturing cost.
[0024]
In the present embodiment, as described above, since the assignment is performed in the order according to the mask manufacturing specification of each layer, one mask is manufactured by the most accurate mask manufacturing apparatus, and one mask is manufactured by the normal accuracy mask manufacturing apparatus. One mask can be manufactured by a mask manufacturing apparatus with an accuracy lower than the normal accuracy, and one mask can be manufactured according to the required accuracy, and the mask manufacturing cost of the entire mask group can be reduced.
[0025]
Therefore, if a semiconductor device is manufactured by performing exposure using the mask group of the present embodiment, the manufacturing cost of the semiconductor device itself can be reduced.
[0026]
Here, a method for manufacturing a mask group according to the present embodiment will be described. First, a process of assigning the order of the specifications in mask production for each layer is performed. That is, in order to assign the order of specifications to each layer, reference is made to the design data (specification data) of the pattern of each layer, the minimum line width of the pattern, the allowable line width variation of the pattern, the positional accuracy of the pattern, and the allowable amount of dust. Comprehensively digitize using one or more of the sizes.
[0027]
In addition, priorities may be assigned to the minimum line width of the pattern, the allowable line width variation of the pattern, the positional accuracy of the pattern, and the allowable size of dust, which are listed as specifications, and the order may be assigned according to the priority order. In addition, in a layer in which the order cannot be determined, the assignment to the mask may be determined due to a relationship with another layer or manufacturing convenience.
[0028]
Next, layers are allocated to each mask based on the number of layers to be arranged on one mask in accordance with the order given to each layer. For example, when four types of layers are arranged on one mask, four layers are selected in the order described above, and each of the four layers is sequentially assigned to each mask.
[0029]
Then, a mask group is completed by forming a pattern of each mask to which a layer is assigned by a mask manufacturing apparatus. Here, if the masks are grouped according to the pattern formation accuracy (rank) of the mask manufacturing apparatus and the patterns are formed by the corresponding mask manufacturing apparatus, the cost of mask manufacturing can be reduced.
[0030]
FIG. 3 is a schematic diagram illustrating another embodiment. In this example, the configuration of the mask group when the layers 1 to 32 are in the order of the specification in this order is shown. Here, the critical layer has two masks M11 to M12, the middle layer has two masks M21 to M22, and the right layer has four masks M31 to M34.
[0031]
Therefore, layers 1-4, 5-8 are assigned to the two masks M11-M12 of the critical layer, respectively, and the layers 9-9, 13-16 are assigned to the two masks M21-M22 of the middle layer. Are allocated, and layers 17 to 20, 21 to 24, 25 to 28, and 29 to 32 are allocated to the four masks M31 to M34 of the Rough Layer, respectively.
[0032]
In this way, by assigning to the masks according to the order of specifications for each layer and by setting each mask into a group corresponding to the pattern formation accuracy (rank) of the mask manufacturing apparatus, the layers constituting each mask can be assigned. It is possible to reduce the cost of the entire mask group by manufacturing the mask in accordance with the specifications and the rank of the mask manufacturing apparatus.
[0033]
Here, a specific example will be described. There are three ranks of mask manufacturing equipment. Correspondingly, three groups of "Critical Layer", "Middle Layer", and "Rough Layer" are assumed to correspond to masks, and the required number of masks for a device is 32. It is assumed that “Critical Layer” has eight layers, “Middle Layer” has eight layers, and “Rough Layer” has sixteen layers. Further, the price ratio for manufacturing each mask is 10: 5: 1.
[0034]
First, when a conventional mask group is applied and eight layers are arranged on one mask, four masks are required. Assuming that “Critical Layer” is arranged on each mask, if even one chip has a layer of Critical specification arranged on one mask, the mask needs to satisfy the Critical specification. A "Critical Layer" mask is required and costs 4 × 10 = 40.
[0035]
On the other hand, if a mask configuration is used for each specification as in the present embodiment, two “Critical Layers”, two “Middle Layers”, and four “Rough Layers” are provided, and the mask cost is (10 × 1) + (5 × 1) + (1 × 2) = 17, and the cost can be reduced by 50% or more.
[0036]
【The invention's effect】
As described above, the present invention has the following effects. That is, by using a mask having a plurality of circuit patterns in one sheet, the number of masks required for manufacturing one semiconductor device can be reduced, and the mask cost can be significantly reduced. Further, by allocating the layer arrangement according to the specifications in manufacturing the mask, it is possible to further reduce the cost, and it is also possible to reduce the cost of the semiconductor device manufactured using this mask group.
[Brief description of the drawings]
FIG. 1 is a schematic diagram illustrating a mask group according to the present embodiment.
FIG. 2 is a schematic diagram illustrating a conventional mask group.
FIG. 3 is a schematic diagram illustrating a mask group according to another embodiment.
[Explanation of symbols]
M1 mask, M2 mask, M3 mask

Claims (11)

In a mask group including a plurality of masks each including a plurality of types of layers arranged therein,
A group of masks, wherein each layer is assigned to each of the masks in an order according to a predetermined specification in mask production for each of the layers. 2. The mask group according to claim 1, wherein the predetermined specification in manufacturing the mask is a minimum line width of the pattern. 2. The mask group according to claim 1, wherein the predetermined specification in manufacturing the mask is an allowable line width variation of a pattern. 2. The mask group according to claim 1, wherein the predetermined specification in manufacturing the mask is a positional accuracy of a pattern. 2. The mask group according to claim 1, wherein the predetermined specification in manufacturing the mask is an allowable size of dust. A step of assigning an order according to a predetermined specification in mask manufacturing in a plurality of types of layers,
Forming a plurality of masks by assigning a plurality of layers to one mask in accordance with the order given to each of the layers. 7. The method according to claim 6, wherein the predetermined specification in manufacturing the mask is a minimum line width of the pattern. 7. The method of manufacturing a mask group according to claim 6, wherein the predetermined specification in manufacturing the mask is an allowable line width variation of a pattern. 7. The method for manufacturing a mask group according to claim 6, wherein the predetermined specification in manufacturing the mask is positional accuracy of a pattern. 7. The method according to claim 6, wherein the predetermined specification in manufacturing the mask is an allowable size of dust. A method of manufacturing a semiconductor device, comprising a step of performing exposure with a mask group including a plurality of masks each including a plurality of types of layers arranged thereon.
A method of manufacturing a semiconductor device, wherein each of the masks uses a mask to which each layer is assigned according to an order in accordance with a predetermined specification in mask manufacturing for each layer.

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