JP2004335505A - Multilayered printed wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the electrical connectability or reliability of a multilayered printed wiring board by hindering the flow of a conductive bump in a substrate at the time of mounting an electronic component, such as the IC chip etc., or performing heat cycle tests. <P>SOLUTION: The multilayered wiring board is constituted by laminating two or more circuit boards, each of which is obtained by forming via holes, by packing conductors in non-through holes formed in an insulating substrate having a conductor layer on one surface or conductor layers on both surfaces, and forming conductive bumps on the via holes upon another. Then the circuit boards are connected to each other through the conductive bumps, and solder bumps are formed on the conductor layer of the outermost circuit board. The conductive bumps contain Cu. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

式中、Ａは錯化剤（キレート剤として作用）、ｎは配位数を示す。
【０１１８】
上式に示されるように、発生した第一銅錯体は、酸の作用で溶解し、酸素と結合して第二銅錯体となって、再び銅の酸化に寄与する。本発明において使用される第二銅錯体は、アゾール類の第二銅錯体がよい。この有機酸−第二銅錯体からなるエッチング液は、アゾール類の第二銅錯体および有機酸（必要に応じてハロゲンイオン）を、水に溶解して調製することができる。
このようなエッチング液は、たとえば、イミダゾール銅（ＩＩ）錯体 １０重量部、グリコール酸 ７重量部、塩化カリウム ５重量部を混合した水溶液から形成される。
【０１１９】
（１０） 次いで、導電性バンプ２４を含んだ絶縁性基材１０の表面から保護フィルムを剥離させた後、その絶縁性基材１０の表面に樹脂接着剤２６を塗布する（図２（ｆ）参照）。
このような樹脂接着剤は、例えば、絶縁性基材１０の導電性バンプ２４を含んだ表面全体または導電性バンプ２４を含まない表面に塗布され、乾燥化された状態の未硬化樹脂からなる接着剤層として形成される。この接着剤層は、取扱が容易になるため、プレキュアしておくことが好ましく、その厚さは、５〜５０μｍの範囲が望ましい。
【０１２０】
前記接着剤層２６は、有機系接着剤からなることが望ましく、有機系接着剤としては、エポキシ樹脂、ポリイミド樹脂、熱硬化型ポリフェノレンエーテル（ＰＰＥ）、エポキシ樹脂と熱可塑性樹脂との複合樹脂、エポキシ樹脂とシリコーン掛脂との複合樹脂、ＢＴレジンから選ばれる少なくとも１種の樹脂であることが望ましい。
有機系接着剤である未硬化樹脂の塗布方法は、カーテンコータ、スピンコータ、ロールコータ、スプレーコート、スクリーン印刷などを使用できる。また、接着剤層の形成は、接着剤シートをラミネートすることによってもできる。
【０１２１】
上記（８）〜（１０）の工程にしたがって作製された片面回路基板Ｂは、絶縁性基材１０の一方の表面に導体回路を有し、他方の表面には半田めっきからなる導電性バンプ２４を有し、さらに導電性バンプ２４を含んだ絶縁性基材１０の表面に他の絶縁性基材との接着用の接着剤層２６、または、銅箔との接着用の接着剤層３２を有して形成される。
【０１２２】
（１１） 上記片面回路基板Ａの導電性バンプ側の面を下方に向け、その面に対して片面回路基板の複数枚、例えばＢ１およびＢ２の２枚を同一方向に積層すると共に、最も外側の片面回路基板Ｂ２の導電性バンプ側の表面に対して、表面粗さが３μｍのマット面を有する厚さが３〜４０μｍの銅箔３０を、そのマット面を対向させた状態で積層し、加熱温度１５０〜２５０℃、圧力１〜１０ＭＰａの条件のもとで、加熱プレスすることによって、片面回路基板Ａと、複数枚の片面回路基板Ｂ１およびＢ２と、銅箔３０とを一体化し、多層化する（図３参照）。
【０１２３】
この場合には、最も外側（下方）に位置する片面回路基板Ｂ２の導電性バンプ側の表面には、接着剤層２６に代えて、半硬化状態を保持された銅箔接着用の樹脂接着剤層３２が形成され、この樹脂接着剤層３２を介して銅箔３０が加熱プレスされる。
【０１２４】
この加熱プレスは、より好ましくは、減圧下において行なわれ、未硬化状態の樹脂接着剤層２６および樹脂接着剤層３２を硬化することによって、片面回路基板Ａと片面回路基板Ｂ１、Ｂ２との間、および片面回路基板Ｂ２と銅箔３０との間が接着される。
その際、銅箔３０は硬化した接着剤層３２を介して片面回路基板Ｂ２の絶縁性基材１０に接着されると共に、銅箔３０と半田バンプ２４とが電気的に接続される。
【０１２５】
（１２）さらに、上記（１１）において一体化された回路基板の最上層の片面回路基板Ａの銅箔１２と、最も外側の片面回路基板Ｂ２の銅箔３０を、エッチング処理することによって、導体回路３６および導体回路３８（共にバイアホールランドを含む）を形成する（図３参照）。
【０１２６】
このエッチング処理工程においては、先ず、片面導体回路Ａの銅箔１２および片面回路基板Ｂ２に圧着された銅箔３０の表面に、それぞれ感光性ドライフィルムレジストを貼付した後、所定の回路パターンに沿って露光、現像処理してエッチングレジストを形成し、エッチングレジスト非形成部分の金属層をエッチングして、バイアホールランドを含んだ導体回路３６および導体回路３８を形成する。
【０１２７】
（１３） 次に、上記（１１）の工程において一体化され、（１２）において両面に回路形成された積層体の導体回路３８側の面に対して、２枚の片面導体回路Ｂ３、Ｂ４の導電性バンプ側の面を対向させた状態で積層させ、加熱温度１５０〜２５０℃、圧力１〜１０ＭＰａの条件のもとで、加熱プレスして、片面回路基板Ａ、片面回路基板Ｂ１、Ｂ２、銅箔３０、片面回路基板Ｂ３、Ｂ４とを一体化する（図４参照）。
【０１２８】
（１４） 次に、最も外側の片面回路基板ＡおよびＢ４の表面にソルダーレジスト層３７および３９をそれぞれ形成する。この場合、回路基板ＡよびＢ４の外表面全体にソルダーレジスト組成物を塗布し、その塗膜を乾燥した後、この塗膜に、開口部を描画したフォトマスクフィルムを載置して露光、現像処理することにより、導体回路３６および２８のバイアホール直上に位置する導電性パッド部分を露出させた開口４０および４２をそれぞれ形成する。
【０１２９】
（１５） 上記（１４）の工程で得られたソルダーレジスト３７および３９の開口４０および４２からバイアホール直上に露出した半田パッド部分に、半田バンプ４４、導電性ボール４６あるいは導電性ピンを配設する前に、各半田パッド部上に「ニッケル−金」からなる金属層５０を形成することが好ましい。
【０１３０】
このニッケル層の厚みは、１〜７μｍが望ましく、金層の厚みは０．０１〜０．０６μｍであることが望ましい。この理由は、ニッケル層は、厚すぎると抵抗値の増大を招き、薄すぎると剥離しやすいからである。一方金層は、厚すぎるとコスト増になり、薄すぎると半田体との密着効果が低下するからである。
【０１３１】
（１６） 上記半田パッド部上に設けたニッケル−金からなる金属層５０上に、半田体を供給し、この半田体の溶融・固化によって半田バンプ４４を形成し、あるいは導電性ボール４６または導電性ピンを導電性接着剤を用いて半田パッド部に接合して、多層回路基板６０が形成される。
【０１３２】
上記半田体の供給方法としては、半田転写法、印刷法、ボール搭載法などを用いることができる。
ここで、半田転写法は、プリプレグに半田箔を貼合し、この半田箔を開口部分に相当する箇所のみを残してエッチングすることにより、半田パターンを形成して半田キャリアフィルムとし、この半田キャリアフィルムを、基板のソルダーレジスト開口部分にフラックスを塗布した後、半田パターンがパッドに接触するように積層し、これを加熱して転写する方法である。
【０１３３】
一方、印刷法は、パッドに相当する箇所に開口を設けた印刷マスク（メタルマスク）を基板に載置し、半田ペーストを印刷して加熱処理する方法である。このような半田バンプを形成する半田としては、Ｓｎ／Ａｇ、Ｓｎ／Ｐｂ、Ｓｎ／Ｚｎ、Ｓｎ／Ｓｂ半田などが使用でき、それらの融点は、積層される各回路基板間を接続する導電性バンプの融点よりも低いことが望ましい。
【０１３４】
上記導電性ボール４６やＴピンをパッド上に接合する導電性接着剤としては、上記導電性バンプの融点Ｔ１および半田バンプの融点Ｔ２よりも融点の高いＳｎ／Ｓｂ系半田、Ｓｎ／Ａｇ系半田、Ｓｎ／Ａｇ／Ｃｕ系半田、Ｓｎ／Ｃｕ系半田などを用いることが好ましい。
【０１３５】
上記（１）〜（１６）の工程にしたがう実施形態によれば、本発明にかかる多層化回路基板６０は、片面回路基板Ａと２枚の片面回路基板Ｂ１、Ｂ２を同一方向に積層すると共に、最も外側に位置する片面回路基板Ｂ２の導電性バンプ側の表面に対して、マット面が対向するように銅箔３０を対向配置させた状態で、加熱プレスすることによって、片面回路基板同士を接着すると共に銅箔３０を片面回路基板Ｂ２に圧着して多層化した後、片面回路基板Ａの銅箔１２と片面回路基板Ｂ２に圧着された銅箔３０とをエッチング処理して、それぞれ導体回路３６および３８を形成し、さらに、片面回路基板Ｂ２の導体回路３８側の面に対して、片面回路基板Ｂ３，Ｂ４の導電性バンプ側の面を対向配置させた状態で、加熱プレスすることによって多層化したが、このような実施形態の他に、以下の▲１▼〜▲２▼に記載したような実施形態を採用することもできる。
【０１３６】
▲１▼ 同一材料で形成された３枚の片面回路基板Ｂ１〜Ｂ３を同一方向に向けて順次積層すると共に、最も外側に位置する片面回路基板Ｂ３の導電性バンプ側の表面に対して、マット面を有する銅箔３０を対向配置させた状態で、真空加熱プレスにより片面回路基板同士を接着すると共に銅箔３０を片面回路基板Ｂ３に圧着して多層化する。そのような多層化の後、最上層の片面回路基板Ｂ１にエッチング保護フィルム２５を貼付した状態で、エッチング処理を施して、片面回路基板Ｂ３に圧着された銅箔３０を選択的にエッチングして所定パターンを有する導体回路３８を形成する。
その後、片面回路基板Ｂ３の導体回路３８側の面に対して、片面回路基板Ｂ４，Ｂ５の導電性バンプ側の面を対向配置させた状態で、真空加熱プレスすることによって多層化する。
【０１３７】
▲２▼ 図６（ａ）に示すように、片面回路基板Ａの導電性バンプ側の表面に塗布すべき接着剤層２６に代えて、銅箔接着用の樹脂接着剤３６を塗布し、半硬化状態を保持した片面回路基板Ａに対して、マット面を有する銅箔３０を対向配置させ、加熱プレスによって、片面回路基板Ａに銅箔３０を圧着した後（図６（ｂ）参照）、エッチング処理を施して、片面回路基板Ａの表裏両面にそれぞれ所定パターンを有する導体回路６２および６４を形成して、両面回路基板Ｃを形成する（図６（ｃ）参照）。その後、同一方向に向けて順次積層された片面回路基板Ｂ１〜Ｂ２、および片面回路基板Ｂ３〜Ｂ４を両面回路基板Ｃの表裏面に対して積層した状態で、真空加熱プレスによって片面回路基板Ｂ１、Ｂ２と、両面回路基板Ｃと、片面回路基板Ｂ３、Ｂ４とを一体化する。
【０１３８】
上述した実施の形態では、５枚の片面回路基板または４枚の片面回路基板と１枚の両面回路基板とを積層一体化して、５層に多層化したが、４層以下でも、６層以上でも必要に応じた多層化が可能である。
【０１３９】
【実施例】
（実施例１‐１）
（１） まず、多層化回路基板を構成する片面回路基板を製作する。この回路基板は、エポキシ樹脂をガラスクロスに含潰させてＢステージとしたプリプレグと、銅箔とを積層して加熱プレスすることにより得られる片面銅張積層板を出発材料として用いる。
【０１４０】
この絶縁性基材１０の厚さは７５μｍ、銅箔１２の厚さは１０μｍであり、この積層板の銅箔形成面と反対側の表面に、厚みが１０μｍの粘着剤層を有し、かつフィルム自体の厚みが１２μｍであるようなＰＥＴフィルム１４をラミネートする。
【０１４１】
（２） ついで、ＰＥＴフィルム１４上から炭酸ガスレーザ照射を行って、ＰＥＴフィルム１４および絶縁性基材１０を貫通して銅箔１２に至るバイアホール形成用開口１６を形成し、さらにその開口１６内を酸素プラズマ放電によってデスミア処理した。または、過マンガン酸、クロム酸等の酸化剤もしくは塩酸、硫酸等の酸などに浸漬させる湿式のデスミア処理を行ってもよい。
【０１４２】
この実施例においては、バイアホール形成用の開口の形成には、三菱電機製の高ピーク短パルス発振型炭酸ガスレーザ加工機を使用し、全体として厚さ２０μｍのＰＥＴフィルムを樹脂面にラミネートした、基材厚７５μｍのガラス布エポキシ樹脂基材に、マスクイメージ法でＰＥＴフィルム側からレーザビーム照射して１００穴／秒のスピードで、１５０μｍφのバイアホール形成用の開口を形成した。
【０１４３】
（３） デスミア処理を終えた絶縁性基材１０の銅箔貼付面にＰＥＴフィルム１５を貼り付け、以下のような条件で、銅箔１２をめっきリードとする電解銅めっき処理を施して、開口１６内に電解銅めっき１８を充填して充填バイアホール２０を形成した。その際、電解銅めっきは開口１６の上部にわずかに露出したので、サンダーベルト研磨およびバフ研磨によって露出部分を除去して平坦化してもよい。
【０１４４】
〔電解銅めっき水溶液〕
硫酸 ：１８０±５ ｇ／ｌ
硫酸銅 ：７８±２ ｇ／ｌ
添加剤（アトテックジャパン製、商品名：カパラシドＧＬ）：１ ｍｌ／ｌ
〔電解めっき条件〕
電流密度 ：２±０．１ Ａ／ｄｍ^２
時間 ：３０±２ 分
温度 ：２５±１ ℃
【０１４５】
（４） さらに、以下のような条件で、電解半田めっき処理を施して、開口１６に充填された銅めっき層１８上に半田めっき層を形成して、絶縁性基材１０の表面から１０μｍ突出する導電性バンプ２４を形成する。
〔電解半田めっき溶液〕
硫酸第一スズ（ＳｎＳＯ_４） ：５０±３ ｇ／ｌ
硫酸 ：９±１ ｍｌ／ｌ
Ｃｕの濃厚液 ：１０±５ ｍｌ／ｌ
安定剤 ：１ ｇ／ｌ
添加剤 ：１５±５ ｍｌ／ｌ
（電解半田めっき条件）
温度 ：２０±１ ℃
電流密度 ：０．４０±０．１０ Ａ／ｄｍ^２
【０１４６】
Ｃｕの濃厚液にはＣｕ^２＋とその錯体を形成するものを用いることができる。この場合、例えば、硫酸銅（ＣｕＳＯ_４）、塩化銅（ＩＩ）（ＣｕＣｌ_２）などがそれに該当する。また、安定剤としては、例えば、スズの安定剤（一例としてトップフリードＳＣＳ奥野製薬社製）、反応安定剤などの反応を安定化させるものを用いることができる。添加剤としては、液の添加剤（一例としてトップフリードＳＣＳ 奥野製薬社製）金属膜の光沢を向上させるもの、液分解抑制させるものなどを用いることができる。
なお、半田めっき溶液は、めっき層の金属組成比がＳｎ／Ｃｕ＝９９．３／０．７となるように調整され、このような半田めっきにより形成された導電性バンプ２４をなすＳｎ−Ｃｕ半田の融点Ｔ１は、２２７℃であった。
【０１４７】
（５） 次に、上記（３）で絶縁性基材１０に貼付したＰＥＴフィルム１５を剥離させた後、絶縁性基材１０の半田バンプ２４側の全面にエポキシ樹脂接着剤を塗布し、プレキュアして、多層化のための接着剤層２６を形成した。
上記（１）〜（５）にしたがって作製した片面回路基板Ａは、多層化の際に、最も上層に配置されるべき回路基板である。
【０１４８】
（６） 上記（１）〜（４）の工程と同様の処理をした後（図２（ａ）〜（ｄ）参照）、絶縁性基材１０の銅箔貼付面からＰＥＴフィルム１５を剥離させ、絶縁性基材１０の半田バンプ側の表面にエッチング保護フィルム２５を貼付した状態で、銅箔１２に適切なエッチング処理を施し、所定パターンを有する導体回路２８を形成した（図２（ｅ）参照）。
【０１４９】
（７） 次いで、上記（６）で得た導体回路２８の表面に、無電解めっき浴として、ホウフッ化スズ−チオ尿素液を用い、２０℃前後で約５分のめっき条件にて、無電解めっき処理を施して、厚さ０．１μｍのスズ薄膜層（図示を省略）を形成した。
【０１５０】
（８） 上記（６）で絶縁性基材１０に貼付したエッチング保護フィルム２５を剥離させた後、絶縁性基材１０の半田バンプ２４側の全面にエポキシ樹脂接着剤を塗布し、プレキュアして、各回路基板を接着して多層化するための接着剤層２６を形成した（図２（ｆ）参照）。
【０１５１】
上記（６）〜（８）の工程にしたがって作製される片面回路基板Ｂは、片面回路基板Ａとの組み合わせで多層化される基板であり、この実施例では３枚が作製された。
【０１５２】
（９） 上記３枚の片面回路基板Ｂに加えて、マット面を有する銅箔３０が圧着される片面回路基板Ｂとして、上記（６）〜（７）の工程と同様の処理をした後、上記（８）のような接着剤に代えて、マット面を有する銅箔３０を絶縁性基材１０上に効果的に接着するためのエポキシ樹脂接着剤が塗布され、１００℃で３０分間の乾燥を行って厚さ２０μｍの樹脂接着剤層３２が形成された。
【０１５３】
（１０） 上記（１）〜（５）にしたがって作製した片面回路基板Ａと、上記（６）〜（８）にしたがって作製した１枚の片面回路基板Ｂ１と、上記（９）にしたがって作製した片面回路基板Ｂ２とを、同一方向に、しかも所定位置に順次積層した後、最も外側に位置する片面回路基板Ｂ２の半田バンプ側の面に対して、片面がマット処理されて、その表面粗度が３μｍであり、厚さが１０μｍの銅箔３０を、そのマット面を対向させた状態で、加熱温度１８０℃、加熱時間７０分、圧力５ＭＰａ、真空度２．５×１０^３Ｐａの条件のもとで、加熱プレスすることによって、各片面回路基板Ａ，Ｂ１，Ｂ２間を接着すると共に、銅箔３０を片面回路基板Ｂ２の半田バンプ側の面に接着して多層化した。
【０１５４】
（１１） その後、多層化された基板の最上層に位置する片面回路基板Ａおよび最下層に位置する片面回路基板Ｂ２上の銅箔１２および３０に、適切なエッチング処理により導体回路３６および３８（バイアホールランドを含む）を形成した。
【０１５５】
（１２） 上記（１０）で多層化され、上記（１１）で回路形成された積層体の片面回路基板Ｂ２の導体回路３８側の面に対して、片面回路基板Ｂ３〜Ｂ４の導電性バンプ側の面を対向配置させた状態で、加熱温度１８０℃、加熱時間７０分、圧力５ＭＰａ、真空度２．５×１０^３Ｐａの条件のもとで、加熱プレスすることによって、上記（１１）で得られた積層体と、各片面回路基板Ｂ３，Ｂ４との間を接着して多層化した。
【０１５６】
（１３） 上記（１）〜（１２）の工程にしたがって作製した多層化基板の最上層および最下層に位置する回路基板ＡおよびＢ４の表面に、ソルダーレジスト層３７および３９を形成する前に、必要に応じて、銅−ニッケル−リンからなる粗化層を設ける。
【０１５７】
（１４） 一方、ＤＭＤＧに溶解させた６０重量％のクレゾールノポラック型エポキシ樹脂（日本化薬製）のエポキシ基５０％をアクリル化した感光性付与のオリゴマー（分子量４０００）を４６．６７重量部、メチルエチルケトンに溶解させた８０重量％のビスフェノールＡ型エポキシ樹脂（油化シェル製、エピコート１００１）１４．１２１重量部、イミダゾール硬化剤（四国化成製、２Ｅ４ＭＺ−ＣＮ）１．６重量部、感光性モノマーである多価アクリルモノマー（日本化薬製、Ｒ６０４）１．５重量部、同じく多価アクリルモノマー（共栄社化学製、ＤＰＥ６Ａ）３０重量部、アクリル酸エステル重合物からなるレベリング剤（共栄社製、ポリフローＮｏ．７５）０．３６重量部を混合し、この混合物に対して光開始剤としてのペンゾフェノン（関東化学製）２０重量部、光増感剤としてのＥＡＢ（保土ヶ谷化学製）０．２重量部を加え、さらにＤＭＤＧ（ジエチレングリコールジメチルエーテル）１０重量部を加えて、粘度を２５℃で１．４±０．３Ｐａ・Ｓに調整したソルダーレジスト組成物を得た。
なお、粘度測定は、Ｂ型粘度計（東京計器、ＤＶＬ‐Ｂ型）で６０ｒｐｍの場合はローターＮｏ．４、６ｒｐｍの場合はローターＮｏ．３によった。また、ソルダーレジストとしては、市販されているものを用いてもよい。
【０１５８】
（１５） 上記（１２）で得られた多層化基板の最上層および最下層の回路基板の表面に、前記（１４）で得られたソルダーレジスト組成物を２５μｍの厚さで塗布した。
次いで、７０℃で２０分間、１００℃で３０分間の乾燥処理を行った後、クロム層によってソルダーレジスト開口部の円パターン（マスクパターン）が描画された厚さ５ｍｍのソーダライムガラス基坂を、クロム層が形成された側をソルダーレジスト層に密着させて１０００ｍＪ／ｃｍ^２の紫外線で露光し、ＤＭＴＧ現像処理した。さらに、８０℃で１時間、１００℃で１時間、１２０℃で１時間、１５０℃で３時間の条件で加熱処理し、パッド部分に対応した開口４０および４２を有する（開口径２００μｍ）ソルダーレジスト層３７および３９（厚み２０μｍ）を形成した。
【０１５９】
（１６） 次に、ソルダーレジスト層３７および３９を形成した基板を、塩化ニッケル３０ｇ／１、次亜リン酸ナトリウム１０ｇ／１、クエン酸ナトリウム１０ｇ／１からなるｐＨ＝５の無電解ニッケルめっき液に２０分間浸漬して、開口部に厚さ５μｍのニッケルめっき層を形成した。
【０１６０】
さらに、その基板を、シアン化金力リウム２ｇ／１、塩化アンモニウム７５ｇ／１、クエン酸ナトリウム５０ｇ／１、次亜リン酸ナトリウム１０ｇ／１からなる無電解金めっき液に９３℃の条件で２３秒間浸漬して、ニッケルめっき層上に厚さ０．０３μｍの金めっき層を形成し、ニッケルめっき層と金めっき層とからなる被覆金属層５０を形成した。
場合によっては、スズもしくは金、銀、白金などの貴金属層の単層を形成してもよい。
【０１６１】
（１７） そして、最上層の片面回路基板Ａを覆うソルダーレジスト層３７の開口４０から露出する半田パッドに対して、融点Ｔ２が約１８３℃のＳｎ／Ｐｂ半田からなる半田ペーストを印刷して１９０℃でリフローすることにより、半田バンプ４４を形成し、最下層の片面回路基板Ｂ４を覆うソルダーレジスト層３９の開口４２から露出する半田パッドに対して、融点Ｔ３が約２３０℃のＳｎ／Ｓｂ半田を供給して２３０℃近傍の雰囲気内でリフローすることによって、半田ボール４６を接続させて、多層化回路基板６０を製作した。
【０１６２】
（実施例１−２）
実施例１−１とほぼ同様であるが、（４）の工程において、電解めっきにより導電性バンプを形成することに代えて、Ｓｎ／Ｃｕの組成比が９９．５／０．５であるような半田ペーストを用いて、マスクを使用した印刷法によって形成した。
【０１６３】
（実施例１−３）
実施例１−１とほぼ同様であるが、（４）の工程において、電解めっきにより導電性バンプを形成することに代えて、Ｓｎ／Ｃｕの組成比が９３．０／７．０であるような半田ペーストを用いて、マスクを使用した印刷法によって形成した。
【０１６４】
（実施例１−４）
実施例１−１とほぼ同様であるが、（４）の工程において、電解めっきにより導電性バンプを形成することに代えて、Ｓｎ／Ｃｕの組成比が９５．０／５．０であるような半田ペーストを用いて、マスクを使用した印刷法によって形成した。
【０１６５】
（実施例１−５）
実施例１−１とほぼ同様であるが、（４）の工程において、電解めっきにより導電性バンプを形成することに代えて、Ｓｎ／Ｃｕの組成比が９９．９／０．１であるような半田ペーストを用いて、マスクを使用した印刷法によって形成した。
【０１６６】
（実施例１−６）
実施例１−１とほぼ同様であるが、（４）の工程において、電解めっきにより導電性バンプを形成することに代え、Ｓｎ／Ｃｕの組成比が９９．９３／０．０７であるような半田ペーストを用いて、マスクを使用した印刷法によって導電性バンプを形成した。
【０１６７】
（実施例１−７）
実施例１−１とほぼ同様であるが、（４）の工程において、電解めっきに代えて、Ｓｎ／Ｃｕの組成比が９２．８／７．２であるような半田ペーストを用いて、マスクを使用した印刷法によって導電性バンプを形成した。
【０１６８】
（実施例１−８）
実施例１−１とほぼ同様であるが、（４）の工程において、電解めっきに代えて、Ｓｎ／Ｃｕの組成比が８９．０／１１．０であるような半田ペーストを用いて、マスクを使用した印刷法によって導電性バンプを形成した。
【０１６９】
（参考例１）
実施例１−１とほぼ同様であるが、（４）の工程において、電解めっきに代えて、Ｓｎ／Ｚｎの組成比が９１．０／９．０であるような半田ペースト（融点１９９℃）を用いて、マスクを使用した印刷法によって導電性バンプを形成した。
【０１７０】
（参考例２）
実施例１−１とほぼ同様であるが、（４）の工程において、電解めっきに代えて、Ｓｎ／Ｚｎの組成比が９９．５／０．５であるような半田ペースト（融点１８８℃）を用いて、マスクを使用した印刷法によって導電性バンプを形成した。
【０１７１】
（参考例３）
実施例１−１とほぼ同様であるが、（４）の工程において、電解半田めっき溶液およびめっき条件を変えて、以下のような条件で、電解半田めっき処理を施して、導電性バンプを形成した。
〔電解半田めっき溶液〕
Ｓｎの濃厚液 ：１２０±１０ ｍｌ／ｌ
Ａｇの濃厚液 ：９±１ ｍｌ／ｌ
安定剤 ：１２．５±０．５ ｍｌ／ｌ
添加剤 ：３００±１０ ｍｌ／ｌ
（電解半田めっき条件）
温度 ：２０±１ ℃
電流密度 ：０．４０±０．１０ Ａ／ｄｍ^２
Ｓｎの濃厚液にはＳｎ^２＋とその錯体を形成するものを用いることができる。この場合、例えば、硫酸スズ（ＳｎＳＯ_４）、塩化スズ（ＳｎＣｌ_２）、Ｋ_２Ｓｎ（ＯＨ）_６、ホウフッ化スズＳｎ（ＢＦ_４）_２、Ａｇの濃厚液にはＡｇ^２＋とその錯体を形成するものを用いることができる。この場合、たとえば、硫酸銀（ＡｇＳＯ_４）、塩化銀（ＩＩ）（ＡｇＣｌ_２）などがそれに該当する。また、安定剤としては、例えば、安定剤（一例としてＴＣ−ＲＢ２ ディップソール社製）、反応安定剤などの反応を安定化させるものを用いることができる。添加剤としては、液の添加剤（一例としてＴＣ−Ｃ ディップソール社製）金属膜の光沢を向上させるもの、液分解抑制させるものなどを用いることができる。
なお、半田めっき溶液は、めっき層の金属組成比がＳｎ／Ａｇ＝９６．５／３．５となるように調整され、このような半田めっきにより形成された導電性バンプ２４をなすＳｎ−Ａｇ半田の融点Ｔ１は、２２１℃であった。
【０１７２】
（参考例４）
実施例１−１とほぼ同様であるが、（４）の工程において、電解めっきに代えて、Ｓｎ／Ｓｂの組成比が９５．０／５．０であるような半田ペースト（融点２４０℃）を用いて、マスクを使用した印刷法によって導電性バンプを形成した。
【０１７３】
（比較例１）
実施例１−１とほぼ同様であるが、（４）の工程において、電解半田めっき溶液およびめっき条件を変えて、以下のような条件で、電解半田めっき処理を施して、導電性バンプを形成した。
〔電解半田めっき溶液〕
Ｓｎ（ＢＦ_４）_２ ：６５±５ ｍｌ／ｌ
Ｐｂ（ＢＦ_４）_２ ：２０±２ ｍｌ／ｌ
ＨＢＦ_４ ：２００±１０ ｍｌ／ｌ
添加剤 ：２０ ｇ／ｌ
安定剤 ：４０ ｍｌ／ｌ
（電解半田めっき条件）
温度 ：２０℃
電流密度 ：０．３８±０．１０ Ａ／ｄｍ^２
なお、半田めっき溶液は、めっき層の金属組成比がＳｎ／Ｐｂ＝６５／３５となるように調整され、このような半田めっきにより形成された導電性バンプ２４をなすＳｎ−Ｐｂ半田の融点Ｔ１は、１８３℃であった。
【０１７４】
（比較例２）
実施例１−１とほぼ同様であるが、（４）の工程において、電解めっきに代えて、Ｓｎ／Ｂｉの組成比が４２．０／５８．０であるような半田ペースト（融点１３８℃）を用いて、マスクを使用した印刷法によって導電性バンプを形成した。
【０１７５】
上記実施例１（実施例１‐１〜１‐７）、参考例１（参考例１‐１〜１‐４）、および比較例１、２により製造された多層化回路基板について、各５ピースずつ製造し、それらに対して信頼性試験としての高温放置試験（１５０℃、５００時間、１０００時間、２０００時間毎に評価）を行なった後に、導通試験を行なった。
その際に、５ピースの全てについて短絡が発生しなかった場合を○とし、１ピースまたは２ピースについて短絡が発生した場合には△とし、３ピース以上の短絡が発生した場合には×として示した。
表１は、これらの導通試験の結果を示す。
【０１７６】
【表１】

【０１７７】
上記導通試験の結果から分るように、導電性バンプの材料として、Ｃｕを含有した半田が、参考例１〜４に示したＳｎ／Ｚｎ、Ｓｎ／Ａｇ、Ｓｎ／Ｓｂ等のＺｎや、Ａｇ、Ｐｂを含有する半田と同様に、比較例１、２に示したＳｎ／Ｐｂ、Ｓｎ／ＢｉのようなＰｂやＢｉを含有する半田よりも信頼性に優れているということである。
【０１７８】
たとえば、Ｃｕの含有比を０．１〜７ｗｔ％とした場合、１５０℃の環境下で最大２０００時間までの高温放置試験を行った際、これらの実施例については、１５０℃、１０００時間の高温放置試験では、短絡の発生が全く認められない、つまり導電性バンプの溶融などが発生していないということが確認された。
【０１７９】
そして、Ｃｕの含有比を０．５〜５ｗｔ％に制限した場合には、１５０℃の環境下で最大２０００時間の高温放置試験を行なっても、短絡の発生が全く認められない。それ故に、そのような範囲であれば、Ｃｕの含有量が多少のバラツキが発生したとしても、０．１〜７ｗｔ％の範囲に収まるということであり、この範囲が最も望ましい範囲である。
【０１８０】
上記信頼性試験の結果からわかるように、多層配線基板を構成する各回路基板を電気的に接続する第１の導電性バンプが、Ｃｕを含有する半田から形成され、その融点Ｔ１が、多層配線基板の最外層に配設され、かつＩＣチップ等の電子部品を実装するための第２の導電性バンプの融点Ｔ２よりも高くなる（Ｔ１＞Ｔ２）ように、Ｃｕの含有比を所定範囲内に調整することによって、１５０℃の環境下で最大２０００時間の高温放置試験を行なっても、短絡発生を完全に阻止することができる。
【０１８１】
さらに、上記試験結果からわかることは、第１の導電性バンプの融点Ｔ１は、２２０℃以上を確保することができ、その融点Ｔ１が第２の導電性バンプ（Ｓｎ／Ｐｂ）の融点Ｔ２（＝１８３℃）よりも５℃以上高い場合には、信頼性が低下することがないことが確認された。
【０１８２】
【発明の効果】
以上説明したように、本発明の多層回路基板によれば、積層化の際に各回路基板間を電気的接続する導電性バンプの再溶融による拡散が効果的に抑制され得るので、隣接するパッド間の短絡や、回路基板間の位置ずれを防止することができる。
【０１８３】
したがって、積層される各回路基板間の電気的接続性や密着強度を向上させることができるとともに、最外層の回路基板上にＩＣチップ等の電子部品を半田バンプを介して確実に実装できるとともに、半田ボール、Ｔピン等の外部接続用端子も確実に実装することができる。
【図面の簡単な説明】
【図１】（ａ）〜（ｅ）は、本発明にかかる多層化回路基板を構成する片面回路基板Ａの製造工程の一部を示す図である。
【図２】（ａ）〜（ｆ）は、本発明にかかる多層化回路基板を構成する片面回路基板Ｂの製造工程の一部を示す図である。
【図３】本発明にかかる多層化回路基板の製造工程の一部を示す図であり、３枚の片面回路基板と銅箔との積層状態を示す。
【図４】本発明にかかる多層化回路基板の製造工程の一部を示す図であり、一体化された３枚の片面回路基板と銅箔との積層体に、他の２枚の片面回路基板を積層した状態を示す。
【図５】本発明にかかる多層化回路基板を示す図である。
【図６】（ａ）〜（ｃ） は、本発明にかかる多層化回路基板を構成する両面回路基板の製造工程の一部を示す図である。
【図７】本発明にかかる多層化回路基板を構成する片面回路基板と両面回路基板との積層状態を示す図である。
【図８】図６に示す積層状態にある片面回路基板と両面回路基板とを積層・一体化した多層化回路基板を示す図である。
【符号の説明】
１０ 絶縁性樹脂基材
１２ 銅箔
１４ 保護フィルム
１６ バイアホール形成用開口
１８ 電解銅めっき
２０ 充填バイアホール
２４ 導電性バンプ
２６ 樹脂接着剤層
２８ 導体回路
３０ 銅箔
３２ 樹脂接着剤層
３６ 導体回路
３７ ソルダーレジスト層
３８ 導体回路
３９ ソルダーレジスト層
４０，４２ 開口
４４ 半田バンプ
４６ 半田ボール
５０ 金属層
６２、６４ 導体回路
７２、７４ 導体回路
Ａ，Ｂ 片面回路基板
Ｃ 両面回路基板[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer printed wiring board having an IVH (inner via hole) structure, and more particularly to a multilayer printed wiring board excellent in connection reliability suitable for flip-chip mounting of electronic components such as IC chips.
[0002]
[Prior art]
There has been proposed a technology in which a conductor layer is provided on one side and an insulating substrate having an IVH (inner via hole) structure is multilayered. They are electrically connected by connecting a conductor layer of one insulating substrate and a via hole of the other insulating substrate, and an IC is provided on the outermost conductive circuit of the multilayered substrate. The configuration is such that a solder bump for mounting an electronic component such as a chip or a capacitor is formed to exert its function.
[0003]
[Patent Publication 1]
JP-A-10-13028
In the above multilayer printed wiring board, a circuit board as a basic unit to be laminated and multilayered has a conductive circuit formed on one surface of an insulating substrate, and a conductive material formed in a non-through hole reaching the conductive circuit from the other surface. Is formed, and a conductive bump made of a conductive metal is formed on the filled via so as to protrude outward from the surface of the insulating substrate.
[0005]
When a plurality of such circuit boards are stacked, and heated and pressed by a press or the like to form a multilayer, the lands of the circuit board facing the metal forming the conductive bumps are pressed and heated, and the like. A reaction occurs, and the conductive bumps of one circuit board are electrically connected to the conductor layers of the other circuit board simultaneously and physically.
[0006]
[Problems to be solved by the invention]
However, when the metal forming the conductive bump is used to mount an electronic component such as an IC chip via a solder bump provided on the outermost conductive circuit, or in a heat cycle test (especially after 1500 cycles), the resistance is reduced. When conducting continuity check such as value measurement, short-circuit (short-circuit) or change in resistance value occurs between adjacent conductive bumps due to melting of metal and flow in the substrate. As a result, As a result, there is a problem that the electrical connectivity and reliability of the multilayer printed wiring board are reduced.
[0007]
Therefore, the present invention has been made in view of the above-mentioned problems of the related art, and an object of the present invention is to mount a conductive bump on a substrate at the time of mounting electronic components such as an IC chip or a heat cycle test. It is an object of the present invention to provide a printed wiring board capable of preventing a flow and improving electrical connectivity and reliability.
[0008]
[Means for Solving the Problems]
The present inventor has conducted intensive studies in order to solve the above-mentioned problems. As a result, after conducting an IC chip mounting or after a high-temperature storage test (particularly after 500 hours), a continuity test such as resistance measurement was performed, and a change in resistance was performed. Observation of a cross photograph of the substrate on which the problem described above occurred, it was found that the metal constituting the conductive bumps diffused at the interface between the insulating layers and contacted with or adjacent to other adjacent conductor layers. . Therefore, a continuity test confirmed that a change in resistance or a short-circuit or a state close to the short-circuit occurred. That is, the flow of the conductive bump in the substrate was caused by the melting point and diffusion property of the metal forming the conductive bump. Was found to be caused by
[0009]
The present invention has been made based on such knowledge, and has the following content as a gist configuration.
[0010]
That is, the present invention provides a non-through hole in an insulating substrate having a conductor layer on one or both sides, fills the non-through hole with a conductor to form a via hole, and forms a conductive bump on the via hole. A multi-layer printed wiring board comprising two or more circuit boards formed by forming solder bumps, connecting the circuit boards by the conductive bumps, and forming solder bumps on the conductor layers of the outermost circuit board. At
The conductive bump is a multilayer printed wiring board characterized by being formed from a solder containing Cu.
[0011]
According to the above configuration, when Cu is contained in the metal forming the conductive bump, melting or diffusion of the metal itself can be suppressed, that is, the metal that forms the conductive bump once solidified becomes a Cu alloy. In order to prevent the metal from melting even under the influence of various thermal histories applied to the substrate when the alloy is multilayered, such as annealing, plating, and mounting of an IC chip, the conductive bump metal Troubles such as melting or diffusion of the compound can be suppressed. Therefore, a change in electric resistance or a short circuit can be prevented, a decrease in electric performance can be suppressed, and electric characteristics can be improved.
[0012]
In addition, when left in a high-temperature environment or during reliability tests such as heat cycle tests, solidified conductive bumps are re-melted, especially when left at high temperatures or when the temperature is raised (from low temperature to high temperature). And diffusion are suppressed.
[0013]
Further, since the intrusion of moisture into the interface between the conductive bump and the conductor portion is suppressed, it is possible to prevent the occurrence of expansion and contraction originating from the moisture at the interface, and therefore, it is possible to prevent the partial electric near the interface from being generated. Since an electrical insulation state (meaning that the moisture forms a gap) is not created, good electrical connectivity is ensured, and the reliability test can be improved.
[0014]
Further, since no moisture enters between the conductor layer and the via hole after the reliability test, the adhesion strength does not decrease. If water invades, when the temperature rises, the water may become the starting point and swell, and in such a case, a gap is formed or cracks are generated, and the adhesion is reduced. Will drop.
However, by employing a Cu-containing metal, the occurrence of gaps and cracks can be prevented, so that the adhesion strength does not decrease and the reliability can be improved.
[0015]
Further, in the case of a Cu-containing conductive metal, the melting or diffusibility of the metal itself is suppressed. Therefore, the via hole pitch can be further reduced, and a multilayer printed wiring board with a higher density can be obtained.
[0016]
Furthermore, at the interface between the solidified conductive metal and the conductive circuit, an alloy layer made of Cu-conductive metal is formed, and the formation of the alloy film becomes a protective film, and the metal of other portions of the conductive metal is formed. It prevents diffusion. In addition, even if the formation of the alloy film is affected by heat such as a heat history or a heat process, the formation of a new Cu alloy, particularly in a conductive circuit, is prevented, so that the diffusion of the conductive metal is prevented. It can be suppressed.
[0017]
Examples of the alloy containing Cu include alloys such as Sn / Cu, Sn / Pb / Cu, Sn / Ag / Cu, Sn / Ag / In / Cu, and Sn / Zn / Cu. Basically, various solders containing Cu can be used.
[0018]
In addition, since the lead-containing metal material is a factor that deteriorates the environment, its use is restricted. From such a viewpoint, as a Cu-containing alloy according to the present invention, a lead-free metal is used. It is preferable to use a material (such as a lead-free alloy).
However, the present invention should not be limited to such a solder, and any solder having a composition other than those may be used as long as it contains Cu.
[0019]
The content ratio of Cu in the metal forming the conductive bump is desirably 0.1 to 7 wt%.
The reason is that if the content is less than 0.1 wt%, the formation of the Cu alloy after solidification is small, so that the flow of the conductive bumps cannot be suppressed when re-melting. This is because in such a case, there is a risk of short-circuiting with another adjacent conductor layer. Further, at the interface between the conductive metal and the conductive circuit, a portion where the Cu alloy film is not formed occurs at a part thereof, and the conductive metal is melted and diffused from the portion where the Cu alloy film is not formed.
[0020]
On the other hand, if the content exceeds 7 wt%, the melting point becomes high, it becomes difficult to melt even when heat is applied, the conductive bump itself becomes hard, and when the conductive layer is brought into contact with the via hole at the time of multilayering, There is a concern that the conductor portion may have poor contact or cracks may occur in the conductor portion. This is because the electrical connectivity and adhesion are reduced.
Within the above range, the fluidity of the conductive bumps can be suppressed, the Cu alloy can be appropriately formed, and the adhesion to the conductor layer can be ensured.
[0021]
The content ratio of Cu in the metal forming the conductive bump is more preferably 0.5 to 5 wt%.
The reason is that the adhesion strength can be improved most, the hardness can be made appropriate, and the fluid can be uniformly flowed and diffused between the conductors, so that the electrical connectivity can be improved. is there.
Further, the adhesiveness of the conductive bump can be improved without being affected by the type of the conductive metal filled in the via hole (eg, plating, conductive paste, or a composite thereof).
[0022]
The melting point of the conductive bump is desirably in the range of 150 to 350C.
The reason is that if the temperature is lower than 150 ° C., the conductive bump itself is easily melted and diffused, and it is difficult to make the melting point higher than the melting point of solder bumps for mounting electronic components such as IC chips. This is because the hardness of the conductive bump becomes too high, making it impossible to connect, and the temperature at which the bump is melted may not be able to withstand the temperature depending on the material of the interlayer resin insulating layer.
[0023]
More preferably, the melting point of the conductive bump is in the range of 180 to 320 ° C. This is because within such a range, a strong bond can be obtained between the lands facing the bumps during hot pressing. Also, it is difficult to melt and diffuse even when mounting electronic components such as an IC chip or under a reliability test which is left in a high temperature environment.
[0024]
Further, the melting point of the conductive bump is most preferably in the range of 200 ° C to 300 ° C. This is because the connection stability is excellent irrespective of factors such as the material within the range.
[0025]
In the multilayer printed wiring board according to the present invention, solder bumps are formed not only on the conductive bumps but also on the outermost conductive circuit of the substrate, and the solder bumps are formed of Sn / Pb, Sn / Ag, Sn / Ag. / Cu, Sn / Cu, or Sn / Ag / In / Cu.
[0026]
It is desirable that the melting point T1 of the conductive bump is higher than the melting point T2 of the solder bump. The reason is that even when the electronic component such as an IC chip is mounted or a heat cycle test is performed, even if the melting temperature of the solder bump is exceeded, the conductive bump already solidified in the substrate can be prevented from melting. It is.
[0027]
On the other hand, if the melting point T1 of the conductive bumps is lower than the melting point T2 of the solder bumps, when mounting the IC chip, the conductive bumps will melt in a considerable part at that temperature. It flows considerably in the substrate. Therefore, when the flowing range is large, the conductive bumps are short-circuited with the adjacent conductor layer. In addition, if the flowing range is small, stress is generated between the substrates, and if the stress is not relaxed, a positional shift occurs. As a result, the thickness of the conductive bumps is reduced, and the adhesion strength and the electrical characteristics are reduced.
[0028]
Preferably, the melting point T1 of the conductive bump is higher than the melting point T2 of the solder bump by 5 ° C. or more. It was found that when the difference in melting point was 5 ° C. or more, even if the temperature exceeded the melting temperature of the solder bump, there was no effect on the conductive bump.
Even if the temperature difference of the melting point exceeds 0 ° C. and is less than 5 ° C., there is basically no effect on the conductive bumps, but the Cu content is relatively small and less than 0.1 wt%. May be affected.
[0029]
External connection terminals are formed on the multilayer printed wiring board using a conductive adhesive, and the melting point T3 of the conductive adhesive of the external connection terminals is preferably higher than the melting point T2 of the solder bumps.
[0030]
Also in this case, the melting point T1 of the conductive bump and the melting point T3 of the conductive adhesive of the external connection terminal are both higher than the melting point T2 of the solder bump.
Therefore, since the two melting points T1 and T3 are higher than the appropriate melting temperature of the solder bump, they do not melt at the time of mounting electronic components. That is, since the metal itself does not flow with the conductive bump, a short circuit occurs. In addition, the external terminals (BGA, PGA, etc.) do not cause a problem such as dropping or misalignment.
[0031]
Further, it is desirable that the melting point T3 of the conductive adhesive of the external connection terminal is higher by 5 ° C. or more than the melting point T1 of the conductive bump.
The reason is that if the difference in the melting points is 5 ° C. or more, the external connection terminals will not be affected even if the mounting is performed at a temperature at which the solder bumps melt when mounting electronic components such as an IC chip. In other words, such a temperature difference may cause external connection terminals (BGA, PGA, etc.) to fall off or to be displaced under the temperature conditions when electronic components such as IC chips are mounted via solder bumps. Because there is no.
[0032]
Examples of such a conductive adhesive include Sn / Ag, Sn / Sb, Sn / Cu, Sn / Ag / Cu, Sn / Zn, and Sn / Sb / Cu as solder. Examples of the brazing material include silver brazing materials such as Ag-Cu, and gold brazing materials such as Au-Si, Au-Sn, and Au-Ge. It is basically desirable that these have a higher melting point than the conductive bumps and the solder bumps.
Even if the temperature difference of the melting point exceeds 0 ° C. and is less than 5 ° C., basically, there is no effect on the external terminals, but when the thickness of the conductive adhesive for connecting the external terminals is small, etc. , May be affected.
[0033]
In the single-sided or double-sided circuit board as a basic unit constituting the multilayered circuit board according to the present invention, it is desirable to use a hard resin base formed from a completely cured resin material as the insulating base.
[0034]
By adopting such a hard resin material, curing shrinkage or the like does not occur when multi-layering is performed by a heat press. Therefore, positional deviation in the Z-axis direction can be minimized and the via land diameter can be reduced.
[0035]
Therefore, the wiring density can be improved by reducing the wiring pitch, and the thickness of the base material can be kept substantially constant, so that an opening for forming a filled via hole as described later is formed by laser processing. In the case of forming, the setting of the laser irradiation condition becomes easy.
[0036]
Examples of such an insulating substrate include glass cloth epoxy resin base material, glass cloth bismaleimide triazine resin base material, glass cloth polyphenylene ether resin base material, aramid nonwoven fabric-epoxy resin base material, and aramid nonwoven fabric-polyimide resin base material. Preferably, a selected hard substrate is used, and a glass cloth epoxy resin substrate is most preferred.
[0037]
Further, the thickness of the insulating base material is desirably 20 to 600 μm. The reason for this is that if the thickness is less than 20 μm, the strength is reduced and handling becomes difficult, and the reliability with respect to electrical insulation is reduced. If the thickness exceeds 600 μm, it is difficult to form a fine via hole opening. This is because the substrate itself becomes thicker.
[0038]
Conductive layers or conductive circuits formed on one or both surfaces of the insulating base material, affixing a copper foil on the insulating base material via a suitable resin adhesive, or etching the copper foil. Respectively formed.
[0039]
That is, the conductor layer is formed by hot-pressing a copper foil having a thickness of 3 to 40 μm on an insulating base material via a resin adhesive layer held in a semi-cured state, and the conductor circuit is formed by: After hot pressing the copper foil, apply a photosensitive dry film on the copper foil surface or apply a liquid photosensitive resist, place a mask with a predetermined wiring pattern, and expose and develop It is preferable that the plating resist layer is formed, and thereafter, the copper foil in the portion where the etching resist is not formed is etched.
[0040]
The heat press of the copper foil on the insulating base material is performed under an appropriate temperature and pressure, and more preferably, is performed under reduced pressure to cure only the semi-cured resin adhesive layer. As a result, the copper foil can be firmly adhered to the insulating base material, so that the manufacturing time is shortened as compared with a circuit board using a conventional prepreg.
[0041]
In addition, instead of sticking copper foil on such an insulating substrate, a single-sided or double-sided copper-clad laminate in which copper foil is previously adhered on an insulating substrate is adopted, and the copper-clad laminate is used. Conductive circuits can also be formed by etching with at least one selected from aqueous solutions of sulfuric acid-hydrogen peroxide, persulfate, cupric chloride, and ferric chloride.
[0042]
It is preferable that lands (pads) as a part of the conductor circuit are formed on the surface corresponding to each via hole of the conductor circuit in a diameter of 50 to 250 μm.
[0043]
It is preferable that a roughened layer is formed on the surface of the wiring pattern of the conductor circuit to improve the adhesion to an adhesive layer that joins the circuit boards, and to prevent the occurrence of delamination.
[0044]
Examples of the roughening treatment method include soft etching treatment, blackening (oxidation) -reduction treatment, formation of a needle-like alloy plating made of copper-nickel-phosphorus (manufactured by Ebara Uzilite: trade name: Interplate), and Mec Corporation There is a surface roughening by an etching solution called "Mech etch bond".
[0045]
A via hole forming opening formed to reach the conductor circuit from the surface opposite to the surface of the insulating resin substrate on which such a conductor circuit is formed has a pulse energy of 0.5 to 100 mJ and a pulse width of 0.5 to 100 mJ. Is preferably formed by a carbon dioxide laser irradiated under the conditions of 1 to 100 μs, a pulse interval of 0.5 ms or more, and the number of shots is 3 to 50, and the opening diameter is preferably in a range of 50 to 250 μm. .
The reason is that if it is less than 50 μm, it is difficult to fill the opening with a conductive substance and the connection reliability is lowered. If it exceeds 250 μm, it is difficult to increase the density.
[0046]
Before the opening is formed by the carbon dioxide gas laser, a resin film is preferably adhered to the surface of the insulating substrate opposite to the surface on which the conductor circuit is formed, and laser irradiation is preferably performed from above the resin film.
[0047]
This resin film performs a desmear treatment in the opening for forming the via hole, and functions as a protective mask when filling the metal plating by electrolytic plating in the opening after the desmear treatment. It functions as a printing mask for forming a conductive bump (projecting conductor) directly on the layer.
[0048]
The resin film is preferably formed of, for example, a PET film in which the thickness of the pressure-sensitive adhesive layer is 1 to 20 μm and the thickness of the film itself is 10 to 50 μm.
[0049]
The reason is that the height of the conductive bumps described later is determined depending on the thickness of the PET film, so if the thickness is less than 10 μm, the conductive bumps are too low, and the connection is likely to be poor, and conversely, the thickness exceeds 50 μm. If the thickness is too large, the conductive bumps spread too much at the connection interface, so that a fine pattern cannot be formed.
[0050]
In order to form a via hole by filling a conductive substance into the via hole forming opening, plating filling or conductive paste filling is desirable.
In order to simplify the filling process, reduce the manufacturing cost and improve the yield, filling with conductive paste is suitable, but depending on the composition ratio of conductive paste (conductive metal, resin, curing agent, etc.) Since curing shrinkage may become too large, plating filling is desirable in terms of the shape and connection reliability at the time of filling.
[0051]
The plating filling can be performed by either electrolytic plating or electroless plating. Metal plating formed by electrolytic plating, for example, tin, silver, solder, copper / tin, copper / silver, etc. Metal plating is preferred, and electrolytic copper plating is particularly optimal.
[0052]
When filling by the electrolytic plating process, the copper foil formed on the insulating base material is used as a plating lead in a state where the protective film is previously adhered to the surface of the insulating base material on which the copper foil is to be adhered (conductor circuit forming surface). Perform electrolytic plating. Since this copper foil (metal layer) is formed over the entire surface of one surface of the insulating base material, the current density becomes uniform, and the opening for forming the via hole is filled with electrolytic plating at a uniform height. can do.
Here, before the electrolytic plating process, the surface of the metal layer in the non-through hole may be activated with an acid or the like.
[0053]
Further, after the electrolytic plating, it is desirable that the electrolytic plating (metal) raised from the opening edge is removed by belt sander polishing, buff polishing, or the like, and flattened.
[0054]
Furthermore, instead of filling the conductive material by plating, a method of filling a conductive paste, or filling part of the opening by electrolytic plating or electroless plating, and filling the remaining part with the conductive paste is performed. You can also.
[0055]
As the conductive paste, a conductive paste composed of at least one kind of metal particles selected from copper, tin, gold, silver, nickel and various solders can be used.
As the metal particles, those obtained by coating the surface of metal particles with a different kind of metal can also be used. Specifically, metal particles in which the surface of copper particles is coated with a noble metal selected from gold and silver can be used.
[0056]
As the conductive paste, an organic conductive paste obtained by adding a thermosetting resin such as an epoxy resin or a polyphenylene sulfide (PPS) resin to metal particles is preferable.
[0057]
Since the opening formed by the laser processing has a fine hole diameter of 20 to 150 μm, bubbles are likely to remain when the conductive paste is filled, so that filling by electrolytic plating is practical.
[0058]
The via holes formed on the single-sided or double-sided circuit board described above have the largest arrangement density on the outermost circuit board for mounting an LSI chip or the like, and the outermost other on the outermost board for connection to the motherboard. The circuit board is formed so as to be the smallest, that is, the distance between via holes formed in each of the circuit boards to be laminated is different from the circuit board on which the LSI chip or the like is mounted to the side connected to the motherboard. Is preferably formed so as to become larger toward the circuit board, and according to such a configuration, the routing of wiring is improved.
[0059]
The multilayered circuit board according to the present invention is provided with a protruding conductor electrically connected to the via hole, that is, a conductive bump, on a single-sided or double-sided circuit board serving as a basic unit to be laminated, so that it can be connected to other circuit boards. Are configured to ensure electrical and mechanical connection.
[0060]
This conductive bump is desirably formed by plating or filling a conductive paste into the opening of the protective film formed by laser irradiation.
[0061]
The plating filling can be performed by either an electrolytic plating process or an electroless plating process, but the electrolytic plating process is preferable.
As the electrolytic plating, a low melting point metal such as copper, gold, nickel, tin and various solders can be used, but tin plating or solder plating is most suitable.
[0062]
The height of the conductive bump is desirably in the range of 3 to 60 μm. The reason for this is that if the thickness is less than 3 μm, variations in the height of the bump cannot be tolerated due to the deformation of the bump. If the thickness exceeds 60 μm, the resistance value increases and the bump spreads in the horizontal direction when the bump is formed. This may cause a short circuit.
[0063]
When the conductive bump is formed by filling the conductive paste, the variation in the height of the electrolytic plating forming the via hole is corrected by adjusting the amount of the conductive paste to be filled. The height of the bumps can be made uniform.
[0064]
The bump made of the conductive paste is preferably in a semi-cured state. This is because the conductive paste is hard even in a semi-cured state and can penetrate the organic adhesive layer softened during hot pressing. In addition, the contact area increases due to deformation during hot pressing, so that not only the conduction resistance can be reduced, but also a variation in bump height can be corrected.
[0065]
In addition to this, for example, a method of screen-printing a conductive paste using a metal mask provided with an opening at a predetermined position, a method of printing a solder paste that is a low-melting metal, and a method of dipping in a solder dissolving liquid A conductive bump can be formed.
[0066]
As the low melting point metal, a material containing Cu such as Sn-Pb-Cu solder, Sn-Cu solder, Ag-Sn-Cu solder, In-Cu solder, or Sn-Cu-Zn is used. Is desirable.
Specific examples include alloys such as Sn / Pb / Cu, Sn / Cu, Sn / Ag / Cu, Sn / Ag / In / Cu, and Sn / Cu / Zn. Basically, various solders containing Cu can be used.
[0067]
The content ratio of Cu in the metal forming the conductive bump is desirably 0.1 to 7% by weight.
The reason is that if it is less than 0.1 wt%, melting and diffusion of the conductive bumps are more likely to occur than in the above range, and if it exceeds 7 wt%, the melting point becomes high, and the melting of the conductive bumps is hindered. This is because the connectivity is reduced.
In particular, if the content exceeds 7 wt%, the material of the bump portion becomes too hard, so that cracks and the like are easily caused depending on the interlayer resin insulating layer. Basically, it is desirable that Cu be contained, and the above range is not affected by the interlayer resin insulating layer, the type of the filling material (plating, conductive paste or composite thereof, etc.), and more. It becomes desirable.
The lower limit of the above range does not include 0. The reason is that when the Cu content is 0 wt%, deterioration is more likely than when Cu is contained.
[0068]
The melting point of the conductive bump is desirably in the range of 150 to 350C.
The reason is that if the temperature is lower than 150 ° C., the conductive bump itself is easily melted and diffused. If the temperature is higher than 350 ° C., the hardness of the conductive bump becomes too hard, and connection may not be performed. This is because, depending on the material of the interlayer resin insulating layer, the material may not be able to withstand the temperature at which it is melted.
[0069]
More preferably, the melting point of the conductive bump is in the range of 180 to 320 ° C. Within such a range, strong bonding can be obtained between the lands facing the bumps during hot pressing. Also, it is difficult to melt and diffuse even when mounting electronic components such as an IC chip or under a reliability test which is left in a high temperature environment.
[0070]
Further, the melting point of the conductive bump is most preferably in the range of 200 ° C to 300 ° C. This is because the connection stability is excellent irrespective of factors such as the material within the range. Also in that case, the temperature is higher than the melting point of the solder bump. Further, it is desirable that the melting point of the solder bump is higher than the melting point by 5 ° C. or more.
[0071]
The multilayer circuit board according to the present invention is formed by laminating a plurality of circuit boards each having a conductor circuit formed on one surface of an insulating base material in a predetermined direction, and is disposed inside of those circuit boards. A conductor circuit having a predetermined wiring pattern formed by etching a copper foil having one surface matted with respect to the surface of the circuit board on which the conductive bumps are provided, with the mat surface facing the copper foil. It is also possible to form it.
[0072]
The matte surface of the copper foil is preferably formed by a known etching process, an electroless plating process, an oxidation-reduction process, or the like, and particularly preferably by an etching process.
The etching process includes a CZ process, the electroless plating process includes an interplate process, and the oxidation-reduction process includes a blackening process.
[0073]
The adhesion between the matted metal foil and the insulating resin base material varies depending on the resin viscosity, the thickness of the copper foil, the heating press pressure, and the like. When the thickness of the metal foil is in the range of 1 to 36 μm, the surface roughness of the mat surface of the metal foil is in the range of 0.5 to 5 μm, and the heating press pressure is 1 to 36 μm. in the range of 10 MPa, the peel strength of the resulting is preferably in the range of ^{0.5~2.0Kgf / cm 2 (4.9 × 10} 4 Pa~19.6 × 10 4 Pa).
[0074]
The matte surface of the copper foil is pressed not only on the surface of the one-sided circuit board on which the conductive bumps protrude, but also on the conductive bumps protruding from that surface. The bondability between the formed conductor circuit and the surface on the conductive bump side and between the conductor circuit and the conductive bump is improved.
[0075]
Generally, when a single-sided circuit board is laminated in multiple layers in the same direction, a heating step such as drying and annealing is repeated after immersion in a plating solution or a cleaning solution. Since the stress applied to the substrate is not buffered, the substrate itself warps, causing breakage of the conductor circuit, disconnection, poor connection at the via hole, peeling of the filled metal, etc., resulting in electrical connectivity and reliability. May cause a decrease in sex.
[0076]
However, as in the present invention, after a plurality of single-sided circuit boards and copper foil laminated in the same direction are integrated by a heat press, the copper foil is etched to form a conductor circuit, and the conductor circuit formation surface is formed. On the other hand, a plurality of other single-sided circuit boards may be stacked in a direction opposite to the above direction and integrated by a heating press.
[0077]
In this case, the matte surface of the copper foil is pressed against the surface on the conductive bump side of the single-sided circuit board located on the inner side, and the conductor circuit formed by etching the copper foil is laminated thereon. It can be formed in a desired wiring pattern having at least a conductive pad to be joined to a conductive bump of another single-sided circuit board.
[0078]
Therefore, the peel strength and the pull strength of the conductive circuit with respect to the surface of the conductive bump side of the substrate are sufficiently ensured, and the displacement of the conductive pad with respect to the via hole due to the heating press can be prevented. It can be carried out.
[0079]
In this case, since it is necessary to perform the heating press twice, an accurate scale factor is required, but high peel strength and pull strength can be obtained.
[0080]
At least one kind of protective film selected from tin, zinc, nickel and phosphorus or a protective film made of a noble metal such as gold or platinum may be formed on the matte surface of the copper foil forming the conductive circuit.
[0081]
The thickness of such a protective film is preferably in the range of 0.01 to 3 μm. The reason is that if it is less than 0.01 μm, fine irregularities on the mat surface cannot be completely covered. If it exceeds 3 μm, the protective film is filled in the formed concave portion of the mat surface, and the matting effect is offset. This is because it may be. A particularly preferred film thickness is in the range of 0.03 to 1 μm.
Among the above protective films, the protective film made of tin can be most advantageously applied because it can be formed as a thin film layer deposited by electroless displacement plating and has excellent adhesion to the mat surface.
[0082]
An electroless plating bath for forming such a tin-containing plating film uses a tin borofluoride-thiourea solution or a tin chloride-thiourea solution, and the plating treatment condition is about 5 ° C. at room temperature around 20 ° C. It is desirable that the heating time be about 1 minute at a high temperature of about 50 ° C. to 60 ° C.
[0083]
According to such an electroless plating treatment, a copper-tin substitution reaction based on the formation of a metal complex of thiourea occurs on the surface of the copper pattern, and a tin thin film layer is formed. Since it is a copper-tin substitution reaction, the mat surface can be covered without destroying the uneven shape.
[0084]
The noble metal that can be used in place of a metal such as tin is preferably gold or platinum. This is because these noble metals are less susceptible to acid or oxidizing agent, which is a roughening treatment liquid, than silver and the like, and can easily cover the mat surface. However, precious metals are often used only for high value-added products due to high costs. Such a gold or platinum coating can be formed by sputtering, electrolytic or electroless plating.
[0085]
By providing such a coating layer, the wettability of the mat surface becomes uniform, not only the bonding property with the conductive bump formed corresponding to the via hole is improved, but also the core material constituting the resin insulating layer Since the bonding property with the resin impregnated into the substrate can also be improved, the electrical connectivity and connection reliability are greatly improved.
[0086]
The multilayered circuit board formed by the laminating and heating press can be provided with a solder resist layer covering the surface of the outermost circuit board, that is, the circuit board located at the uppermost layer or the lowermost layer.
The solder resist layer is mainly formed of a thermosetting resin or a photosensitive resin, and has an opening at a position corresponding to a via hole position on a circuit board.
[0087]
In the multilayer printed wiring board according to the present invention, external connection terminals such as solder bumps, solder balls, and T-shaped conductive pins are provided on the conductor pads exposed from the openings of the solder resist layer.
[0088]
For example, among the outermost circuit boards, the uppermost circuit board on the side on which a semiconductor element such as an LSI is mounted is formed with solder bumps by printing conductive paste on conductive pads, Then, it is fixed by reflow processing.
[0089]
As described above, such a solder bump has a relatively lower melting point than the high melting point solder forming the conductive bump, for example, Sn / Ag, Sn / Pb, Sn / Zn, Sn / Cu, Sn. / Bi, an alloy such as Sn / Bi / Zn, and more desirably a solder having a melting point lower than the conductive bump by 5 ° C. or more.
[0090]
Among the outermost circuit boards, the other circuit boards in the lowermost layer on the side connected to the motherboard are located immediately above the via holes, for example, metal such as 42 alloy or phosphor bronze. T-shaped conductive pins formed of a material, or metal materials such as gold, silver, and solder (for example, Sn / Ag, Sn / Cu, Sn / Ag / Cu, Sn / Pb, Sn / Zn, etc.) An external connection terminal such as a conductive ball formed from a material can be provided.
[0091]
These T-shaped conductive pins are connected by a conductive adhesive made of solder or brazing material. The conductive balls are connected by a conductive adhesive by printing (such as screen printing) or a ball mounting method.
These conductive adhesives are connected to the conductive pads as external connection terminals by Sn / Sb solder, Sn / Ag solder, Sn / Ag / Cu solder or the like.
[0092]
The melting point T3 of the conductive adhesive is preferably formed of a metal higher than the melting point T1 of the conductive bump or the melting point T2 of the solder bump, and more preferably 5 ° C. or more.
[0093]
Hereinafter, an example of a method for manufacturing a multilayer circuit board according to the present invention will be specifically described with reference to the accompanying drawings.
(1) In manufacturing the multilayered circuit board according to the present invention, a single-sided circuit board as a basic unit constituting the multilayered circuit board uses a material in which a copper foil 12 is adhered to one surface of an insulating base material 10 as a starting material. .
[0094]
The insulating base material 10 is, for example, a glass cloth epoxy resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, an aramid nonwoven fabric-epoxy resin base material, an aramid nonwoven fabric-polyimide resin base material. A rigid laminated substrate of choice may be used, but glass cloth epoxy resin substrates are most preferred.
[0095]
The thickness of the insulating substrate 10 is desirably 20 to 600 μm. The reason is that if the thickness is less than 20 μm, the strength is reduced and handling becomes difficult, and the reliability with respect to the electrical insulation is reduced. If the thickness is more than 600 μm, fine via holes are formed and the conductive paste is used. This is because filling becomes difficult and the substrate itself becomes thick.
[0096]
Further, the thickness of the copper foil 12 is desirably 3 to 40 μm. The reason is that, when forming an opening for forming a via hole in the insulating base material by using a laser processing as described later, if it is too thin, it penetrates.On the contrary, if it is too thick, it is etched. This is because it is difficult to form a conductor circuit pattern having a fine line width.
[0097]
As the insulating base material 10 and the copper foil 12, in particular, a single-sided copper-clad laminate obtained by laminating a prepreg obtained by impregnating an epoxy resin into a glass cloth into a B stage, and laminating and hot pressing the copper foil. Preferably, a plate is used. The reason is that the positions of the wiring patterns and the via holes do not shift during handling after the copper foil 12 is etched, and the position accuracy is excellent.
[0098]
(2) Next, a transparent protective film 14 is attached to the surface of the insulating substrate 10 opposite to the surface to which the copper foil 12 is attached.
As the protective film 14, a polyethylene terephthalate (PET) film having a pressure-sensitive adhesive layer thickness of 1 to 20 μm and a film thickness of 10 to 50 μm is used.
[0099]
(3) Next, carbon dioxide laser irradiation is performed from above the PET film 14 stuck on the insulating base material 10, penetrates the PET film 14, and starts from the surface of the insulating base material 10 to the copper foil 12 (or conductive circuit). The opening 16 is formed to reach the pattern (see FIG. 1B).
This laser processing is performed by a pulse oscillation type carbon dioxide laser processing apparatus. The processing conditions are as follows: pulse energy is 0.5 to 100 mJ, pulse width is 1 to 100 μs, pulse interval is 0.5 ms or more, and the number of shots is 3 to It is desirably within the range of 50.
[0100]
It is desirable that the diameter of the via forming opening 16 that can be formed under such processing conditions be 50 to 250 μm.
The protective film 14 can be used as a printing mask when a solder bump as described later is formed by printing a conductive paste.
[0101]
(4) Desmearing is performed to remove resin residues remaining on the side and bottom surfaces of the opening 16 formed in the step (3).
This desmear treatment is desirably performed by dry treatment such as oxygen plasma discharge treatment, corona discharge treatment, ultraviolet laser treatment, or excimer laser treatment.
[0102]
(5) Next, after attaching a PET film 15 as a plating protection film to the copper foil surface of the desmeared substrate, electrolytic copper plating using the copper foil 12 as a plating lead is performed. Is filled with electrolytic copper plating 18 to form a filled via hole 20 (see FIG. 1C).
[0103]
After the electrolytic copper plating treatment, the PET film 14 stuck to the substrate is peeled off, and the electrolytic copper plating 18 raised above the opening 16 is removed and flattened by belt sander polishing, buff polishing or the like.
[0104]
(6) After performing the electrolytic copper plating treatment of the above (5), an electrolytic solder plating treatment (a solder containing Cu such as Sn / Cu) using the copper plating 18 as a plating lead is performed to form an electrolytic solder plating. The protruding conductor, that is, the conductive bump 24 is formed so as to slightly protrude from the surface of the electrolytic copper plating (see FIG. 1D).
[0105]
(7) Next, a resin adhesive is applied to the surface of the insulating base material 10 including the conductive bumps 24 to form an adhesive layer 26, and then the PET is attached to the copper foil 12 of the insulating base material 10. The film 15 is peeled off (see FIG. 1E).
Such a resin adhesive is applied to, for example, the entire surface including the conductive bumps 24 or the surface not including the conductive bumps 24 of the insulating base material 10, and is formed of an uncured resin in a dried state. It is formed as an agent layer. This adhesive layer is preferably precured for easy handling, and its thickness is preferably in the range of 5 to 50 μm.
[0106]
The adhesive layer 26 is preferably made of an organic adhesive. Examples of the organic adhesive include an epoxy resin, a polyimide resin, a thermosetting polyphenolene ether (PPE), and a composite resin of an epoxy resin and a thermoplastic resin. And at least one resin selected from a composite resin of epoxy resin and silicone oil, and BT resin.
As a method of applying the uncured resin which is an organic adhesive, a curtain coater, a spin coater, a roll coater, a spray coat, a screen print, or the like can be used. The formation of the adhesive layer can also be performed by laminating an adhesive sheet.
[0107]
The single-sided circuit board A manufactured according to the steps (1) to (7) has a copper foil as a conductor layer on one surface of the insulating base material 10 and an opening reaching the copper foil from the other surface. And a conductive bump 24 made of solder plating on the filled via hole, and an adhesive layer 26 on the surface of the insulating substrate 10 including the conductive bump 24. When the multilayer circuit board according to the present invention is formed, it is adopted as a circuit board that is laminated on the uppermost layer, or a circuit board that forms a double-sided circuit board together with a copper foil having a matte surface. Is done.
[0108]
Next, another single-sided circuit board B to be laminated below the single-sided circuit board A is manufactured.
(8) First, after performing the same treatment as the above steps (1) to (6) (see FIGS. 2A to 2D), the surface of the insulating base material 10 on which the conductive bumps 24 are formed is protected by etching. After affixing the film 25 and covering the copper foil 12 with a mask having a predetermined circuit pattern, an etching process is performed to form a conductor circuit 28 (including a land) (see FIG. 2E).
[0109]
In this processing step, first, a photosensitive dry film resist is attached to the surface of the copper foil 12, and then exposed and developed according to a predetermined circuit pattern to form an etching resist. The layer is etched to form a conductor circuit pattern 28 including lands.
[0110]
As this etching solution, at least one aqueous solution selected from aqueous solutions of sulfuric acid hydrogen peroxide, persulfate, cupric chloride and ferric chloride is desirable.
[0111]
As a pretreatment for etching the copper foil 12 to form the conductive circuit 28, in order to easily form a fine pattern, the entire surface of the copper foil is etched in advance to a thickness of 1 to 10 μm, more preferably 2 to 10 μm. The thickness can be reduced to about 8 μm.
[0112]
The land as a part of the conductor circuit has substantially the same inner diameter as the via hole diameter, but preferably has an outer diameter in the range of 50 to 250 μm.
[0113]
(9) A tin thin film layer (not shown) is formed on the surface of the conductor circuit 28 formed in (8) by electroless plating.
An electroless plating bath for forming such a tin-containing plating film uses a tin borofluoride-thiourea solution or a tin chloride-thiourea solution, and the plating treatment condition is about 5 ° C. at room temperature around 20 ° C. It is desirable that the heating time be about 1 minute at a high temperature of about 50 ° C. to 60 ° C.
According to such an electroless plating treatment, a copper-tin substitution reaction based on the formation of a metal complex of thiourea occurs on the surface of the copper pattern, and a tin thin film layer having a thickness of 0.01 to 1 μm is formed.
[0114]
The surface of the conductor circuit 28 formed in the step (7) is subjected to a roughening treatment as necessary, and the tin layer formed in the step (8) is formed on the roughened layer. You can also.
In addition, it is desirable to cover with a protective film made of at least one kind selected from zinc, nickel and phosphorus or a protective film made of a noble metal such as gold or platinum, instead of the tin layer.
[0115]
The roughening treatment is for improving the adhesion to the adhesive layer and preventing peeling (delamination) when forming a multilayer.
Examples of the roughening treatment method include soft etching treatment, blackening (oxidation) -reduction treatment, formation of a copper-nickel-phosphorus needle-like alloy plating (manufactured by Ebara Uzilite; trade name: Interplate), and Mec Corporation. There is a surface roughening by an etching solution called "Mech etch bond".
[0116]
The roughened layer is preferably formed by using an etchant. For example, the roughened layer is formed by etching the surface of a conductive circuit from a mixed aqueous solution of a cupric complex and an organic acid using an etchant. be able to. Such an etchant can dissolve the copper conductor circuit pattern under oxygen-existing conditions such as spraying and bubbling, and the reaction is presumed to proceed as follows.
[0117]

In the formula, A represents a complexing agent (acting as a chelating agent), and n represents a coordination number.
[0118]
As shown in the above formula, the generated cuprous complex dissolves under the action of an acid and combines with oxygen to form a cupric complex, which again contributes to copper oxidation. The cupric complex used in the present invention is preferably a cupric complex of azoles. The etching solution comprising the organic acid-cupric complex can be prepared by dissolving a cupric complex of an azole and an organic acid (halogen ion as required) in water.
Such an etchant is formed, for example, from an aqueous solution obtained by mixing 10 parts by weight of an imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride.
[0119]
(10) Next, after the protective film is peeled off from the surface of the insulating substrate 10 including the conductive bumps 24, the resin adhesive 26 is applied to the surface of the insulating substrate 10 (FIG. 2 (f)). reference).
Such a resin adhesive is applied to, for example, the entire surface including the conductive bumps 24 or the surface not including the conductive bumps 24 of the insulating base material 10, and is formed of an uncured resin in a dried state. It is formed as an agent layer. This adhesive layer is preferably precured for easy handling, and its thickness is preferably in the range of 5 to 50 μm.
[0120]
The adhesive layer 26 is preferably made of an organic adhesive. Examples of the organic adhesive include an epoxy resin, a polyimide resin, a thermosetting polyphenolene ether (PPE), and a composite resin of an epoxy resin and a thermoplastic resin. And at least one resin selected from a composite resin of epoxy resin and silicone oil, and BT resin.
As a method of applying the uncured resin which is an organic adhesive, a curtain coater, a spin coater, a roll coater, a spray coat, a screen print, or the like can be used. The formation of the adhesive layer can also be performed by laminating an adhesive sheet.
[0121]
The single-sided circuit board B manufactured according to the steps (8) to (10) has a conductive circuit on one surface of the insulating base material 10 and a conductive bump 24 made of solder plating on the other surface. And an adhesive layer 26 for bonding to another insulating substrate or an adhesive layer 32 for bonding to a copper foil on the surface of the insulating substrate 10 including the conductive bumps 24. It is formed to have.
[0122]
(11) The surface on the conductive bump side of the single-sided circuit board A is directed downward, and a plurality of single-sided circuit boards, for example, two of B1 and B2, are laminated in the same direction with respect to that surface, A copper foil 30 having a mat surface with a surface roughness of 3 μm and a thickness of 3 to 40 μm is laminated on the surface of the single-sided circuit board B2 on the conductive bump side in a state where the mat surface is opposed to the surface and heated. The single-sided circuit board A, the plurality of single-sided circuit boards B1 and B2, and the copper foil 30 are integrated by heating and pressing under the conditions of a temperature of 150 to 250 ° C. and a pressure of 1 to 10 MPa to form a multilayer. (See FIG. 3).
[0123]
In this case, instead of the adhesive layer 26, a resin adhesive for bonding a copper foil held in a semi-cured state is provided on the surface on the conductive bump side of the outermost (lower) single-sided circuit board B2. The layer 32 is formed, and the copper foil 30 is hot-pressed via the resin adhesive layer 32.
[0124]
This heat press is more preferably performed under reduced pressure to cure the uncured resin adhesive layer 26 and the resin adhesive layer 32, thereby allowing the one-sided circuit board A and the one-sided circuit boards B1 and B2 to be hardened. , And between the single-sided circuit board B2 and the copper foil 30.
At this time, the copper foil 30 is adhered to the insulating substrate 10 of the single-sided circuit board B2 via the cured adhesive layer 32, and the copper foil 30 and the solder bumps 24 are electrically connected.
[0125]
(12) Further, the copper foil 12 of the uppermost single-sided circuit board A and the copper foil 30 of the outermost single-sided circuit board B2 of the circuit board integrated in the above (11) are etched to form a conductor. The circuit 36 and the conductor circuit 38 (both include via hole lands) are formed (see FIG. 3).
[0126]
In this etching step, first, a photosensitive dry film resist is attached to the surface of the copper foil 12 of the single-sided conductor circuit A and the surface of the copper foil 30 pressed to the single-sided circuit board B2, respectively. Exposure and development are performed to form an etching resist, and the metal layer in the portion where the etching resist is not formed is etched to form conductor circuits 36 and 38 including via hole lands.
[0127]
(13) Next, the two single-sided conductor circuits B3 and B4 are integrated in the step (11) with respect to the surface on the conductor circuit 38 side of the laminate formed on both surfaces in (12). The layers are laminated with the surfaces on the conductive bump side facing each other, and heated and pressed under the conditions of a heating temperature of 150 to 250 ° C. and a pressure of 1 to 10 MPa, and the single-sided circuit boards A, B1, B2, The copper foil 30 and the single-sided circuit boards B3 and B4 are integrated (see FIG. 4).
[0128]
(14) Next, solder resist layers 37 and 39 are formed on the outermost single-sided circuit boards A and B4, respectively. In this case, a solder resist composition is applied to the entire outer surfaces of the circuit boards A and B4, and the coating film is dried. Then, a photomask film having an opening is placed on the coating film, and the film is exposed and developed. By processing, openings 40 and 42 exposing the conductive pad portions located immediately above the via holes of conductor circuits 36 and 28 are formed, respectively.
[0129]
(15) The solder bumps 44, the conductive balls 46, or the conductive pins are disposed on the solder pads exposed immediately above the via holes from the openings 40 and 42 of the solder resists 37 and 39 obtained in the step (14). Prior to this, it is preferable to form a metal layer 50 made of “nickel-gold” on each solder pad.
[0130]
The thickness of the nickel layer is desirably 1 to 7 μm, and the thickness of the gold layer is desirably 0.01 to 0.06 μm. The reason for this is that if the nickel layer is too thick, the resistance value will increase, and if it is too thin, it will easily peel off. On the other hand, if the gold layer is too thick, the cost increases, and if it is too thin, the adhesion effect with the solder body is reduced.
[0131]
(16) A solder body is supplied on the metal layer 50 made of nickel-gold provided on the solder pad portion, and the solder bump 44 is formed by melting and solidifying the solder body. The multi-layer circuit board 60 is formed by bonding the conductive pins to the solder pads using a conductive adhesive.
[0132]
As a method for supplying the solder body, a solder transfer method, a printing method, a ball mounting method, or the like can be used.
Here, in the solder transfer method, a solder foil is bonded to a prepreg, and the solder foil is etched leaving only a portion corresponding to an opening to form a solder pattern to form a solder carrier film. This is a method of applying a flux to a solder resist opening of a substrate, laminating the film so that a solder pattern is in contact with a pad, and heating and transferring the film.
[0133]
On the other hand, the printing method is a method in which a print mask (metal mask) having an opening at a position corresponding to a pad is placed on a substrate, and a solder paste is printed and heat treatment is performed. As the solder for forming such a solder bump, Sn / Ag, Sn / Pb, Sn / Zn, Sn / Sb solder, or the like can be used, and the melting point thereof is determined by the conductive property for connecting the laminated circuit boards. Desirably, it is lower than the melting point of the bump.
[0134]
Examples of the conductive adhesive for bonding the conductive balls 46 and the T pins on the pads include Sn / Sb-based solder and Sn / Ag-based solder having a melting point higher than the melting point T1 of the conductive bump and the melting point T2 of the solder bump. , Sn / Ag / Cu solder, Sn / Cu solder, or the like is preferably used.
[0135]
According to the embodiment according to the above steps (1) to (16), the multilayer circuit board 60 according to the present invention includes a single-sided circuit board A and two single-sided circuit boards B1 and B2 stacked in the same direction. The single-sided circuit boards B2 are heated and pressed in a state where the copper foil 30 is arranged so as to face the mat surface with respect to the surface on the conductive bump side of the outermost single-sided circuit board B2. After bonding, the copper foil 30 is pressure-bonded to the single-sided circuit board B2 to form a multilayer, and then the copper foil 12 of the single-sided circuit board A and the copper foil 30 pressed to the single-sided circuit board B2 are subjected to an etching treatment, and a conductive circuit 36 and 38 are formed, and further heat-pressed in a state where the surfaces of the single-sided circuit boards B3 and B4 on the side of the conductive bumps are opposed to the surface of the single-sided circuit board B2 on the side of the conductor circuit 38. It was layered, in addition to such an embodiment, it is also possible to employ the following ▲ 1 ▼ ~ ▲ 2 embodiments as described ▼.
[0136]
{Circle around (1)} Three single-sided circuit boards B1 to B3 formed of the same material are sequentially laminated in the same direction, and a mat is formed on the surface of the outermost single-sided circuit board B3 on the conductive bump side. With the copper foils 30 having surfaces facing each other, the single-sided circuit boards are bonded to each other by a vacuum heating press, and the copper foils 30 are pressure-bonded to the single-sided circuit board B3 to form a multilayer. After such multilayering, an etching process is performed with the etching protection film 25 attached to the uppermost single-sided circuit board B1 to selectively etch the copper foil 30 bonded to the single-sided circuit board B3. A conductor circuit having a predetermined pattern is formed.
After that, the layers are formed by vacuum heating and pressing with the surfaces of the single-sided circuit boards B4 and B5 facing the conductive bumps facing the surface of the single-sided circuit board B3 on the side of the conductor circuit 38.
[0137]
{Circle around (2)} As shown in FIG. 6 (a), instead of the adhesive layer 26 to be applied to the surface on the conductive bump side of the single-sided circuit board A, a resin adhesive 36 for copper foil bonding is applied, After the copper foil 30 having the matte surface is arranged to face the single-sided circuit board A that has maintained the cured state, and the copper foil 30 is press-bonded to the single-sided circuit board A by a heat press (see FIG. 6B). By performing an etching process, conductive circuits 62 and 64 having a predetermined pattern are formed on the front and back surfaces of the single-sided circuit board A, respectively, to form a double-sided circuit board C (see FIG. 6C). Thereafter, in a state where the single-sided circuit boards B1 and B2 and the single-sided circuit boards B3 and B4, which are sequentially stacked in the same direction, are stacked on the front and back surfaces of the double-sided circuit board C, the single-sided circuit boards B1 and B2, the double-sided circuit board C, and the single-sided circuit boards B3 and B4 are integrated.
[0138]
In the above-described embodiment, five single-sided circuit boards or four single-sided circuit boards and one double-sided circuit board are laminated and integrated to form a multilayer of five layers. However, multilayering is possible if necessary.
[0139]
【Example】
(Example 1-1)
(1) First, a single-sided circuit board constituting a multilayer circuit board is manufactured. This circuit board uses, as a starting material, a single-sided copper-clad laminate obtained by laminating a copper foil with a prepreg obtained by impregnating an epoxy resin into a glass cloth to form a B stage and heating and pressing.
[0140]
The thickness of the insulating base material 10 is 75 μm, the thickness of the copper foil 12 is 10 μm, and the surface of the laminate opposite to the copper foil forming surface has an adhesive layer with a thickness of 10 μm, and A PET film 14 having a thickness of 12 μm is laminated.
[0141]
(2) Next, carbon dioxide laser irradiation is performed from above the PET film 14 to form a via hole forming opening 16 that penetrates through the PET film 14 and the insulating base material 10 and reaches the copper foil 12. Was desmeared by oxygen plasma discharge. Alternatively, a wet desmear treatment in which the film is immersed in an oxidizing agent such as permanganic acid or chromic acid or an acid such as hydrochloric acid or sulfuric acid may be performed.
[0142]
In this example, a high peak short pulse oscillation type carbon dioxide laser processing machine made by Mitsubishi Electric was used to form an opening for forming a via hole, and a PET film having a thickness of 20 μm as a whole was laminated on the resin surface. A glass film epoxy resin substrate having a substrate thickness of 75 μm was irradiated with a laser beam from the PET film side by a mask image method, and an opening for forming a 150 μmφ via hole was formed at a speed of 100 holes / sec.
[0143]
(3) A PET film 15 is adhered to the copper foil application surface of the insulating base material 10 after the desmear treatment, and electrolytic copper plating using the copper foil 12 as a plating lead is performed under the following conditions to form an opening. 16 was filled with electrolytic copper plating 18 to form a filled via hole 20. At this time, since the electrolytic copper plating was slightly exposed above the opening 16, the exposed portion may be removed and flattened by sander belt polishing and buff polishing.
[0144]
[Electrolytic copper plating aqueous solution]
Sulfuric acid: 180 ± 5 g / l
Copper sulfate: 78 ± 2 g / l
Additive (manufactured by Atotech Japan, trade name: Capalaside GL): 1 ml / l
[Electroplating conditions]
Current density: 2 ± 0.1 A / dm ²
Time: 30 ± 2 minutes Temperature: 25 ± 1 ° C
[0145]
(4) Further, an electrolytic solder plating process is performed under the following conditions to form a solder plating layer on the copper plating layer 18 filled in the opening 16 and project from the surface of the insulating base material 10 by 10 μm. Conductive bumps 24 are formed.
[Electrolytic solder plating solution]
Stannous sulfate (SnSO ₄ ): 50 ± 3 g / l
Sulfuric acid: 9 ± 1 ml / l
Cu concentrate: 10 ± 5 ml / l
Stabilizer: 1 g / l
Additive: 15 ± 5 ml / l
(Electrolytic solder plating conditions)
Temperature: 20 ± 1 ° C
Current density: 0.40 ± 0.10 A / dm ²
[0146]
As the Cu concentrated liquid, one that forms a complex with Cu ²⁺ can be used. In this case, for example, copper sulfate (CuSO ₄ ), copper (II) chloride (CuCl ₂ ), and the like correspond thereto. As the stabilizer, for example, a stabilizer such as a tin stabilizer (for example, Topfried SCS Okuno Pharmaceutical Co., Ltd.) or a reaction stabilizer can be used. As an additive, a liquid additive (for example, Topfried SCS manufactured by Okuno Pharmaceutical Co., Ltd.) that improves the gloss of a metal film and that suppresses liquid decomposition can be used.
The solder plating solution was adjusted so that the metal composition ratio of the plating layer was Sn / Cu = 99.3 / 0.7, and the Sn—Cu forming the conductive bump 24 formed by such solder plating was used. The melting point T1 of the solder was 227 ° C.
[0147]
(5) Next, after the PET film 15 adhered to the insulating base material 10 in the above (3) is peeled off, an epoxy resin adhesive is applied to the entire surface of the insulating base material 10 on the solder bump 24 side, and precuring is performed. Thus, an adhesive layer 26 for multilayering was formed.
The single-sided circuit board A manufactured according to the above (1) to (5) is a circuit board to be disposed on the uppermost layer in the case of multilayering.
[0148]
(6) After performing the same processing as the above steps (1) to (4) (see FIGS. 2A to 2D), the PET film 15 is peeled off from the copper foil application surface of the insulating base material 10. With the etching protection film 25 attached to the surface of the insulating substrate 10 on the solder bump side, the copper foil 12 was subjected to an appropriate etching treatment to form a conductor circuit 28 having a predetermined pattern (FIG. 2E). reference).
[0149]
(7) Next, on the surface of the conductor circuit 28 obtained in the above (6), a tin borofluoride-thiourea solution was used as an electroless plating bath under electroplating conditions at about 20 ° C. for about 5 minutes. Plating was performed to form a tin thin film layer (not shown) having a thickness of 0.1 μm.
[0150]
(8) After the etching protection film 25 attached to the insulating base material 10 in the above (6) is peeled off, an epoxy resin adhesive is applied to the entire surface of the insulating base material 10 on the solder bump 24 side, and pre-cured. Then, an adhesive layer 26 for bonding each circuit board to form a multilayer was formed (see FIG. 2 (f)).
[0151]
The single-sided circuit board B manufactured according to the above-described steps (6) to (8) is a multilayered board in combination with the single-sided circuit board A. In this example, three boards were manufactured.
[0152]
(9) In addition to the three single-sided circuit boards B, a single-sided circuit board B to which the copper foil 30 having a matte surface is pressure-bonded is subjected to the same processing as in the above steps (6) to (7). Instead of the adhesive as in the above (8), an epoxy resin adhesive for effectively bonding the copper foil 30 having the matte surface to the insulating base material 10 is applied, and dried at 100 ° C. for 30 minutes. Was performed to form a resin adhesive layer 32 having a thickness of 20 μm.
[0153]
(10) Single-sided circuit board A manufactured according to the above (1) to (5), one single-sided circuit board B1 manufactured according to the above (6) to (8), and manufactured according to the above (9) After sequentially laminating the single-sided circuit board B2 in the same direction and at a predetermined position, the surface on the solder bump side of the outermost single-sided circuit board B2 is matted on one side, and its surface roughness is increased. Is 3 μm, a copper foil 30 having a thickness of 10 μm is placed under the conditions of a heating temperature of 180 ° C., a heating time of 70 minutes, a pressure of 5 MPa and a degree of vacuum of 2.5 × 10 ³ Pa, with the mat surface facing the copper foil 30. Originally, each of the single-sided circuit boards A, B1, and B2 was bonded by heating and pressing, and the copper foil 30 was bonded to the surface of the single-sided circuit board B2 on the solder bump side to form a multilayer.
[0154]
(11) Thereafter, the copper foils 12 and 30 on the single-sided circuit board A located on the uppermost layer and the single-sided circuit board B2 located on the lowermost layer of the multilayered board are subjected to appropriate etching treatment to conduct the conductor circuits 36 and 38 ( (Including via hole lands).
[0155]
(12) The conductive bumps of the single-sided circuit boards B3 to B4 with respect to the surface on the side of the conductor circuit 38 of the single-sided circuit board B2 of the multilayer formed in the above (10) and formed with the circuit in the above (11). In a state where the surfaces are arranged to face each other, by heating and pressing under the conditions of a heating temperature of 180 ° C., a heating time of 70 minutes, a pressure of 5 MPa, and a degree of vacuum of 2.5 × 10 ³ Pa, The obtained laminate and each of the single-sided circuit boards B3 and B4 were bonded to form a multilayer.
[0156]
(13) Before forming the solder resist layers 37 and 39 on the surfaces of the circuit boards A and B4 located on the uppermost layer and the lowermost layer of the multilayer substrate manufactured according to the above steps (1) to (12), If necessary, a roughening layer made of copper-nickel-phosphorus is provided.
[0157]
(14) On the other hand, 46.67 parts by weight of a photosensitizing oligomer (molecular weight 4000) in which 60% by weight of a cresol nopolak-type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG was acrylated with 50% of epoxy groups. 14.121 parts by weight of an 80% by weight bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, 1.6 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), photosensitive 1.5 parts by weight of a polyvalent acrylic monomer (R604, manufactured by Nippon Kayaku), 30 parts by weight of a polyvalent acrylic monomer (DPE6A, manufactured by Kyoeisha Chemical Co., Ltd.), and a leveling agent made of an acrylic acid ester polymer (Kyoeisha, 0.36 parts by weight of polyflow No. 75) were mixed, and Penzo as a photoinitiator was added to the mixture. 20 parts by weight of phenone (manufactured by Kanto Kagaku), 0.2 parts by weight of EAB (manufactured by Hodogaya Chemical) as a photosensitizer, and 10 parts by weight of DMDG (diethylene glycol dimethyl ether) were added. A solder resist composition adjusted to 4 ± 0.3 Pa · S was obtained.
The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type) at 60 rpm with a rotor No. In the case of 4, 6 rpm, the rotor No. According to 3. A commercially available solder resist may be used.
[0158]
(15) The solder resist composition obtained in the above (14) was applied to a thickness of 25 μm on the surfaces of the uppermost and lowermost circuit boards of the multilayer substrate obtained in the above (12).
Next, after performing a drying process at 70 ° C. for 20 minutes and at 100 ° C. for 30 minutes, a 5 mm-thick soda-lime glass substrate on which a circular pattern (mask pattern) of the solder resist opening is drawn by a chromium layer, The side on which the chromium layer was formed was brought into close contact with the solder resist layer, exposed to ultraviolet light of 1000 mJ / cm ² , and subjected to DMTG development. Furthermore, a solder resist having openings 40 and 42 (opening diameter 200 μm) corresponding to the pad portions is subjected to heat treatment under the conditions of 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours. Layers 37 and 39 (thickness 20 μm) were formed.
[0159]
(16) Next, the substrate on which the solder resist layers 37 and 39 were formed was coated with an electroless nickel plating solution having a pH of 5 consisting of 30 g of nickel chloride, 10 g of sodium hypophosphite, and 10 g of sodium citrate. For 20 minutes to form a nickel plating layer having a thickness of 5 μm in the opening.
[0160]
Further, the substrate was immersed in an electroless gold plating solution consisting of gold cyanide 2 g / 1, ammonium chloride 75 g / 1, sodium citrate 50 g / 1, and sodium hypophosphite 10 g / 1 at 93 ° C. By dipping for 2 seconds, a gold plating layer having a thickness of 0.03 μm was formed on the nickel plating layer, and a coating metal layer 50 including the nickel plating layer and the gold plating layer was formed.
In some cases, a single layer of a noble metal layer such as tin or gold, silver, or platinum may be formed.
[0161]
(17) Then, a solder paste made of Sn / Pb solder having a melting point T2 of about 183 ° C. is printed on the solder pad exposed from the opening 40 of the solder resist layer 37 covering the uppermost single-sided circuit board A and 190. The solder bumps 44 are formed by reflowing at a temperature of ° C, and the Sn / Sb solder having a melting point T3 of about 230 ° C is applied to the solder pads exposed from the openings 42 of the solder resist layer 39 covering the lowermost single-sided circuit board B4. Was supplied and reflowed in an atmosphere at about 230 ° C. to connect the solder balls 46, thereby manufacturing a multilayer circuit board 60.
[0162]
(Example 1-2)
Almost the same as Example 1-1, except that in the step (4), the composition ratio of Sn / Cu is 99.5 / 0.5 instead of forming the conductive bumps by electrolytic plating. It was formed by a printing method using a mask using a suitable solder paste.
[0163]
(Example 1-3)
Almost the same as Example 1-1, except that in the step (4), the composition ratio of Sn / Cu is 93.0 / 7.0 instead of forming the conductive bump by electrolytic plating. It was formed by a printing method using a mask using a suitable solder paste.
[0164]
(Example 1-4)
Almost the same as Example 1-1, except that in the step (4), the composition ratio of Sn / Cu is 95.0 / 5.0 instead of forming the conductive bump by electrolytic plating. It was formed by a printing method using a mask using a suitable solder paste.
[0165]
(Example 1-5)
It is almost the same as Example 1-1, except that in the step (4), the composition ratio of Sn / Cu is 99.9 / 0.1 instead of forming the conductive bump by electrolytic plating. It was formed by a printing method using a mask using a suitable solder paste.
[0166]
(Example 1-6)
This is almost the same as Example 1-1, except that in the step (4), the composition ratio of Sn / Cu is 99.93 / 0.07 instead of forming a conductive bump by electrolytic plating. A conductive bump was formed by a printing method using a mask using a solder paste.
[0167]
(Example 1-7)
Almost the same as in Example 1-1, except that in step (4), a mask was used instead of electrolytic plating, using a solder paste having a Sn / Cu composition ratio of 92.8 / 7.2. The conductive bumps were formed by a printing method using a.
[0168]
(Example 1-8)
Almost the same as in Example 1-1, except that in step (4), a mask was used instead of electrolytic plating, using a solder paste having a Sn / Cu composition ratio of 89.0 / 11.0. The conductive bumps were formed by a printing method using a.
[0169]
(Reference Example 1)
Almost the same as Example 1-1, except that in step (4), instead of electrolytic plating, a solder paste having a Sn / Zn composition ratio of 91.0 / 9.0 (melting point: 199 ° C.) Was used to form conductive bumps by a printing method using a mask.
[0170]
(Reference Example 2)
Almost the same as Example 1-1, except that in step (4), instead of electrolytic plating, a solder paste having a composition ratio of Sn / Zn of 99.5 / 0.5 (melting point: 188 ° C.) Was used to form conductive bumps by a printing method using a mask.
[0171]
(Reference Example 3)
Although substantially the same as Example 1-1, in the step (4), the electroconductive solder plating was performed under the following conditions by changing the electrolytic solder plating solution and the plating conditions to form a conductive bump. did.
[Electrolytic solder plating solution]
Sn concentrated solution: 120 ± 10 ml / l
Ag concentrate: 9 ± 1 ml / l
Stabilizer: 12.5 ± 0.5 ml / l
Additive: 300 ± 10 ml / l
(Electrolytic solder plating conditions)
Temperature: 20 ± 1 ° C
Current density: 0.40 ± 0.10 A / dm ²
As the Sn concentrated solution, a solution that forms a complex with Sn ²⁺ can be used. In this case, for example, Ag ²⁺ and a complex thereof are formed in a concentrated solution of tin sulfate (SnSO ₄ ), tin chloride (SnCl ₂ ), K ₂ Sn (OH) ₆ , tin borofluoride Sn (BF ₄ ) ₂ , and Ag. Can be used. In this case, for example, silver sulfate (AgSO ₄ ), silver (II) chloride (AgCl ₂ ), and the like correspond thereto. Further, as the stabilizer, for example, a stabilizer (for example, TC-RB2 manufactured by Dipsol Co., Ltd.), a reaction stabilizer or the like that stabilizes the reaction can be used. As the additive, a liquid additive (for example, TC-C Dipsol Co., Ltd.) that improves the gloss of the metal film, one that suppresses liquid decomposition, and the like can be used.
The solder plating solution is adjusted so that the metal composition ratio of the plating layer becomes Sn / Ag = 96.5 / 3.5, and Sn-Ag forming the conductive bumps 24 formed by such solder plating is used. The melting point T1 of the solder was 221 ° C.
[0172]
(Reference Example 4)
Almost the same as Example 1-1, except that in step (4), instead of electrolytic plating, a solder paste having a composition ratio of Sn / Sb of 95.0 / 5.0 (melting point 240 ° C.) Was used to form conductive bumps by a printing method using a mask.
[0173]
(Comparative Example 1)
Although substantially the same as Example 1-1, in the step (4), the electroconductive solder plating was performed under the following conditions by changing the electrolytic solder plating solution and the plating conditions to form a conductive bump. did.
[Electrolytic solder plating solution]
Sn (BF ₄ ) ₂ : 65 ± 5 ml / l
Pb (BF ₄ ) ₂ : 20 ± 2 ml / l
HBF ₄ : 200 ± 10 ml / l
Additive: 20 g / l
Stabilizer: 40 ml / l
(Electrolytic solder plating conditions)
Temperature: 20 ° C
Current density: 0.38 ± 0.10 A / dm ²
The solder plating solution was adjusted such that the metal composition ratio of the plating layer was Sn / Pb = 65/35, and the melting point T1 of the Sn—Pb solder forming the conductive bump 24 formed by such solder plating was adjusted. Was 183 ° C.
[0174]
(Comparative Example 2)
Almost the same as Example 1-1, except that in step (4), instead of electrolytic plating, a solder paste having a Sn / Bi composition ratio of 42.0 / 58.0 (melting point: 138 ° C.) Was used to form conductive bumps by a printing method using a mask.
[0175]
Each of the multilayered circuit boards manufactured according to Example 1 (Examples 1-1 to 1-7), Reference Example 1 (Reference Examples 1-1 to 1-4), and Comparative Examples 1 and 2 has a 5-piece structure. Each was manufactured and subjected to a high-temperature storage test (evaluated every 150 hours, 500 hours, 1000 hours, and 2000 hours) as a reliability test, and then a conduction test was performed.
At that time, when a short circuit did not occur in all of the five pieces, it is indicated by ○, when a short circuit occurred in one or two pieces, and when a short circuit occurred in three or more pieces, it was indicated by X. Was.
Table 1 shows the results of these continuity tests.
[0176]
[Table 1]

[0177]
As can be seen from the results of the continuity test, solder containing Cu was used as a material for the conductive bumps, such as Zn or Ag such as Sn / Zn, Sn / Ag, and Sn / Sb shown in Reference Examples 1 to 4, and Ag. Like the solder containing Pb and Pb, it is superior in reliability to the solder containing Pb and Bi such as Sn / Pb and Sn / Bi shown in Comparative Examples 1 and 2.
[0178]
For example, when the Cu content ratio is set to 0.1 to 7 wt%, when a high-temperature storage test is performed in a 150 ° C. environment for up to 2000 hours, a high temperature test at 150 ° C. and 1000 hours is performed. In the standing test, it was confirmed that no short circuit occurred, that is, no melting of the conductive bumps occurred.
[0179]
When the content ratio of Cu is limited to 0.5 to 5 wt%, no short circuit is observed at all even when a high-temperature storage test is performed in an environment of 150 ° C. for a maximum of 2000 hours. Therefore, in such a range, even if the Cu content slightly varies, it falls within the range of 0.1 to 7 wt%, and this range is the most desirable range.
[0180]
As can be seen from the results of the reliability test, the first conductive bumps for electrically connecting the circuit boards constituting the multilayer wiring board are formed of Cu-containing solder, and the melting point T1 of the multilayer wiring board is determined. The Cu content ratio is set within a predetermined range so as to be higher than the melting point T2 of the second conductive bump for disposing an electronic component such as an IC chip on the outermost layer of the substrate (T1> T2). Thus, even when a high-temperature storage test is performed for a maximum of 2000 hours in an environment of 150 ° C., occurrence of a short circuit can be completely prevented.
[0181]
Furthermore, it can be seen from the above test results that the melting point T1 of the first conductive bump can be maintained at 220 ° C. or higher, and the melting point T1 is equal to the melting point T2 of the second conductive bump (Sn / Pb). = 183 ° C), it was confirmed that the reliability did not decrease when the temperature was 5 ° C or more.
[0182]
【The invention's effect】
As described above, according to the multilayer circuit board of the present invention, the diffusion due to the re-melting of the conductive bumps that electrically connect the respective circuit boards during the lamination can be effectively suppressed. A short circuit between them and a displacement between circuit boards can be prevented.
[0183]
Therefore, it is possible to improve the electrical connectivity and adhesion strength between the circuit boards to be laminated, and to securely mount the electronic components such as the IC chips on the outermost circuit board via the solder bumps. External connection terminals such as solder balls and T-pins can also be securely mounted.
[Brief description of the drawings]
FIGS. 1A to 1E are views showing a part of a manufacturing process of a single-sided circuit board A constituting a multilayered circuit board according to the present invention.
FIGS. 2A to 2F are views illustrating a part of a manufacturing process of a single-sided circuit board B constituting a multilayer circuit board according to the present invention.
FIG. 3 is a view showing a part of the manufacturing process of the multilayer circuit board according to the present invention, and shows a laminated state of three single-sided circuit boards and copper foil.
FIG. 4 is a view showing a part of the manufacturing process of the multilayered circuit board according to the present invention, in which a laminated body of three integrated single-sided circuit boards and copper foil is combined with another two single-sided circuit boards; This shows a state where the substrates are stacked.
FIG. 5 is a view showing a multilayer circuit board according to the present invention.
FIGS. 6A to 6C are diagrams illustrating a part of a manufacturing process of a double-sided circuit board constituting the multilayered circuit board according to the present invention.
FIG. 7 is a diagram showing a laminated state of a single-sided circuit board and a double-sided circuit board which constitute a multilayer circuit board according to the present invention.
8 is a diagram showing a multilayer circuit board in which a single-sided circuit board and a double-sided circuit board in the stacked state shown in FIG. 6 are stacked and integrated.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Insulating resin base material 12 Copper foil 14 Protective film 16 Via hole forming opening 18 Electrolytic copper plating 20 Filling via hole 24 Conductive bump 26 Resin adhesive layer 28 Conductor circuit 30 Copper foil 32 Resin adhesive layer 36 Conductor circuit 37 Solder resist layer 38 Conductor circuit 39 Solder resist layer 40, 42 Opening 44 Solder bump 46 Solder ball 50 Metal layer 62, 64 Conductor circuit 72, 74 Conductor circuit A, B Single-sided circuit board C Double-sided circuit board

Claims (6)

A circuit in which a non-through hole is provided in an insulating substrate having a conductor layer on one or both sides, a conductor is filled in the non-through hole, a via hole is formed, and a conductive bump is formed on the via hole. In a multilayer printed wiring board comprising two or more layers of boards, and connection between each circuit board made by the conductive bumps, and solder bumps formed on a conductor layer of the outermost circuit board,
The multilayer printed wiring board, wherein the conductive bump is formed from a solder containing Cu. 2. The conductive bump according to claim 1, wherein the conductive bump is formed of any one of Sn / Cu, Sn / Pb / Cu, Sn / Ag / Cu, Sn / Cu / Zn, and Sn / Ag / In / Cu. 3. The multilayer printed wiring board according to the above. The multilayer printed wiring board according to claim 1, wherein a content ratio of Cu in the conductive bump is 0.1 to 7 wt%. The multilayer printed wiring board according to claim 1, wherein the melting point T1 of the conductive bump is higher than the melting point T2 of the solder bump. 5. The multilayer printed wiring board according to claim 4, wherein the melting point T1 of the conductive bump is higher than the melting point T2 of the solder bump by 5 ° C. or more. 6. The solder bump according to claim 1, wherein the solder bump is formed of one of Sn / Cu, Sn / Pb, Sn / Ag, Sn / Ag / Cu, and Sn / Ag / In / Cu solder. 2. The multilayer printed wiring board according to 1 above.

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