JP2005051136A - Solid-state imaging device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the voltage of an electronic shutter operation by suppressing a decrease in overflow drain function in a solid-state imaging device.
An N-type drain region 19 is provided between an N-type photodiode portion 13 and an N-type semiconductor substrate 11 in a P-type well region 12, and a pulse signal is supplied from a power source 20 to the electronic shutter operation. By applying the voltage and increasing the potential, signal charges accumulated in the photodiode portion 13 are discharged to the N-type drain region 19. Since the distance between the photodiode portion 13 and the N-type drain region 19 can be shortened, a large electric field is easily applied between them, and a depletion layer is easily formed. Therefore, the voltage of the power source 20 to be controlled can be reduced. Since the N-type drain region 19 is formed by As ion implantation and the impurity concentration distribution can be controlled with high accuracy, variation in saturation characteristics of the photodiode can be suppressed and the overflow drain function can be improved.
[Selection] Figure 1

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof.

  First, a conventional solid-state imaging device will be described. FIG. 4 is a cross-sectional view of a pixel portion of a conventional solid-state imaging device, 41 is an N-type semiconductor substrate, 42 is a P-type well region formed in the N-type semiconductor substrate 41, and 43 is an N-type that performs photoelectric conversion. The photodiode section 44 is an N-type charge transfer section for transferring signal charges. In photoelectric conversion, when light enters the photodiode portion 43, electrons and holes are generated. However, since the solid-state imaging device uses electrons as signal charges and accumulates unnecessary holes, 45 is a P-type well region 42. It is a hole accumulating portion that has a higher impurity concentration and accumulates P-type holes formed on the surface of the photodiode portion 43. 46 is a gate insulating film, 47 is a gate electrode for controlling the transfer of signal charges, 48 is a photodiode electron storage capacity, and when excess electrons exceeding the photodiode capacity are generated, electrons are transferred to the N-type charge transfer section 44. A Vsub power source 49 for functioning an overflow drain that allows excess electrons to flow to the N-type semiconductor substrate 41 so as not to leak, 49 is an insulating film covering the gate electrode 47.

  Hereinafter, the operation of the solid-state imaging device configured as described above will be described. When light enters the photodiode unit 43, photoelectric conversion is performed at the PN junction, and signal charges (electrons) corresponding to the amount of incident light are generated. By changing the potential of the gate electrode 47 to deepen the potential of the charge transfer unit 44, signal charges due to light flow from the photodiode unit 43 into the charge transfer unit 44. By applying a clock signal to the gate electrode 47, signal charges are transferred in a direction perpendicular to the paper surface, converted into a signal output, and taken out to an external circuit.

5 shows the in-substrate potential of the cross section taken along the line AA ′ of the solid-state imaging device of FIG. 4, (a) shows the potential when the overflow drain function is performed, and (b) shows the potential when the electronic shutter is activated. The photodiode drain and the overflow drain function for discharging excessive signal charges exceeding the photodiode capacitance to the N-type semiconductor substrate 41 are determined by the potential of the P-type well region 42 controlled by the set voltage of the Vsub power supply 48. . In addition, a pulse signal is applied to the Vsub power supply 48 to make the potential of the P-type well region 43 equal to or deeper than the potential of the photodiode portion 43, and the signal charge accumulated in the photodiode portion 43 is forcibly set within an arbitrary time. Thus, the electronic shutter operation for finely controlling the exposure time is realized by discharging to the N-type semiconductor substrate 41.
Y.Ishihara, E.Oda, H.Tanigawa, N.Teranishi, E.Takeuchi, I.Akiama, K.Arai, M.Nishimuraand T.Kamata: Interline CCD Image Sensor with Anti Blooming Structure, ISSCC Dig.Tech.Papers pp.168-169 (1982)

  However, in the conventional solid-state imaging device, the potential of the well region 42 and the photodiode portion 43 varies due to variations in impurity concentration in the N-type region of the N-type semiconductor substrate 41, wafer-to-wafer differences, and manufacturing variations such as ion implantation and thermal diffusion. Occurs. For this reason, the photodiode characteristics vary, and the saturation characteristics corresponding to the substantial maximum capacity of electrons accumulated in the photodiode section 43 vary. Further, even if the set voltage of the Vsub power supply 48 is applied to the N-type semiconductor substrate 41, the overflow drain function does not sufficiently function, and excessive charge leaks into the charge transfer section 44 as a signal charge, and a suspicious signal called blooming is generated. There has been a problem that image quality degradation occurs.

  Further, as described above, in the conventional solid-state imaging device, a pulse signal is applied to the Vsub power supply 48 during the electronic shutter operation, and the potential is deepened to forcibly cause the signal charges accumulated in the photodiode portion 43 to be an N-type semiconductor substrate. At this time, in order to deplete the well region 42 and completely eliminate the potential barrier through the voltage of the Vsub power supply 48, a high Vsub voltage is required, and the electronic shutter mode is operated at a low voltage. There is a problem that it is difficult to reduce the power consumption of the solid-state imaging device.

  In order to suppress the above-described phenomenon of deterioration of the overflow drain function, there is a method of reducing the variation in the semiconductor substrate concentration and the impurity introduction condition variation of the semiconductor manufacturing apparatus. It is necessary to introduce a device to perform, and the cost is high, which is not realistic. In order to reduce the voltage of the electronic shutter operation described above, there is a method of reducing the concentration of the impurity elements in the well region 42 and the photodiode portion 43 to easily lower the internal potential barrier. The saturation characteristic deteriorates.

  The present invention solves the above-described conventional problems, and provides a solid-state imaging device and a method of manufacturing the same that can suppress variations in saturation characteristics and a decrease in overflow drain function and can reduce the voltage of an electronic shutter function. The purpose is to provide.

  In order to solve the above problems, a solid-state imaging device according to the present invention has a first conductivity type that generates a signal charge by photoelectric conversion on a second conductivity type well region formed on a first conductivity type semiconductor substrate. A solid-state imaging device including a photodiode portion and a first-conductivity-type charge transfer portion for transferring a signal charge generated in the photodiode portion, the well between the photodiode portion and the semiconductor substrate A drain region of the first conductivity type to which a predetermined signal is applied is provided inside the region.

  A voltage for determining the charge storage capacity of the photodiode is applied between the first conductive type semiconductor substrate and the second conductive type well region. The predetermined signal applied to the drain region of the first conductivity type is a pulse voltage.

  The method for manufacturing a solid-state imaging device according to the present invention as described above includes a step of forming a first semiconductor layer of the second conductivity type on a semiconductor substrate of the first conductivity type, and a first region in a predetermined region of the first semiconductor layer. A step of forming a drain region of one conductivity type and a second semiconductor layer of a second conductivity type are formed on the first semiconductor layer and the drain region, thereby forming a well region composed of the first and second semiconductor layers. A first conductive type photodiode unit that generates signal charges by photoelectric conversion and a signal charge generated by the photodiode unit in the well region above the first conductive type drain region; Forming a charge transfer portion of one conductivity type.

  As described above, according to the present invention, the first conductivity type drain region is provided between the photodiode portion and the semiconductor substrate in the second conductivity type well region on the first conductivity type semiconductor substrate. A signal voltage accumulated in the photodiode portion is discharged to the drain region by applying a pulse voltage and deepening the potential during the electronic shutter operation. Thus, by discharging signal charges to the drain region adjacent to the photodiode portion instead of the semiconductor substrate, the voltage of the electronic shutter function can be reduced, and the power consumption can be reduced. Further, since the drain region is formed by As ion implantation or the like, the impurity concentration distribution can be controlled with high accuracy, so that it is possible to quickly discharge excessive signal charges from the photodiode portion to the drain region, The overflow drain function is improved and the variation in the saturation characteristics of the photodiode is reduced.

  Hereinafter, the structure of a solid-state imaging device according to an embodiment of the present invention will be described with reference to FIG. In the figure, 11 is an N-type semiconductor substrate, 12 is a P-type well region formed in the N-type semiconductor substrate 11, 13 is an N-type photodiode portion for performing photoelectric conversion, and 14 is for transferring signal charges. N-type charge transfer unit, 15 is a P-type hole accumulation unit formed on the N-type photodiode unit 13, 16 is a gate insulating film, 17 is a polysilicon gate electrode for controlling the transfer of signal charges, Reference numeral 18 denotes a Vsub power source for determining the photodiode capacitance and causing the overflow drain to function.

  Reference numeral 19 denotes an N-type drain region formed by locally distributing As in the P-type well region 12 and is provided below the photodiode portion 13 provided in each pixel. The planar pattern of the N-type drain region 19 has a strip shape arranged along the column or row of the pixel array. This pattern is connected to the line wiring of the power source 20 at the end of the pixel array. In addition, unlike the above-described strip shape, the planar pattern of the N-type drain region 19 may be a planar pattern in which a rectangular pattern facing the photodiode portion 13 is connected by a thin diffusion layer. Also in this case, it is connected to the line wiring of the power source 20 at the end of the pixel array. A power source 20 applies a pulse signal connected to the N-type drain region 19. An insulating film 21 covers the gate electrode 17.

  In this solid-state imaging device, when light enters the photodiode unit 13, photoelectric conversion is performed at the PN junction between the photodiode unit 13 and the well region 12, and signal charges (electrons) corresponding to the amount of incident light are generated. . By changing the potential of the gate electrode 17 to deepen the potential of the charge transfer unit 14, signal charge due to light flows from the photodiode unit 13 into the charge transfer unit 14. By applying a clock signal to the gate electrode 17, signal charges are transferred in the direction perpendicular to the paper surface, converted into a signal output, and taken out to an external circuit.

  Next, a method for manufacturing the solid-state imaging device corresponding to FIG. 1 will be described with reference to FIG. After implanting B ions into the N-type semiconductor substrate 11, a P-type lower well region 12a is formed by thermal diffusion and annealing (FIG. 2A). Next, As ions are implanted into the P-type lower well region 12a using a resist as a mask, and an N-type drain region 19 is formed on the surface of the lower well region 12a. This N-type drain region 19 is to be connected to a power source 20 to which a pulse signal is applied. Further, by depositing a P-type semiconductor layer (P-type upper well region 12b) on the substrate by an epitaxial method or the like, an N-type drain region 19 is formed in the P-type well region 12 as shown in FIG. ) Structure. The N-type drain region 19 may be formed by performing As ion implantation using a resist as a mask after deposition of the P-type semiconductor layer (P-type upper well region 12b).

  Next, using the resist as a mask, an N-type photodiode portion 13 is formed by ion implantation of As, a charge transfer portion 14 is formed by ion implantation of As and P, and a hole accumulation portion 15 is formed by ion implantation of B ( FIG. 2 (c)). Subsequently, after forming a gate insulating film 16 and polysilicon, a polysilicon gate electrode 17 is formed by etching using a resist as a mask, and then an insulating film 21 covering the upper and side portions of the gate electrode 17 is formed. (FIG. 2D).

  As described above, the solid-state imaging device is completed according to the present embodiment. In this device, the potential of the N-type drain region is controlled by applying a voltage in place of the conventional semiconductor substrate 11. FIG. 3 is a diagram for explaining the operation of the solid-state imaging device of the present embodiment, schematically showing the potential of the cross section taken along the line AA ′ of FIG. 1, wherein (a) shows the potential at the overflow drain function. (B) shows the potential when the electronic shutter is activated.

  The potential of FIG. 3 is shorter than the conventional potential of FIG. 5 because the distance between the photodiode portion 13 and the N-type drain region 19 is short, and a large electric field is easily applied between them, and a depletion layer is easily formed. ing. Further, by forming the N-type drain region 19 by As ion implantation using a resist as a mask, the lateral dimension of the N-type drain region 19 relative to the N-type semiconductor substrate 11 (the photodiode portion 13 of the N-type drain region 19). The position in the horizontal (horizontal) direction) and the impurity concentration distribution in the depth direction are controlled with high accuracy. Therefore, excessive signal charges are quickly discharged from the photodiode portion 13 to improve the overflow drain function and reduce the saturation characteristic variation. As described above, the impurity concentration distribution of the N-type drain region 19 can be accurately obtained without being affected by manufacturing variations such as impurity concentration unevenness and wafer-to-wafer differences, which were problems due to the conventional use of the N-type semiconductor substrate as the drain region. Therefore, it is possible to suppress the variation in saturation characteristics and the occurrence of image deterioration due to blooming.

  Further, during the electronic shutter operation, signal charges are discharged to the N-type drain region 19 in which the concentration of the impurity element is controlled instead of the conventional N-type semiconductor substrate having a large variation in impurity element concentration. Operation can be performed simply by applying a voltage corresponding to the potential of the P-type well region 12 in which the concentration of the impurity element separating the type drain region 19 is controlled, and variation in characteristics is also reduced. At the same time, the photodiode portion 13 and the N-type drain region 19 can be made close to each other, so that a large electric field is easily applied between them, and a depletion layer is easily formed. it can.

  Further, by changing the acceleration voltage and dose amount of As ion implantation, the thickness of the N-type drain region 19 and the distance to the photodiode portion 13 can be arbitrarily changed, so that the operating characteristics of the overflow drain and the electronic shutter can be arbitrarily set. It becomes possible to set to.

  In the present embodiment, the N-type drain region 19 is formed by As ion implantation using a resist as a mask. However, the N-type drain region 19 may be similarly formed by selectively performing epitaxial growth. It is clear that there is an effect.

  A solid-state imaging device and a manufacturing method thereof according to the present invention suppress a variation in saturation characteristics and a decrease in overflow drain function, and can reduce the voltage of an electronic shutter function. It is useful as a manufacturing method thereof.

Sectional drawing of the solid-state imaging device concerning one embodiment of this invention Process sectional drawing which shows the manufacturing method of the solid-state imaging device concerning one embodiment of this invention The figure which shows the potential at the time of the overflow drain function and electronic shutter operation | movement in the solid-state imaging device concerning one embodiment of this invention Sectional view of a conventional solid-state imaging device The figure which shows the potential at the time of the overflow drain function and the electronic shutter operation in the conventional solid-state imaging device

Explanation of symbols

11, 41 N-type semiconductor substrate 12, 42 P-type well region 13, 43 Photodiode portion 14, 44 Charge transfer portion 15, 45 Hole accumulation portion 16, 46 Gate insulating film 17, 47 Gate electrode 18, 48 Vsub power supply 19 N-type drain region 20 Power supply for applying pulse signal

Claims (4)

A first conductivity type photodiode section that generates signal charges by photoelectric conversion on a second conductivity type well region formed on a first conductivity type semiconductor substrate, and a signal charge generated by the photodiode section A solid-state imaging device comprising a first conductivity type charge transfer unit for transferring
A solid-state imaging device, wherein a drain region of a first conductivity type to which a predetermined signal is applied is provided in the well region between the photodiode portion and the semiconductor substrate.   2. The structure according to claim 1, wherein a voltage for determining a charge storage capacity of the photodiode is applied between the first conductive type semiconductor substrate and the second conductive type well region. Solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the predetermined signal applied to the drain region of the first conductivity type is a pulse voltage.   Forming a second conductive type first semiconductor layer on the first conductive type semiconductor substrate; forming a first conductive type drain region in a predetermined region of the first semiconductor layer; and the first semiconductor. Forming a second semiconductor layer of the second conductivity type on the layer and the drain region, forming a well region composed of the first and second semiconductor layers; and an upper portion of the drain region of the first conductivity type Formed in the well region are a first conductivity type photodiode section for generating signal charges by photoelectric conversion and a first conductivity type charge transfer section for transferring signal charges generated by the photodiode section. A solid-state imaging device manufacturing method.

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