JP2005093816A - Semiconductor device manufacturing method and the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor device with which source and drain regions can be formed easily. <P>SOLUTION: A silicon oxide film 13 is formed by heat-oxidizing the upper part of an amorphous silicon film pattern 10. The dimension of the silicon oxide film 13 in the widthwise direction is larger than that of the amorphous silicon film pattern 10 in the widthwise direction. Then a pocket region and an extension region are formed, by injecting an impurity into a silicon substrate 1 from the oblique upside of the substrate 1 by using the silicon oxide film 13 as a mask. Next, the source and drain regions are formed by changing the injection angle of the impurity. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a metal gate electrode and the semiconductor device.

  2. Description of the Related Art In recent years, high integration in semiconductor integrated circuit devices has greatly advanced. In MOS (Metal Oxide Semiconductor) type semiconductor devices, miniaturization and high performance of elements such as transistors have been achieved in order to cope with high integration. ing. In particular, with regard to the gate insulating film which is one of the elements constituting the MOS structure, the thinning is rapidly progressing to cope with the miniaturization, high speed operation and low voltage of the transistor. When the gate insulating film is made thinner, the depletion layer formed in the silicon substrate can be easily controlled, and the short channel effect of the MOSFET can be suppressed.

  However, if the electric field applied to the gate electrode side becomes relatively strong due to the thinning of the gate insulating film, there is a problem that a depletion layer is formed when a sufficient carrier concentration cannot be obtained in the gate electrode. In particular, since there is a limit to the amount of impurities implanted into polycrystalline silicon, when the gate electrode is formed using polycrystalline silicon, the above-described problem of depletion of the gate electrode occurs.

  The depletion of the gate electrode increases the effective gate insulating film thickness and causes a decrease in current driving force. For this reason, when the gate insulating film is thinned, it is necessary to make the gate insulating film thin about several kilometers in advance in consideration of the depletion layer. However, when the gate insulating film is made thinner, there is a problem that a tunnel current, that is, a gate leakage current generated by carriers (electrons and holes) directly tunneling through the gate insulating film increases. Another problem is that B (boron) as an impurity contained in the P-type polycrystalline silicon penetrates the gate insulating film and reaches the channel layer of the semiconductor substrate, thereby varying the threshold voltage of the transistor.

  Therefore, it has been considered to use metal as a gate electrode material instead of polycrystalline silicon. As a result, the resistance of the gate electrode can be reduced, and the above-described problems of depletion of the gate electrode and problems of penetration of B can be solved.

  However, when metal is used as the gate electrode material, there is a problem that the metal reacts with the gate insulating film during the activation annealing process to the source / drain regions in a later process, and the electrical characteristics of the MOS transistor are deteriorated. It was. Therefore, as a process for forming the gate electrode after performing the activation annealing treatment, a MOS transistor forming method using a damascene method or a replacement method has been proposed (see Non-Patent Documents 1 and 2).

A. Chatterjee et al., Sub-100 nm Gate Length Metal Gate NMOS Transistors manufactured by the replacement gate process manufactured by a replacement gate process. IEEE, 1997, p. 821-824 A. Yagishita et al., High Performance Metal Gate MOSFETs Fabricated by CMP for 0.1 μm Regime by CMP, 1998, IE Eee (IEEE), 1998 , P. 785-788

  FIG. 35 is a cross-sectional view of a conventional dummy gate electrode. As shown in the figure, an element isolation region 62 that partitions a PMOS region and an NMOS region is formed on the surface of the silicon substrate 61. An N well 63 is formed in the PMOS region of the silicon substrate 61, and a P well 64 is formed in the NMOS region. A dummy gate electrode 66 is provided on the silicon substrate 61 via a dummy gate insulating film 65. Here, the dummy gate electrode 66 is formed through a patterning process by a photolithography method.

  On the other hand, the pocket regions 67 and 68 and the extension regions 69 and 70 formed in the silicon substrate 61 are divided into a PMOS region and an NMOS region by ion implantation using the dummy gate electrode 66 as a mask. . The source / drain regions 71 and 72 are formed again by dividing the PMOS region and the NMOS region by ion implantation using the side wall 73 formed on the side wall portion of the dummy gate electrode 66 as a mask. Is called.

  As described above, according to the conventional method, there is a problem that ion implantation for forming the impurity region must be performed at least twice for each of the PMOS and NMOS.

  In addition, due to the presence of the sidewall provided on the side wall portion of the dummy gate electrode, the miniaturized device has a problem that the line capacitance between the contact and the gate electrode increases, and the operation speed of the device decreases. It was.

  Furthermore, since the dummy gate electrode is formed through a photolithography process, the obtained gate length and gate width are subject to the rules of the photolithography process. Therefore, there is a problem that an expensive exposure apparatus is required to manufacture a fine transistor.

  The present invention has been made in view of such problems. That is, an object of the present invention is to provide a method of manufacturing a semiconductor device in which source / drain regions can be easily formed.

  Another object of the present invention is to provide a semiconductor device manufacturing method capable of reducing the capacitance between wirings.

  A further object of the present invention is to provide a method for manufacturing a semiconductor device capable of manufacturing a fine transistor without requiring an expensive exposure apparatus, and a semiconductor device manufactured by this method.

  Other objects and advantages of the present invention will become apparent from the following description.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation region on a semiconductor substrate and partitioning it into an NMOS region and a PMOS region, a step of forming a dummy gate insulating material film on the semiconductor substrate, and the dummy A step of forming an amorphous silicon film on the gate insulating material film; a step of forming a hard mask material film on the amorphous silicon film; and etching the hard mask material film by photolithography to form an amorphous silicon film on the amorphous silicon film. Forming a hard mask having an opening in the substrate, etching the amorphous silicon film using the hard mask as a mask to form a dummy gate electrode, forming a silicon oxide film on the surface of the dummy gate electrode, A dummy gate electrode is formed so as to cover the dummy gate electrode after the silicon oxide film is formed. Forming an anti-oxidation film on the insulating film, etching back the anti-oxidation film to expose the upper portion of the dummy gate electrode, and thermally oxidizing the exposed dummy gate electrode to at least in the width direction. Forming an oxidized portion having a size larger than the non-oxidized portion, removing the antioxidant film, etching the dummy gate insulating material film to form a dummy gate insulating film, and an oxidized portion of the dummy gate electrode Using the mask as a mask, impurities are implanted into the PMOS region of the semiconductor substrate from an obliquely upward direction of the semiconductor substrate to form an extension region of the PMOS, and the oxidized portion of the dummy gate electrode as a mask from the obliquely upward direction of the semiconductor substrate. Impurities are implanted into the PMOS region, and a PMOS pocket region is formed at the end of the PMOS extension region. Then, using the oxidized portion of the dummy gate electrode as a mask, impurities are implanted into the PMOS region of the semiconductor substrate at an angle smaller than the implantation angle when forming the PMOS extension region and the implantation angle when forming the PMOS pocket region, A step of forming a source / drain region of the PMOS, a step of implanting impurities into the NMOS region of the semiconductor substrate from an obliquely upward direction of the semiconductor substrate using the oxidized portion of the dummy gate electrode as a mask, and a step of forming an NMOS extension region; Implanting impurities into the NMOS region of the semiconductor substrate from an obliquely upward direction of the semiconductor substrate using the oxidized portion of the gate electrode as a mask, forming an NMOS pocket region at the end of the NMOS extension region, and an oxidized portion of the dummy gate electrode To form an extension region for NMOS A step of implanting impurities into the NMOS region of the semiconductor substrate at an angle smaller than the implantation angle at the time of forming the NMOS pocket region and forming the NMOS source / drain region, and covering the dummy gate electrode Forming an interlayer insulating film, polishing the interlayer insulating film and the oxidized portion of the dummy gate electrode to expose the upper surface of the non-oxidized portion of the dummy gate electrode, and removing the exposed dummy gate electrode. A step of exposing the dummy gate insulating film; a step of removing the exposed dummy gate insulating film to form a groove reaching the semiconductor substrate; a step of forming a gate insulating film on the inner surface of the groove; and And a step of forming a metal gate electrode so as to fill the trench.

  In the above invention, a step of injecting silicon into the amorphous silicon film can be further included before the step of heating and oxidizing the dummy gate electrode. The step of forming the hard mask material film can be a step of depositing a silicon nitride film at a temperature of 550 ° C. or lower. Furthermore, the antioxidant film can be a silicon nitride film.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming an element isolation region in a semiconductor substrate and partitioning it into an NMOS region and a PMOS region, and a step of forming a dummy gate insulating material film on the semiconductor substrate. A step of forming a dummy gate electrode on the dummy gate insulating material film, a step of forming a first spacer on the side wall of the dummy gate electrode, and removing the dummy gate insulating material film under the dummy gate electrode Forming a dummy gate insulating film, and implanting impurities into the PMOS region of the semiconductor substrate from an obliquely upward direction of the semiconductor substrate using the dummy gate electrode and the first spacer as a mask to form a PMOS extension region. Process and PMOS region of semiconductor substrate from diagonally upward direction of semiconductor substrate using dummy gate electrode and first spacer as mask Implanting impurities to form a PMOS pocket region at the end of the PMOS extension region, and using the dummy gate electrode and the first spacer as a mask, the implantation angle when forming the PMOS extension region and the PMOS pocket region Impurities are implanted into the PMOS region of the semiconductor substrate at an angle smaller than the implantation angle at the time of formation, and a source / drain region of the PMOS is formed, and the semiconductor substrate is obliquely formed using the dummy gate electrode and the first spacer as a mask Impurities are implanted into the NMOS region of the semiconductor substrate from the direction to form an NMOS extension region, and impurities are implanted into the NMOS region of the semiconductor substrate from the diagonally upward direction of the semiconductor substrate using the dummy gate electrode and the first spacer as a mask. The end of the NMOS extension region Forming a pocket region of the NMOS, and using the dummy gate electrode and the first spacer as a mask, the semiconductor is formed at an angle smaller than the implantation angle when forming the NMOS extension region and the implantation angle when forming the NMOS pocket region. Implanting impurities into the NMOS region of the substrate to form an NMOS source / drain region, forming an interlayer insulating film so as to cover the dummy gate electrode, and polishing the interlayer insulating film to dummy gate electrode Removing the exposed dummy gate insulating film to form a groove reaching the dummy gate insulating film, and removing the dummy gate insulating film exposed from the groove leaving a predetermined film thickness. Forming a second spacer material film so as to fill the trench, and the second spacer material film and gate insulation Etching the film to expose the semiconductor substrate and forming a second spacer on the side surface of the groove; forming a gate insulating film on the inner surface of the groove; and embedding the groove after forming the gate insulating film And a step of forming a metal gate electrode.

  In the above invention, the thickness of the dummy gate insulating material film is preferably 10 nm or more and 100 nm or less. The dummy gate electrode can be made of polysilicon. The first spacer can be made of a silicon nitride film. Further, the second spacer can be made of a silicon nitride film.

  In the method for manufacturing a semiconductor device of the present invention, the gate insulating film is selected from the group consisting of a silicon oxide film, an aluminum oxide film, a hafnium oxide film, a zirconium oxide film, a strontium oxide film, a titanium oxide film, and a nitrogen-added film thereof. Any one single-layer film or a laminated film composed of two or more films can be used.

  Furthermore, the semiconductor device of the present invention includes a first spacer provided on the side wall of the dummy gate electrode, a pocket region formed by ion implantation in the semiconductor substrate using the dummy gate electrode and the first spacer as a mask, An extension region, a source / drain region, an interlayer insulating film formed by embedding a dummy gate electrode and a first spacer on a semiconductor substrate, and a groove portion from which the dummy gate electrode of the interlayer insulating film has been removed, A second spacer provided along the gate, a gate insulating film covering the semiconductor substrate and the second spacer in the groove, and a metal gate electrode provided in the groove via the gate insulating film. It is a feature.

  In the semiconductor device of the present invention, an insulating film may be provided between the semiconductor substrate and the second spacer.

  As described above, according to the present invention, the dummy gate portion is thermally oxidized to form an oxidized portion having a dimension at least in the width direction larger than that of the non-oxidized portion, and impurities are implanted into the semiconductor substrate using the oxidized portion as a mask. Thus, the source / drain regions can be formed following the formation of the pocket region and the extension region. Therefore, the side wall forming step can be eliminated, and the photolithography step for forming the pocket region and the extension region and the photolithography step for forming the source / drain region can be integrated into one. The number can be made smaller than before.

  In addition, according to the present invention, the first spacer is formed on the side wall of the dummy gate electrode, and impurities are implanted into the semiconductor substrate using the dummy gate electrode and the first spacer as a mask, so that the pocket region and the extension are formed. Subsequent to the formation of the region, a source / drain region can be formed. Therefore, since the photolithography process for forming the pocket region and the extension region and the photolithography process for forming the source / drain regions can be made one, the total number of processes can be reduced as compared with the conventional method. .

  Furthermore, according to the present invention, it is possible to form a fine gate electrode pattern by providing the second spacer in the region where the dummy gate electrode of the interlayer insulating film is removed. That is, by controlling the dimension in the width direction of the second spacer, the dimension in the width direction of the gate electrode can be controlled, so that it is possible to form a fine gate electrode pattern that is not subject to the rules of the photolithography process. It becomes.

Embodiment 1 FIG.
A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. Note that the dimensional ratios of the components in these drawings do not limit the actual semiconductor device. In particular, in FIGS. 1 to 16, the portion where the gate electrode is formed is emphasized for the sake of explanation.

  First, as shown in FIG. 1, an element isolation region 2 is formed on the surface of a silicon substrate 1 as a semiconductor substrate. Thus, the silicon substrate 1 is partitioned into an NMOS region and a PMOS region that constitute the CMOS transistor. Thereafter, an N well 3 is formed in the PMOS region, and a P well 4 is formed in the NMOS region.

  Next, a silicon oxide film 5 as a dummy gate insulating material film is formed on the semiconductor substrate 1 (FIG. 2). The silicon oxide film 5 can be formed to have a thickness of about 10 nm, for example, and can be formed by oxidizing the surface of the silicon substrate 1 in an oxidizing gas atmosphere at a temperature of about 900 ° C.

  Next, an amorphous silicon film 6 as a dummy gate electrode material film is formed on the silicon oxide film 5. As the amorphous silicon film 6, for example, a film having a thickness of about 150 nm formed at a temperature of about 530 ° C. can be used.

  After the amorphous silicon film 6 is formed, a silicon nitride film 7 as a hard mask material film is formed thereon. Here, the silicon nitride film 7 is preferably formed at a low temperature of 550 ° C. or lower in order to prevent the underlying amorphous silicon film 6 from being polycrystallized. The film thickness of the silicon nitride film 7 is appropriately determined in relation to the film thickness of the amorphous silicon film 6. Specifically, the film thickness of the silicon nitride film 7 is preferably a film thickness that disappears upon completion of etching of the amorphous silicon film 6. For example, when the thickness of the amorphous silicon film 6 is about 150 nm, the thickness of the silicon nitride film 7 is preferably in the range of 30 nm to 50 nm.

  After the silicon nitride film 7 is formed, an antireflection film (not shown) may be formed thereon. The antireflection film plays a role of eliminating exposure light reflection at the interface between the resist film and the antireflection film by absorbing exposure light transmitted through the resist film when patterning a resist film to be formed next. As the antireflection film, a film containing an organic substance as a main component can be used. For example, the antireflection film can be formed by a spin coating method or the like.

  Next, a resist film (not shown) is formed on the silicon nitride film 7, and a resist pattern 8 having a desired line width is formed by photolithography to obtain the structure of FIG. Here, the resist pattern 8 corresponds to a dummy gate electrode pattern.

  Next, the silicon nitride film 7 is dry etched using the resist pattern 8 as a mask. Thereafter, by removing the resist pattern 8 that is no longer needed, a silicon nitride film pattern 9 as a hard mask can be formed (FIG. 4). As shown in FIG. 4, the silicon nitride film pattern 9 is a pattern having an opening 9 a on the amorphous silicon film 6.

  Next, the amorphous silicon film 6 is dry etched using the silicon nitride film pattern 9 as a mask. Thereby, an amorphous silicon film pattern 10 as a dummy gate electrode is formed in the NMOS region and the PMOS region (FIG. 5). In FIG. 5, the silicon nitride film pattern 9 disappears with the formation of the amorphous silicon film pattern 10.

  Next, thermal oxidation is performed to form a silicon oxide film 11 on the surface of the amorphous silicon film pattern 10 (FIG. 6). For example, the surface of the amorphous silicon film pattern 10 can be oxidized in an oxidizing gas atmosphere at a temperature of about 800 ° C. to form a silicon oxide film 11 having a thickness of about 5 nm. The silicon oxide film 11 has a role of protecting the amorphous silicon film pattern 10 when an antioxidant film described later is removed.

  Next, a silicon nitride film 12 as an antioxidant film is formed on the entire surface so as to embed the amorphous silicon film pattern 10 (FIG. 7). Here, the anti-oxidation film refers to a film that prevents the surface of the silicon substrate 1 from being thermally oxidized together when the amorphous silicon film pattern 10 is thermally oxidized in a subsequent process. The film thickness of the silicon nitride film 12 can be about 400 nm, for example, and can be deposited by plasma CVD at a film forming temperature of about 400 ° C.

  After the silicon nitride film 12 is formed, the surface of the silicon nitride film 12 is planarized by CMP (Chemical Mechanical Polishing), and then the upper part of the dummy gate electrode is exposed by performing etch back. As a result, as shown in FIG. 8, the upper part of the amorphous silicon film pattern 10 on which the silicon oxide film 11 is formed is exposed. Here, the amorphous silicon film pattern 10 is protected from damage by dry etching due to the presence of the silicon oxide film 11.

  Next, the amorphous silicon film pattern 10 is heated and oxidized on the exposed dummy gate electrode to form a silicon oxide film 13 (FIG. 9). The silicon oxide film 11 is made identical to the silicon oxide film 13 by forming the silicon oxide film 13.

  Here, since amorphous silicon has a large coefficient of thermal expansion, the silicon oxide film 13 is formed by the heat treatment, and the dummy gate electrode has an overall expanded shape. In the present embodiment, the dimension L in the width direction of the dummy gate electrode after the heat treatment is made substantially equal to the dimension in the width direction of the dummy gate electrode after the conventional sidewall formation. Therefore, the height h of the dummy gate electrode exposed in FIG. 8 is appropriately set in consideration of the dimension L in the width direction of the dummy gate electrode after the heat treatment. If the height h is reduced, the dimension L in the width direction is reduced. If the height h is increased, the dimension L in the width direction is also increased.

For example, in the case of batch processing, the heat treatment conditions for forming the silicon oxide film 13 can be about 2 hours in an oxidizing gas atmosphere at a temperature of about 900 ° C. If it is difficult to obtain the desired film thickness of the silicon oxide film 13, silicon is formed in the amorphous silicon film 6 after the formation of the amorphous silicon film 6 shown in FIG. 2 and before the formation of the silicon nitride film 7. It is preferable to inject it into The dose amount at this time can be set to, for example, about 1 × 10 ¹⁶ atoms / cm ² .

  The N well 3 and the P well 4 can be activated by the heat treatment for forming the silicon oxide film 13.

  Next, the silicon nitride film 12 is removed by dry etching and wet etching. At this time, as shown in FIG. 9, since the silicon oxide film 11 is formed on the surface of the amorphous silicon film pattern 10, the amorphous silicon film pattern 10 is protected from damage caused by etching. Subsequently, the silicon oxide film 5 is removed by etching except under the dummy gate electrode, thereby forming a dummy gate insulating film (FIG. 10).

  Next, the process proceeds to an impurity implantation process into the silicon substrate 1. In this embodiment, after the formation of the pocket region and extension region of the PMOS (or NMOS), the source / drain region is formed, and then the formation of the pocket region and extension region of the NMOS (or PMOS). Source / drain regions are formed.

  For example, when the implantation into the PMOS region is performed first, the NMOS region is covered with a resist film 14 as shown in FIG. Next, by implanting impurities into the silicon substrate 1 in the PMOS region, the PMOS pocket region 15 and the extension region 16 are formed. Specifically, using the dummy gate electrode portion (that is, the oxidized portion of the dummy gate electrode, hereinafter the same) on which the silicon oxide film 13 is formed as a mask, impurities are obliquely upward in the silicon substrate 1 in the PMOS region. Ion implantation. Here, an angle θ (hereinafter referred to as an implantation angle θ) formed by an incident direction A of implanted ions and a direction B perpendicular to the main surface of the silicon substrate 1 is a film thickness of the silicon oxide film 5 as a dummy gate insulating film. And the pattern pitch of the amorphous silicon film pattern 10 as a dummy gate electrode. The implantation angle θ is set so as to be an angle at which a desired impurity profile can be formed at the end portion of the gate electrode formed in a later step. Thus, the PMOS extension region 16 can be formed. Next, the implantation angle θ is increased (for example, θ = 45 degrees), and a PMOS pocket region 15 is formed at the end of the extension region 16.

  After the formation of the pocket region 15 and the extension region 16, the source / drain region 17 is formed without peeling off the resist film 14 (FIG. 12). Specifically, impurities are ion-implanted into the silicon substrate 1 using the gate electrode portion where the silicon oxide film 13 is formed as a mask. In this case, the injection angle θ ′ is smaller than the injection angle θ at the time of pocket injection and extension injection. For example, while the injection angle θ is 45 degrees, the injection angle θ ′ can be 0 degrees.

  After the impurities are ion-implanted in the PMOS region by the above steps, the impurity is also ion-implanted in the NMOS region in the same manner to form the NMOS pocket region 18, the extension region 19 and the source / drain region 20 (FIG. 13).

  Thus, according to the present embodiment, it is possible to reduce the number of manufacturing steps of the semiconductor device as compared with the conventional case. That is, conventionally, after forming a pocket region and an extension region, a sidewall is formed on the side wall portion of the dummy gate electrode, and thereafter, ion implantation for forming a source / drain region is performed using the dummy gate electrode as a mask. It was. On the other hand, according to the present embodiment, pocket regions 15 and 18 and extension regions 16 and 19 can be formed by oblique ion implantation using the dummy gate electrode portion on which silicon oxide film 13 is formed as a mask. Further, by changing the implantation angle, the source / drain regions 17 and 20 can be formed using the same dummy gate electrode portion as a mask. Therefore, the side wall forming step can be eliminated, and the photolithography step for forming the pocket region and the extension region and the photolithography step for forming the source / drain region can be integrated into one. The number can be made smaller than before.

  After completing the PMOS and NMOS impurity implantation steps, the source / drain regions 17 and 20 are activated by heat treatment.

  Next, a silicon nitride film 21 as an etching stopper and an HDP (High Density Plasma) oxide film 22 as an interlayer insulating film are sequentially formed on the entire surface so as to cover the dummy gate electrode, and the structure shown in FIG. 14 is obtained. . The film thickness of the silicon nitride film 21 can be about 30 nm, for example. On the other hand, the thickness of the HDP oxide film 22 can be set to, for example, about 400 nm. Further, these can be formed by a low pressure CVD method or the like. The etching stopper and the interlayer insulating film may be a film made of a material other than the above. In this embodiment, the etching stopper may not be provided.

  Next, the HDP oxide film 22, the silicon nitride film 21, and the silicon oxide film 13 are polished by a CMP (Chemical Mechanical Polishing) method to expose the upper surface of the non-oxidized portion of the dummy gate electrode. As a result, the amorphous silicon film pattern 10 is exposed on the surface as shown in FIG.

  Next, the amorphous silicon film pattern 10 is removed by dry etching.

  After the removal of the amorphous silicon film pattern 10, the exposed silicon oxide film 5 is removed to obtain the structure shown in FIG. In FIG. 16, a trench 23 is a gate trench in which a transistor is actually formed, and a side surface is the silicon nitride film 21 and a bottom surface is the silicon substrate 1.

  After forming the groove 23 as the gate groove by the above process, the gate insulating film 24 is formed on the inner surface of the groove 23. Next, the gate electrode material is embedded in the groove 23 to form the metal gate electrode 25.

  In order to form the metal gate electrode 25, a metal gate electrode material is formed on the entire surface of the HDP oxide film 20 including the groove 23 in FIG. Here, the metal gate electrode material is preferably formed with a thickness greater than the depth of the groove 23. Next, the metal gate electrode material is polished by CMP or the like until the surface of the HDP oxide film 20 is exposed. Thereby, the metal gate electrode 25 can be formed (FIG. 17).

  Next, after forming the HDP oxide film 22 as an interlayer insulating film again, a contact is opened on the metal gate electrode 25 and the source / drain regions 17 and 20, and tungsten or the like is formed inside the contact via a barrier metal. The interconnect 26 is formed by embedding the wiring material (FIG. 18). Thereafter, a wiring structure can be formed through a wiring material deposition and patterning process.

  In FIG. 18, as the gate insulating film 24, a silicon oxide film, a silicon oxynitride film, or the like can be used. As the gate insulating film 24, a high dielectric constant insulating film such as a metal oxide film and a metal silicate film can also be used. Specifically, any one element selected from the group consisting of Si (silicon), Al (aluminum), Hf (hafnium), Zr (zirconium), Sr (strontium), Ti (titanium), and Ta (tantalum). These oxides can be used. Alternatively, an oxide of these elements added with nitrogen may be used as the gate insulating film 24. Further, the gate insulating film 24 is not limited to a single layer film, and may be a laminated film in which two or more kinds of films made of any of the above substances are laminated.

  In FIG. 18, the metal gate electrode 25 may be composed of one kind of metal film or may be composed of a laminated film in which two or more kinds of metal films are laminated. The metal that can be used as the metal gate electrode material is not particularly limited as long as the threshold voltage and the gate wiring resistance of the transistor can be set to desired values. Specifically, Al (aluminum), W (tungsten), Cs (cesium), Co (cobalt), TiN (titanium nitride), or the like can be used.

Embodiment 2. FIG.
FIG. 19 is an example of a cross-sectional view of the semiconductor device according to this embodiment.

  In FIG. 19, the metal gate electrode 55 is provided in a region where the dummy gate electrode (not shown) of the HDP oxide film 50 as an interlayer insulating film is removed. The silicon nitride film 41 as the first spacer provided on the side wall portion of the dummy gate electrode is ion-implanted into the silicon substrate 31 together with the dummy gate electrode to form pocket regions 43 and 46, extension regions 44 and 47, and source / source regions. It is used as a mask when the drain regions 45 and 48 are formed. By adopting such a structure, it is possible to form the source / drain regions following the formation of the pocket region and the extension region only by changing the implantation angle.

  In FIG. 19, a silicon nitride film 52 as a second spacer is provided around the metal gate electrode 55 together with the gate insulating film 54. In other words, the silicon nitride film 52 is provided along the inner wall of the trench from which the dummy gate electrode of the HDP oxide film 50 is removed. The gate insulating film 54 is provided so as to cover the silicon substrate 31 and the silicon nitride film 52 in the trench. By adopting such a structure, the dimension in the width direction of the metal gate electrode 55 can be controlled by controlling the dimension in the width direction of the silicon nitride film. It is possible to form a gate electrode pattern.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. In these drawings, the parts denoted by the same reference numerals as those in FIG. 19 indicate the same parts. In addition, the dimensional ratio of each component in FIGS. 19 to 34 does not limit an actual semiconductor device. In particular, in FIGS. 20 to 34, the portion where the gate electrode is formed is emphasized for the sake of explanation.

  First, as shown in FIG. 20, an element isolation region 32 is formed on the surface of a silicon substrate 31 as a semiconductor substrate. Thus, the silicon substrate 31 is partitioned into the NMOS region and the PMOS region that constitute the CMOS transistor. Thereafter, an N well 33 is formed in the PMOS region, and a P well 34 is formed in the NMOS region.

  Next, a silicon oxide film 35 as a dummy gate insulating material film is formed on the semiconductor substrate 31 (FIG. 21). This embodiment is characterized in that the film thickness of the dummy gate insulating material film is made thicker than before. For example, the silicon oxide film 35 can be a film having a thickness of about 50 nm obtained by oxidizing the surface of the silicon substrate 1 in an oxidizing gas atmosphere at a temperature of about 900 ° C.

  Next, a polysilicon film 36 as a dummy gate electrode material film is formed on the silicon oxide film 35 (FIG. 21). As the polysilicon film 36, for example, a film having a thickness of about 150 nm formed at a temperature of about 620 ° C. can be used.

  After forming the polysilicon film 36, a silicon nitride film 37 as a hard mask material film is formed thereon (FIG. 21). The thickness of the silicon nitride film 37 is appropriately determined in relation to the thickness of the polysilicon film 36. Specifically, the film thickness of the silicon nitride film 37 is preferably a film thickness that disappears when the polysilicon film 36 is etched. For example, when the thickness of the polysilicon film 36 is about 150 nm, the thickness of the silicon nitride film 37 is preferably in the range of 30 nm to 50 nm.

  After forming the silicon nitride film 37, an antireflection film (not shown) may be formed thereon. The antireflection film plays a role of eliminating exposure light reflection at the interface between the resist film and the antireflection film by absorbing exposure light transmitted through the resist film when patterning a resist film to be formed next. As the antireflection film, a film containing an organic substance as a main component can be used. For example, the antireflection film can be formed by a spin coating method or the like.

  Next, a resist film (not shown) is formed on the silicon nitride film 37, and a resist pattern 38 having a desired line width is formed by photolithography to obtain the structure of FIG. Here, the resist pattern 38 corresponds to a dummy gate electrode pattern.

  Next, the silicon nitride film 37 is dry etched using the resist pattern 38 as a mask. Thereafter, by removing the resist pattern 38 that is no longer needed, a silicon nitride film pattern 39 as a hard mask can be formed (FIG. 23). As shown in FIG. 23, the silicon nitride film pattern 39 is a pattern having an opening 39 a on the polysilicon film 36.

  Next, the polysilicon film 36 is dry etched using the silicon nitride film pattern 39 as a mask. As a result, a polysilicon film pattern 40 as a dummy gate electrode is formed in the NMOS region and the PMOS region (FIG. 24). In FIG. 24, the silicon nitride film pattern 39 disappears with the formation of the polysilicon film pattern 40.

  Next, a silicon nitride film 41 as a first spacer is formed on the side wall portion of the polysilicon film pattern 40 (FIG. 25). Specifically, first, a silicon nitride film is deposited on the entire surface so as to bury the polysilicon film pattern 40. For example, a silicon nitride film of about 40 nm is deposited at a film forming temperature of about 500 ° C. Thereafter, the silicon nitride film 41 of FIG. 24 can be formed by performing dry etching of the silicon nitride film while leaving the side wall portion of the polysilicon film pattern 40.

  Next, the silicon oxide film 35 is etched using the dummy gate electrode on which the silicon nitride film 41 is formed as a mask to expose the surface of the silicon substrate 31. At this time, the silicon oxide film 35 under the silicon nitride film 41 is also removed as shown in FIG. This can be performed by dry etching or wet etching in the horizontal direction with respect to the main surface of the silicon substrate 31.

  Next, the process proceeds to an impurity implantation process into the silicon substrate 31. In this embodiment, after the formation of the pocket region and extension region of the PMOS (or NMOS), the source / drain region is formed, and then the formation of the pocket region and extension region of the NMOS (or PMOS). Source / drain regions are formed.

  For example, when the implantation into the PMOS region is performed first, the NMOS region is covered with a resist film 42 as shown in FIG. Next, by implanting impurities into the silicon substrate 31 in the PMOS region, a PMOS pocket region 43 and an extension region 44 are formed.

  Specifically, using the dummy gate electrode on which the silicon nitride film 41 is formed as a mask, impurities are ion-implanted into the silicon substrate 31 in the PMOS region from an obliquely upward direction. Here, an angle θ (hereinafter referred to as an implantation angle θ) formed by the incident direction of the implanted ions and the direction perpendicular to the main surface of the silicon substrate 31 is the film thickness of the silicon oxide film 35 as a dummy gate insulating film, It depends on the pattern pitch of the polysilicon film pattern 36 as a dummy gate electrode. The implantation angle θ is appropriately set so as to be an angle sufficient to form a desired impurity profile at the end of the gate electrode formed in a later step. By doing so, a PMOS extension region 44 can be formed. Next, the implantation angle θ is increased (for example, θ = 45 degrees), and a PMOS pocket region 43 is formed at the end of the extension region 44. A larger value of the injection angle θ is preferable, but about 45 degrees is a maximum value that can be taken practically.

  In the present embodiment, the minimum value of the thickness of the dummy gate insulating material film is determined by the dimension in the width direction of the gate electrode (hereinafter referred to as the gate width) and the implantation angle θ. For example, when the gate width is 30 nm and the implantation angle θ is 45 degrees, the minimum value of the thickness of the dummy gate insulating material film is preferably about 5 nm to 10 nm. When the gate width is 100 nm and the implantation angle θ is 45 degrees, the minimum value of the thickness of the dummy gate insulating material film is preferably about 10 nm to 100 nm.

  On the other hand, the maximum value of the dummy gate insulating material film is largely determined by its workability. That is, if the thickness of the dummy gate insulating material film becomes too large, it becomes difficult to remove by etching, so that workability is lowered. Specifically, the thickness of the dummy gate insulating material film is preferably 100 nm or less. Therefore, when the gate width is 100 nm, the thickness of the dummy gate insulating material film is preferably 10 nm or more and 100 nm or less when the implantation angle θ is 45 degrees.

  Here, in FIG. 27, when the maximum value in the width direction of the silicon nitride film 41 as the first spacer is w and the film thickness of the dummy gate insulating material film is t, the implantation angle θ is 45 degrees. In this case, w = t. On the other hand, when it is desired to set the injection angle θ to a value smaller than 45 degrees, w <t may be set. This makes it possible to reduce the implantation angle without increasing the depth of the impurity region formed in the silicon substrate. As described above, in this embodiment, the first spacer is preferably formed so that the dimension in the width direction is smaller than the film thickness of the dummy gate insulating material film.

  After the formation of the pocket region 43 and the extension region 44, the source / drain region 45 is formed without peeling off the resist film 42 (FIG. 28). Specifically, impurities are ion-implanted into the silicon substrate 31 using the dummy gate electrode on which the silicon nitride film 41 is formed as a mask. In this case, the injection angle θ ′ is smaller than the injection angle θ at the time of pocket injection and extension injection. For example, while the injection angle θ is 45 degrees, the injection angle θ ′ can be 0 degrees.

  After the impurities are ion-implanted in the PMOS region by the above steps, the impurity is also ion-implanted in the NMOS region in the same manner to form the NMOS pocket region 46, the extension region 47, and the source / drain region 48 (FIG. 29).

  Thus, according to the present embodiment, the dummy gate insulating film is formed thick, and the dummy gate insulating film is not provided under the first spacer, so that the pocket injection and extension injection can be performed. The injection angle can be increased. In other words, ions can be implanted into the silicon substrate at a large implantation angle without being shielded by the dummy gate electrode, so that a very shallow impurity profile corresponding to a high integration / high density device can be formed. .

  Further, according to the present embodiment, by changing the implantation angle, ion implantation for forming the source / drain regions can be performed using the same dummy gate electrode as a mask. Therefore, since the photolithography process for forming the pocket region and the extension region and the photolithography process for forming the source / drain regions can be made one, the total number of processes can be reduced as compared with the conventional method. .

  After completing the PMOS and NMOS impurity implantation steps, the source / drain regions 45 and 48 are activated by heat treatment.

  Next, a silicon nitride film 49 as an etching stopper and an HDP (High Density Plasma) oxide film 50 as an interlayer insulating film are sequentially formed on the entire surface so as to cover the polysilicon film pattern 36, and the structure shown in FIG. And The film thickness of the silicon nitride film 49 can be about 30 nm, for example. On the other hand, the thickness of the HDP oxide film 50 can be set to, for example, about 400 nm. Further, these can be formed by a low pressure CVD method or the like. The etching stopper and the interlayer insulating film may be a film made of a material other than the above. In this embodiment, the etching stopper may not be provided.

  Next, the silicon nitride film 49 and the HDP oxide film 50 are polished by CMP (Chemical Mechanical Polishing) to expose the upper surface of the dummy gate electrode. As a result, the polysilicon film pattern 36 is exposed on the surface as shown in FIG.

  Next, after the polysilicon film pattern 36 is removed by dry etching, the silicon oxide film 35 is also removed until a predetermined film thickness is obtained, resulting in the structure shown in FIG. By leaving the silicon oxide film 35, it is possible to prevent the underlying silicon substrate 1 from being etched when the silicon nitride film to be formed next is etched to form the second spacer.

  Next, after a silicon nitride film is deposited to a thickness of about 20 nm so as to fill the opening 51 in FIG. 32, the silicon nitride film and the silicon oxide film 35 are dry-etched. Thereby, as shown in FIG. 33, a silicon nitride film 52 as a second spacer can be formed. In FIG. 33, a groove 53 is a gate groove in which a transistor is actually formed. The side surfaces are silicon nitride films 52 and 41, and the bottom surface is the silicon substrate 21.

  In FIG. 33, the upper tip of the silicon nitride film 52 is formed at a position lower than the surface of the HDP oxide film 50, but the present invention is not limited to this. The top end of the silicon nitride film 52 may be flush with the surface of the HDP oxide film 50.

  Thus, by providing the second spacer in the gate groove, a fine gate electrode pattern can be formed. That is, the dimension in the width direction of the gate groove is determined by the dimension in the width direction of the dummy gate electrode formed through the photolithography process, but the dimension in the width direction of the gate electrode is the second dimension with respect to the gate groove. It is formed in a size that is smaller by the amount of the spacer. In other words, since the dimension in the width direction of the gate electrode can be controlled by controlling the dimension in the width direction of the second spacer, it is possible to form a fine gate electrode pattern that is not subject to the rules of the photolithography process. It becomes possible.

  As described above, the dimension in the width direction of the silicon nitride film 52 may be appropriately set according to the dimension in the width direction of the gate electrode to be formed. In accordance with this, the implantation angle and the implantation energy when forming the pocket regions 43 and 46 and the extension regions 44 and 47 are also set appropriately. Specifically, assuming that the implantation angle is θ, the implantation energy is reduced by cos θ and the dose amount by sin θ, respectively, compared to the case where the implantation angle is 0 degrees.

  After forming the groove 53 as the gate groove by the above process, the gate insulating film 54 is formed on the silicon substrate 31, the silicon nitride films 52 and 41 and the HDP oxide film 50 exposed from the groove 53. Next, the gate electrode material is embedded in the groove 53 to form the metal gate electrode 55.

  In order to form the metal gate electrode 55, a metal gate electrode material is formed on the entire surface of the HDP oxide film 50 including the groove 53 in FIG. Here, the metal gate electrode material is preferably formed with a film thickness thicker than the depth of the groove 53. Next, the metal gate electrode material is polished by CMP or the like until the surface of the HDP oxide film 50 is exposed. Thereby, the metal gate electrode 55 can be formed (FIG. 34).

  Thereafter, HDP oxide film 50 as an interlayer insulating film is formed again in the same manner as described in the first embodiment, and then a contact is opened over metal gate electrode 55 and source / drain regions 45 and 48. The interconnect 56 is formed by embedding a wiring material such as tungsten through the barrier metal in the contact. Thereby, the structure shown in FIG. 19 is obtained. Thereafter, a wiring structure can be formed through a wiring material deposition and patterning process.

  In FIG. 34, as the gate insulating film 54, a silicon oxide film or a silicon oxynitride film can be used. Further, as the gate insulating film 54, a high dielectric constant insulating film such as a metal oxide film or a metal silicate film can be used. Specifically, an oxide of any one element selected from the group consisting of Si (silicon), Al (aluminum), Hf (hafnium), Zr (zirconium), Sr (strontium), and Ti (titanium) is used. be able to. Alternatively, an oxide of these elements added with nitrogen may be used as the gate insulating film 54. Further, the gate insulating film 54 is not limited to a single-layer film, and may be a stacked film in which two or more films made of any of the above substances are combined and stacked.

  In FIG. 34, the metal gate electrode 55 may be composed of one kind of metal film or may be composed of a laminated film in which two or more kinds of metal films are laminated. The metal that can be used as the metal gate electrode material is not particularly limited as long as the threshold voltage and the gate wiring resistance of the transistor can be set to desired values. Specifically, Al (aluminum), W (tungsten), Cs (cesium), Co (cobalt), TiN (titanium nitride), or the like can be used.

  In the present embodiment, the first spacer and the second spacer are formed using the same material, but the present invention is not limited to this. The first spacer and the second spacer may be made of different materials. However, the second spacer needs to be made of a material different from the material constituting the gate insulating film.

7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. FIG. 6 is a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment; It is sectional drawing of the conventional semiconductor device.

Explanation of symbols

1,31,61 Silicon substrate 2,32,62 Element isolation region 3,33,63 N well 4,34,64 P well 5,35 Silicon oxide film 6 Amorphous silicon film 7, 12, 21, 37, 52 Silicon nitride Film 8, 38 Resist pattern 9, 39 Silicon nitride film pattern 10 Amorphous silicon film pattern 11, 13, 41, 49 Silicon oxide film 14, 42 Resist film 15, 18, 43, 46, 67, 68 Pocket region 16, 19, 44, 47, 69, 70 Extension region 17, 20, 45, 48, 71, 72 Source / drain region 22, 50 HDP oxide film 23, 53 Groove 24, 54 Gate insulating film 25, 55 Metal gate electrode 26, 56 Interconnect 36 Polysilicon film 40 Polysilicon film pattern 6 Dummy gate insulating film 66 dummy gate electrode 73 side wall

Claims (12)

Forming an element isolation region in a semiconductor substrate and partitioning it into an NMOS region and a PMOS region;
Forming a dummy gate insulating material film on the semiconductor substrate;
Forming an amorphous silicon film on the dummy gate insulating material film;
Forming a hard mask material film on the amorphous silicon film;
Etching the hard mask material film by a photolithography method to form a hard mask having an opening on the amorphous silicon film;
Etching the amorphous silicon film using the hard mask as a mask to form a dummy gate electrode;
Forming a silicon oxide film on the surface of the dummy gate electrode;
Forming an antioxidant film on the dummy gate insulating film so as to cover the dummy gate electrode after the silicon oxide film is formed;
Etching back the antioxidant film to expose the upper portion of the dummy gate electrode;
Heating and oxidizing the exposed dummy gate electrode to form an oxidized portion having a dimension at least in the width direction larger than the non-oxidized portion;
Removing the antioxidant film;
Etching the dummy gate insulating material film to form a dummy gate insulating film;
Injecting impurities into the PMOS region of the semiconductor substrate from the obliquely upward direction of the semiconductor substrate using the oxidized portion of the dummy gate electrode as a mask, and forming a PMOS extension region;
Injecting impurities into the PMOS region of the semiconductor substrate from an obliquely upward direction of the semiconductor substrate using the oxidized portion of the dummy gate electrode as a mask, and forming a PMOS pocket region at an end of the PMOS extension region;
Using the oxidized portion of the dummy gate electrode as a mask, impurities are implanted into the PMOS region of the semiconductor substrate at an angle smaller than the implantation angle when forming the PMOS extension region and the implantation angle when forming the PMOS pocket region. Forming a PMOS source / drain region;
Implanting impurities into the NMOS region of the semiconductor substrate from an obliquely upward direction of the semiconductor substrate using the oxidized portion of the dummy gate electrode as a mask, and forming an NMOS extension region;
Injecting impurities into the NMOS region of the semiconductor substrate from an obliquely upward direction of the semiconductor substrate using the oxidized portion of the dummy gate electrode as a mask, and forming an NMOS pocket region at an end of the NMOS extension region;
Using the oxidized portion of the dummy gate electrode as a mask, impurities are implanted into the NMOS region of the semiconductor substrate at an angle smaller than the implantation angle when forming the NMOS extension region and the implantation angle when forming the NMOS pocket region. And forming a source / drain region of the NMOS,
Forming an interlayer insulating film so as to cover the dummy gate electrode;
Polishing the oxidized portion of the interlayer insulating film and the dummy gate electrode to expose the upper surface of the non-oxidized portion of the dummy gate electrode;
Removing the exposed dummy gate electrode to expose the dummy gate insulating film;
Removing the exposed dummy gate insulating film to form a groove reaching the semiconductor substrate;
Forming a gate insulating film on the inner surface of the groove,
And a step of forming a metal gate electrode so as to fill the groove after the gate insulating film is formed.   The method of manufacturing a semiconductor device according to claim 1, further comprising a step of injecting silicon into the amorphous silicon film before the step of thermally oxidizing the dummy gate electrode.   The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the hard mask material film is a step of depositing a silicon nitride film at a temperature of 550 ° C. or lower.   The method of manufacturing a semiconductor device according to claim 1, wherein the antioxidant film is a silicon nitride film. Forming an element isolation region in a semiconductor substrate and partitioning it into an NMOS region and a PMOS region;
Forming a dummy gate insulating material film on the semiconductor substrate;
Forming a dummy gate electrode on the dummy gate insulating material film;
Forming a first spacer on the side wall of the dummy gate electrode;
Removing the dummy gate insulating material film except under the dummy gate electrode, and forming a dummy gate insulating film;
Using the dummy gate electrode and the first spacer as a mask, implanting impurities into the PMOS region of the semiconductor substrate from an obliquely upward direction of the semiconductor substrate, and forming a PMOS extension region;
Implanting impurities into the PMOS region of the semiconductor substrate from an obliquely upward direction of the semiconductor substrate using the dummy gate electrode and the first spacer as a mask to form a PMOS pocket region at the end of the PMOS extension region When,
Using the dummy gate electrode and the first spacer as a mask, impurities are introduced into the PMOS region of the semiconductor substrate at an angle smaller than an implantation angle when forming the PMOS extension region and an implantation angle when forming the PMOS pocket region. And forming a PMOS source / drain region; and
Using the dummy gate electrode and the first spacer as a mask, implanting impurities into the NMOS region of the semiconductor substrate from an obliquely upward direction of the semiconductor substrate, and forming an NMOS extension region;
Using the dummy gate electrode and the first spacer as a mask, implanting impurities into the NMOS region of the semiconductor substrate from an obliquely upward direction of the semiconductor substrate to form an NMOS pocket region at the end of the NMOS extension region When,
Using the dummy gate electrode and the first spacer as a mask, impurities are introduced into the NMOS region of the semiconductor substrate at an angle smaller than an implantation angle when forming the NMOS extension region and an implantation angle when forming the NMOS pocket region. And forming NMOS source / drain regions; and
Forming an interlayer insulating film so as to cover the dummy gate electrode;
Polishing the interlayer insulating film to expose the upper surface of the dummy gate electrode;
Removing the exposed dummy gate insulating film to form a groove reaching the dummy gate insulating film;
Removing the dummy gate insulating film exposed from the trench leaving a predetermined thickness;
Forming a second spacer material film so as to fill the groove;
Etching the second spacer material film and the gate insulating film to expose the semiconductor substrate and forming a second spacer on a side surface of the groove;
Forming a gate insulating film on the inner surface of the groove,
And a step of forming a metal gate electrode so as to fill the trench after the gate insulating film is formed.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the dummy gate insulating material film has a thickness of 10 nm to 100 nm.   7. The method of manufacturing a semiconductor device according to claim 5, wherein the dummy gate electrode is made of polysilicon.   The method of manufacturing a semiconductor device according to claim 5, wherein the first spacer is made of a silicon nitride film.   The method of manufacturing a semiconductor device according to claim 5, wherein the second spacer is made of a silicon nitride film.   The gate insulating film is a single-layer film selected from the group consisting of a silicon oxide film, an aluminum oxide film, a hafnium oxide film, a zirconium oxide film, a strontium oxide film, a titanium oxide film, and a nitrogen-added film thereof, or 2 The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a laminated film composed of two or more films. A first spacer provided on the side wall of the dummy gate electrode;
A pocket region, an extension region, and a source / drain region formed by ion implantation using the dummy gate electrode and the first spacer as a mask in a semiconductor substrate;
An interlayer insulating film formed by embedding the dummy gate electrode and the first spacer on the semiconductor substrate;
A second spacer provided along an inner wall of the groove in the groove from which the dummy gate electrode of the interlayer insulating film is removed;
A gate insulating film covering the semiconductor substrate and the second spacer in the groove;
A semiconductor device comprising: a metal gate electrode provided in the trench through the gate insulating film.   The semiconductor device according to claim 11, wherein an insulating film is provided between the semiconductor substrate and the second spacer.

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