JP2005094484A - Phase difference detection circuit, clock skew correction circuit, phase difference detection method, and clock skew correction method - Google Patents

Abstract

A phase difference detection circuit capable of detecting a phase difference between two signals without using a high-speed clock is provided.
Delay adjustment cells 210 to 215, 230 to 235 for delaying a supply clock SCLK by a predetermined value, and a plurality of signals whose phases are shifted by a predetermined value by these delay adjustment cells are used as clock signals, respectively, and a feedback clock MCLK_1 is used. Flip-flops 200 to 208 and 220 to 228 that respectively take in at predetermined timings are provided, and a phase difference between the supply clock SCLK and the feedback clock MCLK_1 is detected.
[Selection] Figure 5

Description

  The present invention relates to a phase difference detection circuit and a phase difference detection method for detecting a phase difference between two signals. The present invention also relates to a clock skew correction circuit and a clock skew correction method for correcting clock skew.

  Conventionally, when designing a layout of a semiconductor integrated circuit (LSI), in order to reduce the number of man-hours required for the design and facilitate verification, each element is not laid out on the chip one by one, but to a certain degree of logic function. Generally, after layout design for each functional block, that is, for each functional block is completed in advance, the arrangement and wiring between these functional blocks are performed.

  In recent years, as the degree of integration of LSIs has increased and the size has increased, the wiring length in a chip, particularly the wiring for supplying clock signals to each functional block, has become longer, and the delay of the clock signal cannot be ignored. Yes. In other words, the phases of the clock signals supplied to the plurality of functional blocks are shifted between the functional blocks, which may cause a problem in the operation of the entire system LSI.

  As a technology to adjust the clock phase difference in each functional block, a supply clock and a feedback clock corresponding to this supply clock are generated, and the phase difference of the clock signal transmitted via the feedback clock is detected using a counter There is known a technique in which a clock skew correction circuit is configured by providing a phase difference detecting means for controlling and a control means for adjusting a clock signal delay time based on the phase difference detection result (for example, Patent Document 1). reference).

JP-A-6-273478 (FIG. 9)

  However, in the above-described conventional technique, for example, when the phase difference between the supply clock and the feedback clock is 1 (ns), in order to detect this phase difference, the measurement counter has an ultrafast clock of 1 (GHz). In addition, it is considered that the power consumption as a chip is greatly increased because an ultrahigh-speed clock is used.

  The present invention has been made in view of the above-described conventional circumstances, and an object thereof is to provide a phase difference detection circuit and a phase difference detection method capable of detecting a phase difference between two signals without using a high-speed clock. Another object of the present invention is to provide a clock skew correction circuit and a clock skew correction method using the phase difference detection circuit.

  The phase difference detection circuit according to the present invention is a phase difference detection circuit for detecting a phase difference between a first signal and a second signal, a plurality of delay means for delaying one signal, and the other signal for each delay means. And a plurality of flip-flops fetched at the output timing. According to this configuration, the phase difference can be detected by comparing the first signal and the second signal by fetching the other signal into the flip-flop at the timing when one signal is sequentially delayed. The phase difference can be detected without the need for a high-speed counter even in the case of high.

  The clock skew correction circuit according to the present invention detects a phase difference between a supply clock supplied to a functional block and a feedback clock fed back from the functional block, and the detected phase difference. And a delay adjustment circuit for adjusting the delay of the supply clock supplied to the functional block based on the above.

  The clock skew correction circuit according to the present invention is the clock skew correction circuit according to claim 2, wherein the delay adjustment circuit is based on a plurality of delay means for delaying the supplied clock at different times and the phase difference. And a selector for selecting a supply clock having a delay time necessary for delay adjustment of the supply clock from the output of each delay means.

  The phase difference detection method of the present invention is a phase difference detection method for detecting a phase difference between a first signal and a second signal, wherein one signal is sequentially delayed, and the other signal and each delayed signal are Each is a comparison. According to this configuration, one signal can be sequentially delayed, and the other signal can be compared with each delayed signal to detect a phase difference. Therefore, even when the signal frequency is high, a high-speed counter is not required. In addition, the phase difference can be detected.

  The phase difference detection step of detecting a phase difference between a supply clock supplied to the functional block and a feedback clock fed back from the functional block by the phase difference detection method according to claim 4, And a delay adjustment step of delay adjusting a supply clock to be supplied to the functional block based on the detected phase difference.

  Furthermore, in the clock skew correction method of the present invention, the delay adjustment step includes a step of delaying the supply clock by different times, and a delay adjustment of the supply clock from a plurality of supply clocks having different delay times based on the phase difference. Selecting a supply clock having a necessary delay time.

  According to the present invention, it is possible to provide a phase difference detection circuit and a phase difference detection method capable of detecting a phase difference between two signals without using a high-speed clock. Further, it is possible to provide a clock skew correction circuit and a clock skew correction method for correcting a clock skew using the phase difference detection circuit and the phase difference detection method.

  In addition, according to the present invention, by providing a phase difference detection circuit and a delay adjustment circuit for each clock to constitute a clock skew correction circuit, delay adjustment is performed for each clock even when there are a plurality of clock signals. Therefore, the clock skew can be adjusted. Furthermore, since the clock skew adjustment, which has been performed on the layout so far, is automatically performed by the circuit, the number of steps can be greatly reduced.

  FIG. 1 is a diagram showing a configuration of a clock skew correction circuit for explaining an embodiment of the present invention. Clocks having the same phase are supplied to functional blocks 30 and 40 having different wiring lengths from the clock supply source 20. An example in which clock phase difference adjustment is performed to supply power will be described.

  In the present embodiment, the phase difference is adjusted by adjusting the phase difference between the clock SCLK supplied from the clock supply source 20 to the clock skew correction circuit 10 and the feedback clocks MCLK_1 and MCLK_2 fed back from the functional blocks 30 and 40. The clock skew is corrected by supplying the clocks SCLK_1 and SCLK_2 to the function blocks 30 and 40, respectively.

  FIG. 2 is a diagram illustrating clock timing before the clock phase difference adjustment in the configuration example of FIG. The period of the supply clock SCLK is T, and before the clock phase difference adjustment, the clock SCLK_1 at the point S_1 and the clock SCLK_2 at the point S_2 in FIG. 1 have the same phase as the supply clock SCLK.

  Further, the feedback clock MCLK_1 at the point E_1 becomes a clock delayed from the supply clock SCLK by a round trip value A of the wiring delay (A / 2) to the functional block 30, and the feedback clock MCLK_2 at the point E_2 The clock is delayed from the supply clock SCLK by the round trip value C of the wiring delay (C / 2).

  In FIG. 1, point S_1 is an output terminal of the clock skew correction circuit 10 for the clock SCLK_1 supplied to the functional block 30, and point S_2 is an output of the clock SCLK_2 to be supplied to the functional block 40 in the clock skew correction circuit 10. Is the end.

  The point E_1 is an input end of the feedback clock MCLK_1 fed back from the functional block 30 in the clock skew correction circuit 10, and the point E_2 is an input end of the feedback clock MCLK_2 fed back from the functional block 40 in the clock skew correction circuit 10. is there.

In FIG. 2, time A is a clock delay time when reciprocating between the clock skew correction circuit 10 and the functional block 30, and time C is reciprocating between the clock skew correction circuit 10 and the functional block 40. This is the clock delay time. Therefore, time B and time D shown in FIG.
B = TA
D = TC
It becomes. However, T is the cycle of the supply clock SCLK.

  FIG. 3 is a diagram illustrating clock timing after the clock phase difference adjustment in the configuration example of FIG. For the clock SCLK_1 supplied to the functional block 30, the wiring delay value A / 2 from the point M_1 to the point E_1 and the time B from the rise of the feedback clock MCLK_1 before adjustment to the next rise of the supply clock SCLK are added. Delay the time corresponding to the value.

  For the clock SCLK_2 supplied to the functional block 40, the wiring delay value C / 2 from the point M_2 to the point E_2 and the time D from the rise of the feedback clock MCLK_2 before adjustment to the next rise of the supply clock SCLK are obtained. The time corresponding to the added value is delayed. Note that point M_1 is an input end of the clock SCLK_1 in the functional block 30, and point M_2 is an input end of the clock SCLK_2 in the functional block 40.

As shown in FIG. 3, the clock SCLK_1 delayed by the value of (A / 2) + B by the clock skew correction circuit 10 reaches the functional block 30, and the wiring delay value A / 2 from the point S_1 to the point M_1. As a result, the clock is delayed by one clock period T. That is,
(A / 2) + B + A / 2 = A + B = T
It becomes.

Further, the clock SCLK_2 delayed by the value of (C / 2) + D by the clock skew correction circuit 10 is also delayed by the wiring delay value C / 2 from the point S_2 to the point M_2 before reaching the function block 40. Specifically, the clock is delayed by one clock cycle T. That is,
(C / 2) + D + C / 2 = C + D = T
It becomes.

  As described above, when the clock supplied from the clock supply source 20 reaches the functional blocks 30 and 40, both are adjusted by the clock skew correction circuit 10 so as to be delayed by one clock cycle T from the supply clock SCLK. The phases of the clocks reaching the blocks 30 and 40 can be aligned.

  Next, the configuration and operation of the clock skew correction circuit 10 of this embodiment will be described. FIG. 4 is a block diagram for explaining the configuration of the clock skew correction circuit 10 of the present embodiment.

  As shown in FIG. 4, the clock skew correction circuit 10 includes a phase difference detection circuit 100 and a delay adjustment circuit 101 for clock adjustment of the clock SCLK_1 supplied to the functional block 30, and a clock SCLK_2 supplied to the functional block 40. A phase difference detection circuit 102 for adjustment and a delay adjustment circuit 103 are provided.

  Since the same clock adjustment method is applied to the clock SCLK_1 supplied to the functional block 30 and the clock SCLK_2 supplied to the functional block 40, the clock adjustment of the clock SCLK_1 supplied to the functional block 30 will be described below. Do.

  The phase difference detection circuit 100 has a phase difference (phase difference A) between the rising edge of the clock SCLK supplied from the clock supply source 20 to the clock skew correction circuit 10 and the rising edge of the feedback clock MCLK_1 fed back from the functional block 30. Signal (M1_0 to M1_8) and signals (M1_10 to M1_18) indicating the phase difference (phase difference B) between the feedback clock MCLK_1 and the next rising edge of the supply clock SCLK are detected. Output to the delay adjustment circuit 101.

  The delay adjustment circuit 101 adjusts the phase of the supply clock SCLK based on the detected values of the signals M1_0 to M1_8 and M1_10 to M1_18, and a function block is used to adjust the phase of the supply clock SCLK (clock SCLK_1). Output to 30.

  FIG. 5 is a schematic configuration diagram of the phase difference detection circuit 100. The phase difference detection circuit 100 includes delay adjustment cells 210 to 215 and 230 to 235 having a delay value X, delay adjustment cells 216, 217, 236, and 237 having a delay value Y (= 3X), flip-flops ( FF) 200 to 208 and 220 to 228.

  The phase difference detection circuit 100 detects the phase difference A between the supply clock SCLK and the feedback clock MCLK_1 by the FFs 200 to 208, the delay adjustment cells 210 to 215, and the delay adjustment cells 216 and 217. The FF 200 uses the supply clock SCLK as a clock signal. The FF 201 uses a signal delayed by the delay value X of the delay adjustment cell 210 from the supply clock SCLK as a clock signal.

  The FF 202 uses a signal delayed from the supply clock SCLK by the total delay value 2X by the delay adjustment cells 210 and 211 as a clock signal. Similarly, the FF 203 to FF 208 use a signal delayed by a delay value obtained by adding the delay value X of each delay adjustment cell as a clock signal. With this circuit configuration, the FF 200 to FF 208 generate signals M1_0 to M1_8. A specific method for detecting the phase difference A based on the signals M1_0 to M1_8 will be described later.

  On the other hand, the phase difference detection circuit 100 uses the FFs 220 to 228, the delay adjustment cells 230 to 235, and the delay adjustment cells 236 and 237 to obtain the phase difference B between the rising edge of the feedback clock MCLK_1 and the next rising edge of the supply clock SCLK. To detect. The FF 220 uses the feedback clock MCLK_1 as a clock signal. The FF 221 uses a signal delayed by the delay value X of the delay adjustment cell 230 from the feedback clock MCLK_1 as a clock signal.

  The FF 222 uses a signal delayed from the feedback clock MCLK_1 by the total delay value 2X of the delay adjustment cells 230 and 231 as a clock signal. Similarly, the FF 223 to the FF 228 use a signal delayed by a delay value obtained by adding the delay value X of each delay adjustment cell as a clock signal. With this circuit configuration, the FFs 220 to F228 generate signals M1_10 to M1_18. A specific method for detecting the phase difference B based on the signals M1_10 to M1_18 will be described later.

  FIG. 6 is a timing diagram of clocks in the phase difference detection circuit 100. FIGS. 4-1 to 4-9 in FIG. 6A show the data fetch timings in the FF 200 to FF 208, respectively.

  As shown in FIG. 4B, the data fetch timing of the supply clock SCLK in the FF 201 is delayed by the delay value X of the delay adjustment cell 210 from the data fetch timing of the supply clock SCLK in the FF 200. Similarly, the data fetch timing of the supply clock SCLK in the FF 202 to FF 208 is delayed by the sum of the delay values of the delay adjustment cells.

  In the phase difference detection circuit 100, since the clock input timing (data capture timing) to each FF is shifted by the delay adjustment cells 210 to 217, the value output from each FF changes before and after the change of the feedback clock MCLK_1. To do. That is, the outputs from the FFs are switched such that the outputs of the FFs 200 and 201 are 0 while the outputs of the FFs 202 to 208 are 1.

  Further, FIGS. 4-11 to 4-19 in FIG. 6B show the data fetch timings in the FFs 220 to 228, respectively. As shown in FIG. 4-12, the data fetch timing of the clock MCLK_1 in the FF 221 is delayed by the delay value X of the delay adjustment cell 230 from the data fetch timing of the feedback clock MCLK_1 in the FF 220. Similarly, the data fetch timing in the FFs 222 to 228 is delayed by the sum of the delay values of the delay adjustment cells.

  In the phase difference detection circuit 100, since the clock input timing (data capture timing) to each FF is shifted by the delay adjustment cells 230 to 237, the value output from each FF changes before and after the change of the supply clock SCLK. To do. That is, the outputs from the FFs are switched such that the outputs of the FFs 220 to 227 are 0 while the output of the FF 228 is 1.

  Next, the phase difference detection operation in the phase difference detection circuit 100 will be specifically described. FIG. 7 is a diagram illustrating timing when the phase difference A is detected by the phase difference detection circuit 100.

  As described above, the period of the supply clock SCLK is T, and the feedback clock MCLK_1 is assumed to be delayed by the time A from the supply clock SCLK. The delay values of the delay adjustment cells 210 to 215 and 230 to 235 are set to X = T / 10, and the delay values of the delay adjustment cells 216, 217, 236, and 237 are set to Y = 3X = 3T / 10. Hereinafter, a case where the phase difference between the supply clock SCLK and the feedback clock MCLK_1 has the relationship shown in FIG. 7 will be described.

  As shown in FIG. 5, the clocks SCLK (200) to SCLK (208) delayed by the delay value X are input to the FFs 200 to 208, and the data of the feedback clock MCLK_1 is taken in at the rising edge. Therefore, the output signals M1_0 to M1_8 of the FFs 200 to 208 are “0”, “0”, “0”, “0”, “1”, “1”, “1”, “1”, “1”, respectively. That is, “00001111” is obtained.

Here, when bit numbers are assigned to the signals M1_0 to M1_8 in the order of 0, 1, 2,..., 4 bits are changed to “1”, and the feedback clock MCLK_1 is 4 bits from the supply clock SCLK. Because it ’s a minute late,
A = 4X = 4 · T / 10 = 2T / 5
Can be detected.

  FIG. 8 is a diagram illustrating timing when the phase difference detection circuit 100 detects the phase difference B. Hereinafter, a case where the phase difference between the rising edge of the feedback clock MCLK_1 and the next rising edge of the supply clock SCLK has the relationship shown in FIG. 8 will be described.

  In this case, as shown in FIG. 5, the feedback clocks MCLK (220) to MCLK (228) delayed by the delay value X are input to the FFs 220 to 228, and the data of the supply clock SCLK is taken in at the rising edge. Therefore, the output signals M1_10 to M1_18 of the FFs 220 to 228 are “1”, “0”, “0”, “0”, “0”, “0”, “1”, “1”, “1”, respectively. That is, “100000111”.

Here, when bit numbers are assigned to the signals M1_10 to M1_18 in order, such as 0, 1, 2,..., 6 bits are changed to “1” corresponding to the next clock edge. Since the clock SCLK (next clock edge) is delayed by 6 bits from the feedback clock MCLK_1,
B = 6X = 6 · T / 10 = 3T / 5
Can be detected.

  FIG. 9 is a schematic configuration diagram of the delay adjustment circuit 101. The delay adjustment circuit 101 includes delay buffers 301 to 309 having different delay values and a block 300 including a selector 320 that uses the output signals M1_0 to M1_8 from the phase difference detection circuit 100 as inputs, and delays having different delay values. The block 310 includes buffers 311 to 319 and a selector 330 that uses the output signals M1_10 to M1_18 from the phase difference detection circuit 100 as inputs.

  In the block 300, first, the delay buffers 301 to 309 delay the input supply clock SCLK by a predetermined value, respectively. A plurality of signals having different phases generated by the delay buffers 301 to 309 are input to the selector 320 as clock signals.

  Based on the values of the output signals M1_0 to M1_8 from the phase difference detection circuit 100, the selector 320 selects a supply clock having a delay time necessary for delay adjustment of the supply clock, that is, a clock signal with an A / 2 delay. The clock DSCLK_1 delayed by A / 2 from the supply clock SCLK is output to the block 310.

  In block 310, first, the delay buffers 311 to 319 respectively delay the clock DSCLK_1 input from the block 300 by a predetermined value. A plurality of signals having different phases generated by the delay buffers 311 to 319 as described above are input to the selector 330 as clock signals.

  Based on the values of the output signals M1_10 to M1_18 from the phase difference detection circuit 100, the selector 330 selects a supply clock having a delay time necessary for delay adjustment of the supply clock, that is, a clock signal with a B delay. The clock SCLK_1 delayed by (A / 2) + B from the supply clock SCLK is output to the functional block 30.

Since the wiring delay from the delay adjustment circuit 101 to the functional block 30 is A / 2, the clock SCLK_1 is a clock delayed by one clock cycle T from the supply clock SCLK when reaching the functional block 30. That is, the clock reaching the functional block 30 is relative to the supply clock SCLK.
(A / 2) + B + A / 2 = A + B = T
As a result, the phase of the supply clock SCLK coincides.

  As described above, the clock skew correction circuit 10 causes the phase difference detection circuit 100 and the delay adjustment circuit 101 to match the phase of the clock SCLK supplied from the clock supply source 20 with the phase of the clock SCLK_1 that has reached the functional block 30. Further, although the case where the phase of the clock SCLK_1 is adjusted has been described, the phase of the clock SCLK_2 supplied to the functional block 40 can be similarly adjusted by the phase difference detection circuit 102 and the delay adjustment circuit 103. Therefore, the clock SCLK_1 and the clock SCLK_2 are in phase with the supply clock SCLK when they reach the functional blocks 30 and 40, respectively. Thus, according to the clock skew correction circuit of the present embodiment, the phase difference detection circuit can detect the phase difference of the clock without using a high-speed clock, and can align the phase of the clock reaching each functional block. .

  In the clock skew correction circuit of the present embodiment, a clock skew correction circuit is configured by providing a phase difference detection circuit and a delay adjustment circuit for each clock supplied to each functional block, so that a clock is corrected for a plurality of clock signals. Since the delay can be adjusted every time, a skew (clock phase shift) between a plurality of functional blocks can be corrected.

  Further, according to the clock skew correction circuit of the present embodiment, the clock skew adjustment that has been performed on the layout can be automatically performed by the circuit, so that the number of steps for clock skew adjustment is greatly reduced. be able to.

  In addition, according to the present invention, it is possible to easily improve the phase difference detection accuracy without increasing the clock speed by increasing the number of flip-flops constituting the phase difference detection circuit.

  The phase difference detection circuit and the phase difference detection method of the present invention have the effect of detecting the phase difference between two signals without using a high-speed clock. For example, a clock skew correction circuit and a clock skew correction method for correcting a clock skew Useful for.

The figure which shows the structure of the clock skew correction circuit for describing one Embodiment of this invention The figure which shows the timing of the clock before a clock phase difference adjustment in the structural example of FIG. The figure which shows the timing of the clock after a clock phase difference adjustment in the structural example of FIG. The block diagram for demonstrating the structure of the clock skew correction circuit 10 of this embodiment. Schematic configuration diagram of the phase difference detection circuit 100 Timing diagram of clock in phase difference detection circuit 100 The figure which shows the timing in the case of detecting the phase difference A in the phase difference detection circuit 100 The figure which shows the timing in the case of detecting the phase difference B in the phase difference detection circuit 100 Schematic configuration diagram of the delay adjustment circuit 101

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Clock skew correction circuit 20 Clock supply source 30,40 Functional block 100,102 Phase difference detection circuit 101,103 Delay adjustment circuit 200-208,220-228 Flip-flop (FF)
210 to 217, 230 to 237 Delay adjustment cell 300, 310 Blocks 301 to 309, 311 to 319 Delay buffer 320, 330 Selector SCLK supply clock SCLK_1, SCLK_2 Phase difference adjustment clock MCLK_1, MCLK_2 Feedback clock

Claims (6)

In the phase difference detection circuit that detects the phase difference between the first signal and the second signal,
A plurality of delay means for delaying one signal;
A phase difference detection circuit comprising a plurality of flip-flops that take in the other signal at the output timing of each delay means. The phase difference detection circuit according to claim 1 for detecting a phase difference between a supply clock supplied to the functional block and a feedback clock fed back from the functional block;
A clock skew correction circuit comprising: a delay adjustment circuit that delay-adjusts a supply clock supplied to the functional block based on the detected phase difference. The clock skew correction circuit according to claim 2, wherein the delay adjustment circuit includes:
A plurality of delay means for delaying the supply clock by different times;
A clock skew correction circuit comprising: a selector that selects a supply clock having a delay time necessary for delay adjustment of the supply clock from an output of each delay means based on the phase difference. In a phase difference detection method for detecting a phase difference between a first signal and a second signal,
A phase difference detection method that sequentially delays one signal and compares the other signal with each delayed signal. A phase difference detecting step of detecting a phase difference between a supply clock supplied to the functional block and a feedback clock fed back from the functional block by the phase difference detecting method according to claim 4;
And a delay adjustment step of adjusting a delay of a supply clock supplied to the functional block based on the detected phase difference. 6. The clock skew adjustment method according to claim 5, wherein the delay adjustment step includes:
Delaying each of the supply clocks by different times;
Selecting a supply clock having a delay time required for delay adjustment of the supply clock from a plurality of supply clocks having different delay times based on the phase difference.

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