JP2005157781A - Information processor and information processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor and information processing method for shortening a write time for writing data into a flash memory. <P>SOLUTION: An information processor 100 is provided with a detecting means which detects the bit distribution of data, a determining means which determines whether or not inversion is necessary based on the detection result of the detecting means and a converting means which inversely converts the value of the data. When data are written, the value of 0 is detected in the data to be written by the determining means, and whether the number of the data values which are 0 is large or not is determined by the determining means, and when the number of 0 is large, it is determined that inversion is necessary, and the values of the data are inversely converted with the same bit length, and written in a storage means. Also, when the data are read, the inversely converted data values read from the storage means are converted into an original value, and outputted. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an information processing apparatus and information processing method for writing or reading data in a memory such as a flash ROM. Specifically, an information processing apparatus having a storage means whose read / write processing time differs depending on the data value at least one of data reading and writing is provided with a conversion means for converting the data value, and the data value is the same during writing. By converting the value of the converted data read from the storage means to the original value and outputting it at the time of reading and writing to the storage means after conversion by the bit length, data that takes time to write can be obtained. The present invention relates to an information processing apparatus or the like that can shorten the writing time of a flash memory or the like by performing conversion after writing into data with a short writing time.

  Flash EEPROM (Flash Electrically Erasable and Programmable Read Only Memory) is also called flash memory or flash ROM, and writing is possible in bit units, but erasing is in all bits or block units (that is, a unit of a number of bits). This is a read-only memory that can be electrically written and erased.

  Conventionally, the created data is written as it is in the writing of the flash memory. Therefore, when there is a lot of write data, there is a problem that it takes time to write.

In order to solve this problem, a program voltage control method that can shorten the program time of the memory has been proposed (see, for example, Patent Document 1).
In this case, when data is programmed in the nonvolatile memory cell, the program voltage is applied to the memory cell a plurality of times while gradually increasing the program voltage. At this time, the increment of the program voltage is set to the first voltage until the threshold voltages of all the memory cells to be programmed reach the initial value. Thereafter, the increment of the program voltage is set to the second voltage until the threshold voltage reaches the target value. By raising the program voltage without changing the increment, the threshold voltage of the memory cell can be brought close to the target value with a small number of programs. Further, by setting the increment of the program voltage to the second voltage after the threshold voltage exceeds the initial value, the error of the threshold voltage with respect to the target value can be minimized. As a result, the memory cell programming time can be reduced.

Japanese Unexamined Patent Publication No. 2003-173688 (Pages 6, 7 and 1)

  However, in the flash memory, when writing data, writing time of 0 is longer than writing time of 1, so when the value of writing data is large, the created data is written as it is as before. However, the time required for writing becomes long, and there is a problem that it takes time for writing.

  In the case of Patent Document 1, the program time of the memory can be shortened by controlling the program voltage of the nonvolatile memory, but the complexity of the circuit and voltage control is a problem.

  Accordingly, an object of the present invention is to provide an information processing apparatus and an information processing method capable of shortening a writing time when writing data to a flash memory or the like.

  An information processing apparatus according to the present invention comprises a conversion means for converting a data value in an information processing apparatus having a storage means whose read / write processing time differs depending on a value of the data at least one of reading and writing of the data, The conversion means converts the data value with the same bit length at the time of writing and writes it to the storage means, and at the time of reading, converts the converted data value read from the storage means to the original value and outputs it It is.

  For example, the information processing apparatus determines a detection unit that detects a bit distribution of data, a determination unit that determines whether conversion processing is necessary based on a detection result of the detection unit, and a determination unit that determines that conversion processing is necessary. In the case, the setting means for setting the control information indicating the conversion process to the data and the control information detection means for detecting the control information indicating the conversion process from the data are further provided, and the determination means When the appearance frequency is high, it is determined that processing is necessary. The storage means is a flash memory.

  The information processing method according to the present invention is an information processing method in an information processing apparatus having an information processing apparatus having a read / write processing time that differs depending on a value of the data at least one of reading and writing of the data. The method includes a step of converting the bit length and writing to the storage unit, and a step of converting the value of the converted data read from the storage unit into an original value and outputting at the time of reading.

  For example, the information processing method includes a step of detecting a bit distribution of data, a determination step of determining whether or not a data value conversion process is necessary based on the detection result, and a case where the conversion process is determined to be necessary A setting step for setting control information indicating conversion processing, and a detection step for detecting control information from data at the time of writing. When control information is detected in this detection step, the value of the data is set to the same bit. The length is converted and written to the storage means.

  According to the present invention, the information processing apparatus having a storage means whose read / write processing time differs depending on the data value at least one of reading and writing of information is provided with a conversion means for converting the value of the data. Converts the value with the same bit length and writes it to the storage means, and at the time of reading, converts the value of the converted data read from the storage means to the original value and outputs the data, which takes time to write Conversion is made to data with a short writing time, and writing is performed. Thereby, it is possible to reduce the writing time of a memory such as a flash ROM by converting data that takes a long time to write into data having a short writing time.

  In the present invention, for example, the information processing apparatus includes a detection unit that detects a bit distribution of data, a determination unit that determines whether inversion processing is necessary based on a detection result by the detection unit, and a determination unit When it is determined that the conversion process is necessary, setting means for setting control information indicating the conversion process in the data and control information detection means for detecting control information indicating the conversion process from the data are further provided. A value of 0 is detected in the data to be written by the detecting means, and it is determined whether or not the data value is large by the determining means. If there are many 0, it is determined that inversion processing is necessary, and conversion processing to data is performed by the setting means. If the control information is set, and the control information is detected at the time of writing, the data value is inverted and converted to the same bit length and written to the storage means, and at the time of reading, the inverted conversion read from the storage means The converted data value is converted to the original value and output. As a result, it is possible to reduce the writing time of a memory such as a flash ROM, and it is possible to automatically detect the bit distribution of data and determine whether the inversion process is necessary.

  According to the present invention, the information processing apparatus is provided with conversion means for converting the value of the data. At the time of writing, the data value is converted into the same bit length and written to the storage means, and at the time of reading from the storage means. The read converted data value is converted to the original value and output, and the data that takes a long time to write is converted to the data with a short writing time to perform the writing. The memory writing time can be shortened.

  Hereinafter, an information processing apparatus and an information processing method according to embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of an information processing apparatus 100 according to the embodiment of this invention. As shown in FIG. 1, the information processing apparatus 100 includes a CPU (Central Processing Unit) 11, a bus interface 12, a DMAC (Direct Memory Access Controller) 13, a RAM (Random Access Memory) 14, and a flash memory 15. The video interface 16, the monitor 17, the keyboard interface 18, the keyboard 19, the disk interface 20, and the HDD (Hard Disk Drive) 21.

  The CPU 11 is connected to the bus via the bus interface 12. The CPU 11 can access the RAM 14 and the flash memory 15 via the bus. The CPU 11 functions as a conversion unit that inverts and converts data values. At the time of reading or writing, the data value is inverted and converted with the same bit length.

  The CPU 11 also functions as a detection unit that detects the bit distribution of data and a determination unit that determines whether or not inversion is necessary based on the detection result of the detection unit. At the time of writing, the determination unit detects a value of 0 in the data to be written, and the determination unit determines whether or not the data value is large. If there are many 0s, it is determined that inversion is necessary, and the data value is the same. Inversion conversion is performed with the bit length and the result is written to the storage means. At the time of reading, the value of the inverted and converted data read from the storage means is converted into the original value and output.

  The DMAC 13 is a dedicated block that mediates data transfer between the peripheral device and the memory. The DMAC 13 can access the RAM 14 and the flash memory 15 via the bus. Further, the DMAC 13 controls a process of directly transferring data between the peripheral device and the memory without using the CPU 11. Note that the conversion unit, detection unit, and determination unit described above may be provided in the DMAC 13.

  The RAM 14 is connected to the bus and is used as a work area when data is processed.

  The flash memory 15 is a kind of nonvolatile semiconductor memory, and a memory cell (storage unit) is composed of one stacked gate type MOS transistor. The flash memory 15 can write and read program information by the CPU 11 or the DMAC.

  The monitor 17 is connected to the bus via the video interface 16 and displays input data and the like. The keyboard 19 is connected to the bus via the keyboard interface 18 and is a means for inputting data. The HDD 21 is connected to the bus via the disk interface 20. The HDD 21 stores various data.

  FIG. 2 shows the appearance rate of bits of programs and data written to the flash memory 15. As shown in FIG. 2, the appearance rates of bit 0 of program 1, program 2, and data file are 64.3%, 59.5%, and 85.1%, respectively. As a result, the appearance rate of bit 0 of many programs or data files is higher than that of bit 1.

  In the flash memory 15, writing bit 0 takes longer than writing bit 1. Then, the write time can be shortened by performing bit conversion of the program and data at the time of writing.

  Subsequently, an operation example of the information processing apparatus 100 according to the present invention will be described with respect to the information processing method with reference to the drawings.

  FIG. 3 is a flowchart showing an operation example at the time of writing. As shown in FIG. 3, in the information processing apparatus 100, when writing data, first, write data is created in step S11. For example, a predetermined program is created. Next, in step S12, the data distribution is detected. Here, the CPU 11 (detection means) checks the appearance rate of 0 in the write data created in step S11.

  Next, in step S13, it is determined whether a reversal process is necessary. In this case, based on the detection result in step S12 described above, if the appearance rate of 0 is large, it is determined that inversion processing is necessary. The determination is made by the CPU 11 (determination means).

  If it is determined in step S13 that inversion processing is necessary, inversion setting is written in the register in step S14. If it is determined in step S13 that the inversion process is unnecessary, the process proceeds to step S15.

  Next, in step S15, an inversion identification flag is set. Here, data whose position and bit value are known in advance may be used. For example, 1 is set in the inversion identification flag. In step S16, the write data is read out to the RAM 14. For example, the read data is “0x00A4”. In this data, there are 3 bits 1 and 13 bits 0.

  Next, in step S17, it is determined whether or not the register is set to be inverted. If it is determined that the register is set to invert, the data is inverted in step S18. Here, for example, the data “0x00A4” is inverted to the data “0xFF5B”. This data has 13 bits 1 and 3 bits 0.

  Next, in step S19, the data obtained by the inversion process is written into the flash memory 15. Then, the write operation is terminated.

  In this manner, writing speed can be improved by converting data with many bits 0 into data with little bits 0 and writing.

  FIG. 4 is a flowchart showing an operation example at the time of reading. As shown in FIG. 4, in the information processing apparatus 100, when data is read, first, in step S21, a reverse identification flag is read from the flash memory 15 in a non-inverted manner. Here, it can be seen whether the data with the position and bit known in advance is inverted or not.

  In step S22, inversion / non-inversion information is set in the register. In step S23, data is read from the flash memory 15. For example, data “0xFF5B” is read. This data has 13 bits 1 and 3 bits 0.

  Next, in step S24, it is determined whether or not the register is set to be inverted. Here, if it is determined that the register is in the inversion setting, the read data is subjected to bit inversion processing in step S25. For example, the data “0xFF5B” is inverted to the data “0x00A4”. This data has 3 bits 1 and 13 bits 0, and is the same as the data before writing. The obtained data is output and the read operation is terminated.

  FIG. 5 is a diagram illustrating states of write data and read data. FIG. 5A shows a data state in the case of inversion writing and inversion reading. FIG. 5B shows a data state in the case of non-inversion writing and non-inversion reading.

  As shown in FIG. 5A, the first 1 bit of the write data is an inversion identification flag. For example, when the inversion identification flag is “0”, inversion writing is performed. The inverted data is written into the flash memory. At the time of reading, the reverse identification data shown in the figure is obtained by recognizing the reverse identification flag and performing reverse read.

  As shown in FIG. 5B, the first 1 bit of the write data is an inversion identification flag. For example, when the inversion identification flag is “1”, non-inversion writing is performed. Write data to flash memory as it is. At the time of reading, the non-inverted identification flag is recognized and non-inverted reading is performed to obtain read data shown in the figure.

  As described above, in the present embodiment, the information processing apparatus 100 detects a data bit distribution, a determination unit that determines whether inversion is necessary based on a detection result by the detection unit, Conversion means for inverting the value is provided, and at the time of writing, the value of 0 is detected in the data to be written by the determination means, and the determination means determines whether or not the data value is large. The data value is inverted and converted with the same bit length and written to the storage means. At the time of reading, the inverted and converted data value read from the storage means is converted to the original value. It is made to output.

  Thereby, it is possible to shorten the writing time of a memory such as a flash ROM. High-speed writing improves the productivity of the data writing process. In addition, it is possible to automatically detect the bit distribution of the data and determine whether the inversion process is necessary, thereby facilitating the data rewriting work.

  In the above embodiment, as shown in FIG. 6A, the inversion conversion of data is performed in units of 1 bit. For example, “0” in the data of B′00011011 is changed to “1”. The conversion is performed to convert “1” to “0”, but the present invention is not limited to this. In the case of one cell multiple bits, for example, as shown in FIG. In this case, “00” in the data of B′00011011 is converted to “11”, “01” is converted to “01”, “10” is converted to “10”, and “11” is converted to “00”. To be made.

  In this manner, writing speed can be improved by converting data with many bits 0 into data with little bits 0 and writing.

  In the above-described embodiment, the information processing apparatus 100 is provided with detection means for detecting the bit distribution of data and determination means for determining whether inversion is necessary based on the detection result by the detection means. However, the present invention is not limited to this. For example, the bit distribution of data may be examined in advance to determine whether inversion is necessary, and the inversion identification flag may be set in the data.

  In the above embodiment, the storage means is a flash memory, but the present invention is not limited to this. A memory having different read / write processing times depending on other data values may be used as the storage means.

  As described above, in the information processing apparatus using the information processing method according to the present invention, the writing time is shortened and the data writing process is produced by high-speed writing with respect to the flash memory whose reading / writing processing time varies depending on the data value. It can be used for the purpose of improving the performance.

It is a figure which shows the structural example of the information processing apparatus of embodiment. It is a figure which shows the bit distribution example of a program and a data file. It is a flowchart which shows the operation example of the information processing apparatus 100 at the time of writing. 6 is a flowchart illustrating an operation example of the information processing apparatus 100 at the time of reading. It is a figure which shows the example of a data state. It is a figure which shows the bit conversion example.

Explanation of symbols

11 ... CPU, 12 ... bus interface, 13 ... DMAC, 14 ... RAM, 15 ... flash memory, 16 ... video interface, 17 ... monitor, 18 ... keyboard Interface, 19 ... Keyboard, 20 ... Disk interface, 21 ... HDD, 100 ... Information processing device,

Claims (12)

In at least one of data reading or writing, in an information processing apparatus having a storage unit that has different read / write processing times depending on the value of the data,
Conversion means for converting the value of the data,
The conversion means is
At the time of writing, the value of the data is converted with the same bit length and written to the storage means,
An information processing apparatus, wherein at the time of reading, the converted data value read from the storage means is converted into an original value and output. Detection means for detecting the bit distribution of the data;
Determination means for determining whether conversion processing is necessary based on a detection result by the detection means;
When the determination unit determines that the conversion process is necessary, a setting unit that sets control information indicating the conversion process in the data;
Further comprising control information detecting means for detecting control information indicating conversion processing from the data,
The information processing apparatus according to claim 1, wherein the determination unit determines that processing is necessary when the appearance frequency of data that takes time to write is high. The information processing apparatus according to claim 1, wherein the storage unit is a flash memory. The information processing apparatus according to claim 1, wherein the conversion unit converts a plurality of storage cell units at the same time in the data read / write unit. The information processing apparatus according to claim 1, wherein the conversion unit converts data that takes a long time during writing into data having a short writing time. The information processing apparatus according to claim 1, wherein when there are a plurality of storage units, the conversion unit performs conversion only when reading from and writing to a predetermined storage unit. In an information processing method in an information processing apparatus having a storage unit in which read / write processing time differs depending on a value of the data, at least one of reading and writing data,
When writing, converting the value of the data with the same bit length and writing to the storage means;
An information processing method comprising: a step of converting the value of the converted data read from the storage means into an original value and outputting the original value at the time of reading. Detecting a bit distribution of the data;
A determination step of determining whether conversion processing of the value of the data is necessary based on the detection result;
If it is determined that the conversion process is necessary, a setting step for setting control information indicating the conversion process;
A detection step of detecting the control information from the data at the time of writing;
8. The information processing method according to claim 7, wherein when the control information is detected in the detection step, the value of the data is converted with the same bit length and written to the storage means. The information processing method according to claim 7, wherein the conversion processing performs conversion in units of a plurality of storage cells at the same time in the data read / write unit. The information processing method according to claim 7, wherein the conversion process converts data that takes a long time during writing into data having a short writing time. 8. The information processing method according to claim 7, wherein when there are a plurality of storage means, the conversion means performs conversion only when reading from and writing to the predetermined storage means. The information processing method according to claim 7, wherein the conversion is performed only when the write data is biased.

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