JP2005159211A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the concentration of an impurity which is injected into a channel area, from being reduced while suppressing occurrence of an interface state in a gate-insulated semiconductor device including a trench element separation. <P>SOLUTION: In the manufacturing method of the semiconductor device relating to the present invention, a part of a semiconductor layer 101 is removed to form a trench 104, and a surface of the trench 104 is oxidized to form a silicon oxide film 105. At least a surface portion of the silicon oxide film 105 is then nitrided by nitriding radicals in plasma. At such a time, it is preferable that the concentration of nitrogen in the surface portion of the silicon nitride film 105 is higher than the concentration of nitrogen in the interface of the silicon nitride film 105 and a silicon substrate 101. A filling insulating film 107 is then formed for filling the trench 104. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a gate insulating semiconductor device having trench element isolation and a manufacturing method thereof.

  In recent years, there has been a strong demand for higher density SRAM circuits in order to reduce the cost of semiconductor devices. In order to increase the density, miniaturization in the gate length direction of the transistor is important, but reduction in the isolation direction of each element cannot be avoided. Therefore, in order to reduce the isolation width, it is essential to reduce the gate width of the transistor.

  However, as the gate width of the transistor is reduced, the inverse narrow effect that the threshold voltage decreases becomes more prominent. This reverse narrow effect occurs because in the step of oxidizing the gate oxide film, the channel impurity existing at the channel end diffuses into the trench element isolation, and the impurity concentration at the channel end decreases.

  When the inverse narrow effect occurs, the threshold voltage differs between transistors having different gate widths, and variations in leakage current and saturation current occur, and circuit performance deteriorates. As means for suppressing the reverse narrow effect, for example, there is a means disclosed in Patent Document 1. The method will be described below with reference to FIGS. 8 (a) to (f). 8 (a) to 8 (f) are cross-sectional views showing a manufacturing process of a conventional semiconductor device.

  First, in order to obtain the structure shown in FIG. First, an underlying oxide film 602 and a silicon nitride film 603 are formed on a P-type silicon substrate 601. Next, a photoresist (not shown) is formed on the silicon nitride film 603 by photolithography to open a region where trench element isolation is to be formed. Next, reactive ion etching is performed using a photoresist as a mask, thereby forming a trench 604 formed by removing the silicon nitride film 603, the underlying oxide film 602, and the upper portion of the silicon substrate 601. Thereafter, nitrogen 605 is doped on the side and bottom surfaces of the trench by performing rotational oblique ion implantation using the silicon nitride film 603 as a mask.

  Next, in the step shown in FIG. 8B, a buried oxide film 606 filling the trench is deposited on the substrate by thermal CVD or bias CVD.

  Next, in the step shown in FIG. 8C, the buried oxide film 606 is planarized using CMP technology. This planarization is performed until the silicon nitride film 603 is exposed.

  Next, in the step shown in FIG. 8D, the silicon nitride film 603 and the underlying oxide film 602 are removed.

  Next, in the step shown in FIG. 8E, the channel region in the silicon substrate 601 is doped with channel boron 607 for controlling the threshold voltage.

  Next, in the step shown in FIG. 8F, a gate insulating film 608 and a gate polysilicon film 609 are formed on the silicon substrate 601. Thereafter, a trench element isolation type MISFET is formed through a step of forming a wiring.

In the semiconductor device formed by the above manufacturing method, boron 607 implanted into the channel region can be prevented from diffusing into the buried oxide film 606 because nitrogen 605 is implanted.
Japanese Patent Laid-Open No. 11-45996

  However, in the semiconductor device formed by the above-described method, an interface state is generated at the interface between the gate insulating film 608 and the silicon substrate 601 due to the influence of nitrogen 605 doped into the silicon substrate 601, and NBTI (Negative bias Temperature Instability). ) This causes a problem that the characteristics deteriorate.

  An object of the present invention is to provide a semiconductor device that can prevent the concentration of impurities implanted in a channel region from decreasing and can suppress the generation of interface states, and a method for manufacturing the same. is there.

  The semiconductor device of the present invention includes a semiconductor layer having an element region, an impurity layer provided in the element region of the semiconductor layer, and a first insulating layer located on a side of the impurity layer of the semiconductor layer. A semiconductor device comprising: a film; and an element isolation having a second insulating film formed between the semiconductor layer and the first insulating film so as to cover a side surface and a lower surface of the first insulating film In the second insulating film, nitrogen is contained in at least the surface portion on the side in contact with the first insulating film.

  As described above, when the second insulating film contains nitrogen, it is possible to suppress diffusion of impurities contained in the impurity layer into the first insulating film for element isolation. Thereby, since the impurity concentration of the impurity layer does not decrease, the reverse narrow channel effect can be prevented.

  When the nitrogen concentration at the surface portion is higher than the nitrogen concentration at the interface between the second insulating film and the semiconductor layer, the nitrogen concentration at the interface between the second insulating film and the semiconductor layer is low. Therefore, generation of interface states in the semiconductor layer can be suppressed. Thereby, deterioration of the NBTI characteristic is suppressed.

  In the portion of the second insulating film located on the side surface and the lower surface of the element isolation, at least the surface portion may contain the nitrogen.

  Alternatively, in only the portion of the second insulating film located on the side surface of the element isolation, at least the surface portion may contain the nitrogen. In this case, since the portion of the second insulating film located on the lower surface of the element isolation does not contain nitrogen, stress due to nitrogen is less likely to occur.

  When the peak concentration of nitrogen in the second insulating film is 6 atomic% or more, the migration of impurities can be effectively prevented.

  When the nitrogen concentration at the interface between the second insulating film and the semiconductor layer is 2 atomic% or less, the amount of nitrogen contained in the semiconductor layer is sufficiently small, so that an interface level is further generated. It becomes difficult to do.

  In the case where boron is contained in the impurity layer, the movement of boron is effectively prevented by the above-described method of including nitrogen in the second insulating film.

  The method of manufacturing a semiconductor device of the present invention includes a step (a) of forming a protective film on a semiconductor layer, and removing a part of the semiconductor layer using the protective film as a mask, thereby forming a trench in the semiconductor layer. A step (b) of forming, a step (c) of forming a first insulating film on a side surface and a bottom surface of the trench by oxidizing a portion of the semiconductor layer exposed on the surface of the trench, A step (d) of nitriding at least a surface portion of the first insulating film; a step (e) of forming a second insulating film filling the trench after the step (d); and the step (e). And (f) forming an impurity layer by implanting impurities into the semiconductor layer.

  Thereby, even when a high-temperature heat treatment or the like is performed later, since at least the surface portion of the first insulating film is nitrided, it is difficult for impurities to diffuse into the second insulating film in element isolation. Therefore, the reverse narrow channel effect can be made difficult to occur.

  In the step (d), when the nitrogen concentration at the surface portion is formed higher than the nitrogen concentration at the interface between the first insulating film and the semiconductor layer, Since the nitrogen concentration at the interface between the semiconductor layer and the semiconductor layer is low, interface states are not easily generated by heat treatment or the like. From the above, in the semiconductor device manufactured by this method, the deterioration of the NBTI characteristic is suppressed.

  In the step (d), the transfer of impurities can be effectively prevented by setting the peak concentration of nitrogen in the first insulating film to 6 atomic% or more.

  In the step (d), since the nitrogen concentration at the interface between the first insulating film and the semiconductor layer is 2 atomic% or less, the amount of nitrogen contained in the semiconductor layer is sufficiently small. Interface levels are less likely to occur.

  In the step (e), when boron is implanted as the impurity, the movement of boron is effectively prevented by using nitrogen.

  In the step (d), radical nitriding treatment may be performed on the first insulating film.

  In the step (d), nitrogen may be ion-implanted into the first insulating film.

  After the step (b) and before the step (c), a portion of the semiconductor layer exposed to the surface of the trench is oxidized to form a third insulating film. A step (g) of rounding a portion exposed at an edge of the trench, and a step (h) of removing the third insulating film after the step (g) and before the step (c). It may be. In this case, after forming and removing the third insulating film having a thickness that can sufficiently round the portion of the semiconductor layer exposed at the edge of the trench, the third insulating film is formed more than the third insulating film. A thin first insulating film can be formed. By nitriding the first insulating film having a small thickness, a steeper nitrogen profile can be formed. Thereby, since the area | region with low nitrogen concentration becomes narrow among 1st insulating films, an impurity can be made hard to diffuse more.

  After step (c), before step (d), step (i) of filling the trench to a depth in the middle of the trench, and after step (d), removing the photoresist (J) can be further provided, so that only a shallow region of the semiconductor layer exposed on the surface of the trench can be selectively nitrided, so that generation of stress due to nitrogen can be suppressed.

  In the semiconductor device of the present invention, by nitriding the silicon oxide film on the side and bottom surfaces of the trench element isolation to form the nitride film, it is possible to suppress diffusion of impurities in the channel region toward the trench element isolation. . Thereby, since the channel region impurity concentration does not decrease, the reverse narrow channel effect can be prevented. Here, since the concentration of nitrogen at the interface between the semiconductor layer and the silicon oxide film is low, even when heat treatment or the like for forming the gate insulating film is performed, interface states are hardly generated, and deterioration of NBTI characteristics is suppressed. Can do.

(First embodiment)
Below, the 1st Embodiment of this invention is described, referring FIG. 1 (a)-(f). 1A to 1F are cross-sectional views showing a process flow of a semiconductor device in the first embodiment.

  First, in order to obtain the configuration shown in FIG. First, an underlying oxide film 102 having a thickness of 5 to 100 nm and a silicon nitride film 103 having a thickness of 50 to 1000 nm are formed on a P-type silicon substrate 101. Next, a photoresist (not shown) having an opening in a region where trench element isolation is to be formed is formed on the silicon nitride film 103 by photolithography. Thereafter, reactive ion etching is performed using a photoresist as a mask to form a trench 104 having a depth of 100 to 1000 nm that penetrates the silicon nitride film 103 and the underlying oxide film 102 and removes the upper portion of the silicon substrate 101. To do.

  Next, in the step shown in FIG. 1B, a portion of the silicon substrate 101 exposed at the surface of the trench 104 is thermally oxidized to form a silicon oxide film 105 having a thickness of 10 to 50 nm.

Next, in the step shown in FIG. 1C, at least the surface portion of the silicon oxide film 105 is nitrided by nitrogen radicals in plasma to form a surface nitrided layer 106 having a nitrogen peak concentration of 6 atomic% or more. Nitriding may occur up to the interface between the silicon oxide film 105 and the silicon substrate 101. In that case, the concentration of nitrogen at the interface is preferably 2 atomic% or less. Here, a gas such as N ₂ / O ₂ , NO, N ₂ O, or NH ₃ may be used as a nitriding gas for generating plasma.

  Here, the concentration distribution of nitrogen will be described. FIG. 7 is a graph showing the concentration distribution of nitrogen when the silicon oxide film is nitrided by nitrogen radicals in the plasma. As shown in FIG. 7, the concentration of nitrogen is maximized near the surface of the silicon oxide film, and decreases as the depth from the surface increases. Nitrogen is contained only at a very low concentration at the interface between the silicon oxide film and the silicon substrate.

  Next, in the step shown in FIG. 1D, a buried oxide film 107 having a thickness of 1 to 3 times the depth of the trench 104 is deposited by a thermal CVD method or a bias CVD method. Subsequently, the buried oxide film 107 is planarized using CMP technology. This planarization is performed until the silicon nitride film 103 is exposed.

  Next, in the step shown in FIG. 1E, the silicon nitride film 103 and the underlying oxide film 102 are removed. At this time, the buried oxide film 107 (shown in FIG. 1D) becomes the trench element isolation 107a.

  Next, in the step shown in FIG. 1F, the region for forming the P-type MISFET is covered with a photoresist 108 by photolithography, and the region for forming the N-type MISFET is exposed. Thereafter, boron 109 is ion-implanted using the photoresist 108 as a mask, thereby forming a channel impurity region 110 in a region where an N-type MISFET is to be formed. This channel impurity region 110 is formed to control the threshold voltage.

  Thereafter, although not shown, a gate insulating film and a gate electrode are formed on the channel impurity region 110 in the silicon substrate 101. Thereafter, ion implantation or the like for forming source / drain regions is performed to form the semiconductor device of this embodiment.

  In the semiconductor device of this embodiment, the surface nitride layer 106 is formed on the surface of the trench 104 in the silicon substrate 101, so that boron implanted into the channel impurity region 110 diffuses into the buried oxide film 107. Can be suppressed. As a result, the boron concentration in the channel impurity region 110 does not decrease, so that the reverse narrow channel effect can be prevented. On the other hand, the concentration of nitrogen at the interface between the silicon substrate 101 and the silicon oxide film 105 is low. Therefore, even when heat treatment or the like for forming the gate insulating film is performed, interface states are hardly generated, and deterioration of NBTI characteristics can be suppressed.

(Second Embodiment)
Below, the 2nd Embodiment of this invention is described, referring Fig.2 (a)-(f). 2A to 2F are cross-sectional views showing a process flow of the semiconductor device in the second embodiment.

  First, in order to obtain the configuration shown in FIG. First, an underlying oxide film 202 having a thickness of 5 to 100 nm and a silicon nitride film 203 having a thickness of 50 to 1000 nm are formed on a P-type silicon substrate 201. Next, a photoresist (not shown) having an opening in a region for forming trench element isolation is formed on the silicon nitride film 203 by photolithography. Thereafter, reactive ion etching is performed using a photoresist as a mask to form a trench 204 having a depth of 100 to 1000 nm that penetrates the silicon nitride film 203 and the underlying oxide film 202 and removes the upper portion of the silicon substrate 201. To do.

  Next, in the step shown in FIG. 2B, a portion of the silicon substrate 201 exposed at the surface of the trench 204 is thermally oxidized to form a silicon oxide film 205 having a thickness of 10 to 50 nm.

Next, in the step shown in FIG. 2C, nitrogen is injected with low energy from at least two directions with respect to the P-type silicon substrate 201 at a large inclination angle (for example, the inclination from the normal direction is 15 to 45 degrees). To do. For example, nitrogen is ion-implanted under an implantation condition of an implantation energy of 5 keV, an implantation dose of 1 × 10 ¹⁶ ions / cm ² , and an implantation angle of 15 degrees. Thus, at least the surface portion of the silicon oxide film 205 is nitrided to form a surface nitride layer 206 having a nitrogen peak concentration of 6 atomic% or more. Here, nitridation may occur up to the interface between the silicon oxide film 105 and the silicon substrate 101. In that case, the concentration of nitrogen at the interface is 2 atomic% or less.

  Next, in the step shown in FIG. 2D, a buried oxide film 207 having a thickness of 1 to 3 times the depth of the trench 204 is deposited by thermal CVD or bias CVD. Subsequently, the buried oxide film 207 is planarized using CMP technology. This planarization is performed until the silicon nitride film 203 is exposed.

  Next, in the step shown in FIG. 2E, the silicon nitride film 203 and the underlying oxide film 202 are removed. Thereby, the buried oxide film 207 (shown in FIG. 2D) becomes the trench element isolation 207a.

  Next, in the step shown in FIG. 2F, the region for forming the P-type MISFET is covered with a photoresist 208 by photolithography, and the region for forming the N-type MISFET is exposed. Thereafter, ion implantation of boron 209 is performed using the photoresist 208 as a mask, thereby forming a channel impurity region 210 in a region where an N-type MISFET is to be formed. This channel impurity region 210 is formed to control the threshold voltage.

  Thereafter, although not shown, a gate insulating film and a gate electrode are formed on the channel impurity region 210 in the silicon substrate 201. Thereafter, ion implantation or the like for forming source / drain regions is performed to form the semiconductor device of this embodiment.

  In the semiconductor device of this embodiment, the surface nitride layer 206 is formed on the surface of the trench 204 in the silicon substrate 201, so that boron implanted into the channel impurity region 210 diffuses into the buried oxide film 207. Can be suppressed. Thereby, since the boron concentration of the channel impurity region 210 is not lowered, the reverse narrow channel effect can be prevented. On the other hand, the concentration of nitrogen at the interface between the silicon substrate 201 and the silicon oxide film 205 is low. Therefore, even when heat treatment or the like for forming the gate insulating film is performed, interface states are hardly generated, and deterioration of NBTI characteristics can be suppressed.

  Furthermore, in the present embodiment, since ion implantation is performed at a large tilt angle in the step shown in FIG. 2C, a deep region in the surface of the trench 204 is difficult to be doped with nitrogen. That is, since only the shallow region of the surface of the trench 204 can be selectively nitrided, it is possible to prevent the generation of stress due to nitrogen while suppressing the diffusion of the impurity implanted into the channel region. Can do.

(Third embodiment)
Below, the 3rd Embodiment of this invention is described, referring FIG. 3 (a)-(d) and FIG. 4 (a)-(d). FIGS. 3A to 3D and FIGS. 4A to 4D are cross-sectional views showing the process flow of the semiconductor device in the third embodiment.

  First, in order to obtain the configuration shown in FIG. First, an underlying oxide film 302 having a thickness of 5 to 100 nm and a silicon nitride film 303 having a thickness of 50 to 1000 nm are formed on a P-type silicon substrate 301. Next, a photoresist (not shown) having an opening in a region for forming trench element isolation is formed on the silicon nitride film 303 by photolithography. Thereafter, reactive ion etching is performed using a photoresist as a mask to form a trench 304 having a depth of 100 to 1000 nm that penetrates the silicon nitride film 303 and the underlying oxide film 302 and removes the upper portion of the silicon substrate 301. To do.

  Next, in a step shown in FIG. 3B, a silicon oxide film 305 having a thickness of 10 to 50 nm is formed by thermally oxidizing a portion of the silicon substrate 301 exposed on the surface of the trench 304.

  Next, in the step shown in FIG. 3C, wet etching is performed to remove the silicon oxide film 305 formed on the side surface and the bottom surface of the trench 304.

  Next, in the step shown in FIG. 3D, the surface portion of the silicon substrate 301 exposed on the surface of the trench 304 is thermally oxidized to form a silicon oxide film 311 having a thickness of 10 nm or less.

Next, in the step shown in FIG. 4A, the nitride layer 311 ′ is formed by nitriding the silicon oxide film 311 with nitrogen radicals in the plasma. At this time, the peak concentration of nitrogen is 6 atomic% or more. Nitridation may occur up to the interface between the silicon oxide film 311 and the silicon substrate 301. In this case, the concentration of nitrogen at the interface is 2 atomic% or less. Here, a gas such as N ₂ / O ₂ , NO, N ₂ O, or NH ₃ may be used as a nitriding gas for generating plasma.

  Next, in the step shown in FIG. 4B, a buried oxide film 307 having a thickness of 1 to 3 times the depth of the trench 304 is deposited by a thermal CVD method or a bias CVD method. Thereafter, the buried oxide film 307 is planarized using CMP technology. This planarization is performed until the silicon nitride film 303 is exposed.

Next, in the step shown in FIG. 4C, the silicon nitride film 303 and the underlying oxide film 302 are removed. At this time, the buried oxide film 307 (shown in FIG. 4B) becomes the trench element isolation 307a.
Next, in the step shown in FIG. 4D, the region for forming the P-type MISFET is covered with a photoresist 308 by photolithography, and the region for forming the N-type MISFET is exposed. Thereafter, ion implantation of boron 309 is performed using the photoresist 308 as a mask, thereby forming a channel impurity region 310 in a region where an N-type MISFET is to be formed. This channel impurity region 310 is formed in order to control the threshold voltage.

  Thereafter, although not shown, a gate insulating film, a gate electrode, and the like are formed on the silicon substrate 301. Thereafter, by performing ion implantation or the like, the semiconductor device of this embodiment is formed.

  In the semiconductor device of this embodiment, the nitride layer 311 ′ is formed on the surface of the trench 304 in the silicon substrate 301, so that boron in the channel impurity region 310 implanted later diffuses into the buried oxide film 307. This can be suppressed. Thereby, since the boron concentration in the channel does not decrease, the reverse narrow channel effect can be prevented. On the other hand, the nitrogen concentration in the nitride layer 311 ′ decreases as the silicon substrate 301 is approached. Therefore, even when heat treatment or the like for forming the gate insulating film is performed, interface states are hardly generated, and deterioration of NBTI characteristics can be suppressed.

  Further, by removing the silicon oxide film 305 formed in the step shown in FIG. 3B and forming a new silicon oxide film 311 in the step shown in FIG. 3D, the following effects can be obtained. Can do.

  In the step shown in FIG. 3B, by forming the silicon oxide film 305, the portion of the silicon substrate 301 exposed at the upper edge of the trench 304 (the upper end portion of the silicon substrate 301) is rounded. This step is performed to alleviate electric field concentration on the upper end portion of the silicon substrate 301. Here, in order to obtain a sufficient electric field concentration effect, the thickness of the silicon oxide film 305 is preferably 10 nm or more. In contrast, the thickness of the silicon oxide film 311 newly formed in the step shown in FIG. 3D is set to 10 nm or less. Then, in the step shown in FIG. 4A, a steeper nitrogen profile can be formed by nitriding the thin silicon oxide film 311. As a result, the region having a low nitrogen concentration in the nitride layer 311 ′ is narrow, so that impurities such as boron contained in the silicon substrate 301 are less likely to diffuse.

(Fourth embodiment)
Below, the 4th Embodiment of this invention is described, referring FIG. 5 (a)-(d) and FIG. 6 (a)-(d). FIGS. 5A to 5D and FIGS. 6A to 6D are cross-sectional views showing the process flow of the semiconductor device in the fourth embodiment.

  First, in order to obtain the configuration shown in FIG. First, an underlying oxide film 402 having a thickness of 5 to 100 nm and a silicon nitride film 403 having a thickness of 50 to 1000 nm are formed on a P-type silicon substrate 401. Next, a photoresist (not shown) having an opening in a region where trench element isolation is to be formed is formed on the silicon nitride film 403 by photolithography. Thereafter, reactive ion etching is performed using a photoresist as a mask to form a trench 404 having a depth of 100 to 1000 nm that penetrates the silicon nitride film 403 and the underlying oxide film 402 and removes the upper portion of the silicon substrate 401. To do.

  Next, in a step shown in FIG. 5B, a portion of the silicon substrate 401 exposed at the surface of the trench 404 is thermally oxidized to form a silicon oxide film 405 having a thickness of 10 to 50 nm.

  Next, in the step shown in FIG. 5C, a photoresist 412 is deposited with a thickness of 1 to 3 times the depth of the trench 404.

  Next, in the step shown in FIG. 5D, ashing is performed to remove the photoresist 412 to a depth in the middle of the trench 404. As a result, the upper part of the side wall of the trench 404 in the silicon oxide film 405 is exposed.

Next, in the step shown in FIG. 6A, the surface nitride layer 413 is formed by nitriding at least the surface portion of the silicon oxide film 405 exposed on the upper portion of the sidewall of the trench with nitrogen radicals in the plasma. To do. At this time, the peak concentration of nitrogen is 6 atomic% or more. Nitridation may occur up to the interface between the silicon oxide film 405 and the silicon substrate 401, but in this case, the concentration of nitrogen at the interface is 2 atomic% or less. Here, a gas such as N ₂ / O ₂ , NO, N ₂ O, or NH ₃ may be used as a nitriding gas for generating plasma.

  Next, after removing the photoresist 412 in the step shown in FIG. 6B, a buried oxide film 407 having a thickness of 1 to 3 times the depth of the trench 404 is formed by thermal CVD or bias CVD. accumulate. Thereafter, the buried oxide film 407 is planarized using CMP technology. This planarization is performed until the silicon nitride film 403 is exposed.

  Next, in the step shown in FIG. 6C, the silicon nitride film 403 and the underlying oxide film 402 are removed. At this time, the buried oxide film 407 (shown in FIG. 6B) becomes the trench element isolation 407a.

  Next, in the step shown in FIG. 6D, the region for forming the P-type MISFET is covered with a photoresist 408 by photolithography, and the region for forming the N-type MISFET is exposed. Thereafter, ion implantation of boron 409 is performed using the photoresist 408 as a mask, thereby forming a channel impurity region 410 in a region where an N-type MISFET is to be formed. This channel impurity region 410 is formed to control the threshold voltage.

  Thereafter, although not shown, a gate insulating film, a gate electrode, and the like are formed on the silicon substrate 401. Thereafter, ion implantation or the like for forming source / drain regions is performed to form the semiconductor device of this embodiment.

  In the semiconductor device of the present embodiment, since the silicon oxide film 405 formed on the surface of the trench 404 contains nitrogen in the region located above the trench, boron in the channel impurity region 410 implanted later is buried and oxidized. Diffusion into the film 407 can be suppressed. Thereby, since the boron concentration in the channel does not decrease, the reverse narrow channel effect can be prevented. On the other hand, the concentration of nitrogen at the interface between the silicon substrate 401 and the silicon oxide film 405 is low. Therefore, even when heat treatment or the like for forming the gate insulating film is performed, interface states are hardly generated, and deterioration of NBTI characteristics can be suppressed.

  Further, in the step shown in FIG. 6A, only the portion exposed at the upper part of the side wall of the trench 404 is selectively nitrided, so that it is caused by nitrogen while suppressing the diffusion of the impurity implanted into the channel region. It is possible to prevent the generation of stress.

  As described above, the present invention has high industrial applicability in that the impurity concentration of the channel region can be maintained without deteriorating the NBTI characteristics.

(A)-(f) is sectional drawing which shows the process flow of a semiconductor device in 1st Embodiment. (A)-(f) is sectional drawing which shows the process flow of a semiconductor device in 2nd Embodiment. (A)-(d) is sectional drawing which shows the process flow of a semiconductor device in 3rd Embodiment. (A)-(d) is sectional drawing which shows the process flow of a semiconductor device in 3rd Embodiment. (A)-(d) is sectional drawing which shows the process flow of a semiconductor device in 4th Embodiment. (A)-(d) is sectional drawing which shows the process flow of a semiconductor device in 4th Embodiment. FIG. 6 is a graph showing a nitrogen concentration distribution when a silicon oxide film is nitrided by nitrogen radicals in plasma. (A)-(f) is sectional drawing which shows the manufacturing process of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Silicon substrate 102 Underlay oxide film 103 Silicon nitride film 104 Trench 105 Silicon oxide film 106 Surface nitride layer 107 Embedded oxide film 107a Trench element isolation 108 Photoresist 109 Boron 110 Channel impurity region 201 Silicon substrate 202 Underlay oxide film 203 Silicon nitride film 204 Trench 205 Silicon oxide film 206 Surface nitride layer 207 Embedded oxide film 207a Trench element isolation 208 Photoresist 209 Boron 210 Channel impurity region 301 Silicon substrate 302 Underlay oxide film 303 Silicon nitride film 304 Trench 305 Silicon oxide film 307 Embedded oxide film 307a Trench element Isolation 308 Photoresist 309 Boron 310 Channel impurity region 311 Silicon oxide film 11 'nitride layer 401 silicon substrate 402 underlying oxide film 403 a silicon nitride film 404 trench 405 silicon oxide film 407 buried oxide film 407a trench isolation 408 photoresist 409 boronic 410 channel impurity regions 412 photoresist 413 surface nitriding layer

Claims (16)

A semiconductor layer having an element region;
An impurity layer provided in the element region of the semiconductor layer;
Of the semiconductor layer, located on the side of the impurity layer, between the semiconductor layer and the first insulating film so as to cover the first insulating film and the side and bottom surfaces of the first insulating film A semiconductor device including an element isolation having a formed second insulating film,
A semiconductor device in which nitrogen is contained in at least a surface portion of the second insulating film on a side in contact with the first insulating film. The semiconductor device according to claim 1,
The semiconductor device, wherein a nitrogen concentration in the surface portion is higher than a nitrogen concentration at an interface between the second insulating film and the semiconductor layer. The semiconductor device according to claim 1, wherein
The semiconductor device, wherein at least the surface portion contains the nitrogen in portions of the second insulating film located on the side surface and the lower surface of the element isolation. The semiconductor device according to claim 1, wherein
A semiconductor device, wherein only the portion of the second insulating film located on the side surface for element isolation contains at least the surface portion of the nitrogen. The semiconductor device according to any one of claims 1 to 4,
A semiconductor device in which the peak concentration of nitrogen in the second insulating film is 6 atomic% or more. A semiconductor device according to any one of claims 1 to 5,
The semiconductor device, wherein the nitrogen concentration at the interface between the second insulating film and the semiconductor layer is 2 atomic% or less. It is a semiconductor device given in any 1 paragraph among Claims 1-6,
A semiconductor device in which the impurity layer contains boron. Forming a protective film on the semiconductor layer (a);
(B) forming a trench in the semiconductor layer by removing a part of the semiconductor layer using the protective film as a mask;
(C) forming a first insulating film on the side and bottom surfaces of the trench by oxidizing a portion of the semiconductor layer exposed on the surface of the trench;
A step (d) of nitriding at least a surface portion of the first insulating film;
A step (e) of forming a second insulating film filling the trench after the step (d);
A method of manufacturing a semiconductor device, comprising the step (f) of injecting impurities into the semiconductor layer to form an impurity layer after the step (e). A method for manufacturing a semiconductor device according to claim 8, comprising:
In the step (d), a method for manufacturing a semiconductor device, wherein the nitrogen concentration at the surface portion is formed higher than the nitrogen concentration at the interface between the first insulating film and the semiconductor layer. A manufacturing method of a semiconductor device according to claim 8 or 9,
In the step (d), a method for manufacturing a semiconductor device, wherein the peak concentration of nitrogen in the first insulating film is 6 atomic% or more. It is a manufacturing method of the semiconductor device given in any 1 paragraph among Claims 8-10,
In the step (d), the method for manufacturing a semiconductor device, wherein the nitrogen concentration at the interface between the first insulating film and the semiconductor layer is 2 atomic% or less. It is a manufacturing method of a semiconductor device given in any 1 paragraph among Claims 8-11,
In the step (e), a method for manufacturing a semiconductor device, wherein boron is implanted as the impurity. It is a manufacturing method of the semiconductor device according to any one of claims 8 to 12,
In the step (d), a radical nitriding process is performed on the first insulating film. It is a manufacturing method of the semiconductor device according to any one of claims 8 to 12,
In the step (d), a method for manufacturing a semiconductor device, wherein nitrogen is ion-implanted into the first insulating film. It is a manufacturing method of the semiconductor device according to any one of claims 8 to 14,
After the step (b) and before the step (c), a portion of the semiconductor layer exposed to the surface of the trench is oxidized to form a third insulating film. Rounding the portion exposed at the upper edge of the trench (g);
A method of manufacturing a semiconductor device, further comprising a step (h) of removing the third insulating film after the step (g) and before the step (c). It is a manufacturing method of the semiconductor device according to any one of claims 8 to 15,
After the step (c) and before the step (d), a step (i) of filling up to a depth in the middle of the trench with a photoresist;
A method of manufacturing a semiconductor device, further comprising a step (j) of removing the photoresist after the step (d).

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