JP2005175668A - Power amplifier circuit, transmitter , receiver and transceiver employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power amplifier circuit technology suitable for circuit integration with ease of use. <P>SOLUTION: The power amplifier circuit includes: a bias application means for applying a bias voltage generated in a current mirror circuit of a bias circuit to an amplifier transistor; and a ground means for grounding a connecting point between the bias application means and the bias circuit to a ground point. The bias application means is configured to include a bias resistor and the ground means is configured to include a capacitor. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a power amplifier circuit technology including a current mirror circuit.

  As a prior art example, FIG. 10 shows a configuration example of a power amplifier circuit. This power amplifier circuit is used in the final stage of a transmitter for transmitting a modulated radio frequency signal (RF signal) to an access point or another personal computer equipped with the wireless LAN system in a wireless LAN system. An example of a power amplifier circuit is shown. An input signal is an RF signal having a frequency of 5 GHz, and a power supply voltage is 3.3V.

  10 includes an RF signal input terminal 1, an RF signal output terminal 2, a power supply terminal 3, a reference voltage terminal 4, an amplifying transistor 5, a grounding capacitor 6, an input matching circuit 20, and the like. The output matching circuit 30, the bias circuit 40 and the bias resistor 7, the emitter of the amplifying transistor 5 is grounded, the base is connected to the RF signal input terminal 1 through the input matching circuit 20, and the bias circuit The collector is connected to the RF signal output terminal 2 and the power supply terminal 3 through the output matching circuit 30. Further, the bias circuit 40 includes bias transistors 43, 44, 45 and current adjustment resistors 41, 42. The base of the bias transistor 43 whose emitter is grounded is connected to the emitter of the bias transistor 44, The collector is connected to the base of the bias transistor 44, connected to the reference voltage terminal 4 via the current adjustment resistors 42 and 41, and the base of the bias transistor 45 is connected to the connection point of the current adjustment resistors 41 and 42. . The power supply voltage terminal 3 is connected to the collector of the bias transistor 44 and the collector of the bias transistor 45, and the bias voltage is applied to the base of the amplifying transistor 5 via the bias resistor 7 at the emitter of the bias transistor 45. To do. Further, the input matching circuit 20 includes capacitors 21 and 22 and an inductor 23, and performs impedance matching between the base of the amplifying transistor 5 and the RF signal source impedance. The output matching circuit 30 includes inductors 31 and 33, The capacitor 32 has a function of matching the impedance between the collector of the amplifying transistor 5 and the load impedance, and also serves to supply the voltage of the power supply terminal 3 to the collector of the amplifying transistor 5.

The high-frequency amplifier circuit amplifies the 5 GHz band RF signal input to the RF signal input terminal 1 by the amplifying transistor 5 and outputs the amplified signal to the RF signal output terminal 2. At this time, the bias circuit 40 that supplies a bias voltage to the amplifying transistor 5 detects a change in bias current caused by a change in the base-collector voltage V _BE of the amplifying transistor 5 due to a temperature change. 44, the temperature dependence of the collector current of the amplifying transistor 5 is suppressed (for example, by canceling out the fluctuation due to the temperature change of the voltage between the base and the collector of the emitter follower circuit of the bias transistor 45 and the current mirror circuit). Non-Patent Document 1). Further, the current mirror circuit and the amplifying transistor are connected via a buffer by an emitter follower circuit, so that the drive capability at the time of high output in the power amplifying circuit is not short.

  The collector current flowing through the amplifying transistor 5 is adjusted by the values of the current adjusting resistors 41 and 42, and the connection between the base of the amplifying transistor 5 and the bias circuit 40 is biased via the bias resistor 7. The distortion in the biasing transistor 45 caused by the RF signal input to the base of the amplifying transistor 5 leaking into the biasing circuit 40 through the biasing resistor 7 is suppressed while suppressing a decrease in gain due to the influence of the impedance of the circuit 40. And the deterioration of distortion characteristics in the amplifying transistor 5 are suppressed.

“Efficiency Improvement Method Using Distortion Cancellation in W-CDMA Two-stage Power Amplifier HBT MMIC” The Institute of Electronics, Information and Communication Engineers IEICE Technical Report, ED2001-207, FIG.

In the above prior art, in order to reduce the deterioration of the gain due to the decrease in the gain due to the influence of the impedance of the bias circuit 40 and the occurrence of distortion in the bias transistor 45 due to the input RF signal leaking into the bias circuit 40. For this purpose, the resistance value of the bias resistor 7 may be increased. However, when a high-level RF signal is input so that the base and emitter of the amplifying transistor are turned on as a diode, the input impedance of the amplifying transistor is reduced and the voltage V _BE between the base and the emitter is reduced. Since the base value increases, the voltage drop due to the bias resistor 7 increases, and the supply of the bias current to the amplifying transistor becomes insufficient. For this reason, input / output characteristics are deteriorated, and sufficient output power cannot be obtained.

For example, when the power amplifier circuit of FIG. 10 is used in the first stage low noise amplifier circuit of the receiver, the output waveform is distorted at the time of strong input, and a sufficient dynamic range cannot be obtained. In addition, sufficient transmission power cannot be obtained when used in the power amplification circuit at the final stage of the transmitter. However, if an inductor having a large impedance with respect to the RF signal is used instead of the bias resistor 7, the voltage drop due to the inductor is eliminated, so that the input / output characteristics are improved. However, since the semiconductor chip area of the inductor becomes very large, integration is impossible and there is a limit to the bias current supply capability of the bias circuit.
The problem of the present invention is that, in view of the above-described state of the prior art, in the power amplifier circuit, it is possible to improve the input / output characteristics, and to make an integrated circuit with little deterioration of the input / output characteristics and distortion characteristics. Is to make it possible.
An object of the present invention is to solve the above-mentioned problems and provide a power amplifying circuit technology that is easy to use and is suitable for integration.

  In order to solve the above problems, in the present invention, as a power amplifier circuit, a bias applying means for applying a bias voltage generated in a current mirror circuit of a bias circuit to an amplifying transistor, the bias applying means, and the bias A grounding means for grounding a connection point with the circuit is provided. The bias applying unit includes a bias resistor, and the ground unit includes a capacitor.

  According to the present invention, it is possible to improve input / output characteristics in a power amplifier circuit. Also, integration in a state where input / output characteristics are secured is possible.

The best mode for carrying out the present invention will be described below with reference to the drawings.
FIG. 1 is a configuration diagram of a power amplifier circuit according to a first embodiment of the present invention.
In FIG. 1, 101 is a grounding capacitor, 102 is a grounding resistor, 103 is a biasing inductor, 104 is a biasing resistor, and other parts corresponding to those in FIG. The bias transistors 43 and 44 and the current adjustment resistors 41 and 42 constitute a current mirror circuit, and the bias transistor 45 constitutes an emitter follower circuit. The connection configuration of the grounding capacitor 101 and the grounding resistor 102 constitutes a grounding means. The connection configuration of the bias inductor 103 and the bias resistor 104 constitutes a bias application unit. The bias applying means is connected to the emitter of the biasing transistor 45 constituting the emitter follower circuit, and the connection point is grounded by a series connection body (grounding means) of the grounding resistor 102 and the grounding capacitor 101.

  In the above configuration, the RF signal input to the RF signal input terminal 1 is amplified by the amplifying transistor 5 via the input matching circuit 20 and output from the RF signal output terminal 2 via the output matching circuit 30. Also, a bias voltage from the emitter of the bias transistor 45 is applied to the base of the amplifying transistor 5 via a serial connection configuration (bias applying means) of the bias inductor 103 and the bias resistor 104.

  With the above configuration, the emitter of the emitter follower circuit is grounded by the series connection body (grounding means) of the grounding resistor 102 and the grounding capacitor 101, so that the bias signal 40 of the RF signal input to the base of the amplifying transistor 5 can be obtained. Leakage is suppressed. For this reason, even if the values of the bias resistor 104 and the bias inductor 103 are reduced, deterioration of distortion characteristics and input / output characteristics can be suppressed. As a result, a power amplifier circuit configuration suitable for integration can be obtained. it can.

FIG. 2 is a configuration example diagram of a power amplifier circuit according to a second embodiment of the present invention.
In FIG. 2, reference numeral 200 denotes a bias circuit, which includes a current adjustment resistor 201 and bias transistors 202 and 203, and other parts corresponding to those in FIG.

  In the bias circuit 200, the bias transistors 202 and 203 form a current mirror circuit. The base of the bias transistor 202 whose emitter is grounded is connected to the emitter of the bias transistor 203, and the collector of the bias transistor 202 is connected to the base of the bias transistor 203 and via the current adjustment resistor 201. The reference voltage terminal 4 is connected. The collector of the bias transistor 203 is connected to the power supply terminal 3. Further, the connection point between the base of the biasing transistor 202 and the emitter of the biasing transistor 203 is connected to the base of the amplifying transistor 5 via the biasing inductor 103 and the biasing resistor 104 as bias applying means, and for grounding. The resistor 102 and the grounding capacitor 101 are grounded by a series connection body (grounding means).

  The configuration of the second embodiment is a configuration in which a bias voltage is directly applied to the amplifying transistor 5 without using an emitter follower circuit, compared to the configuration of the first embodiment of FIG. Other configurations are the same as those of the first embodiment. Since the emitter follower circuit is not used, the circuit can be simplified.

FIG. 3 is a configuration example diagram of a power amplifier circuit as a third embodiment of the present invention. In the third embodiment, there are two current mirror circuits in the bias circuit.
In FIG. 3, 300 is a bias circuit, 301 and 302 are PNP-type bias transistors, 303 and 304 are current adjustment resistors, and 305 is a current adjustment for adjusting the current flowing through the amplification transistor 5. Resistance. In addition, parts corresponding to those in FIG. In the bias circuit 300, the NPN type bias transistors 43 and 44 constitute a first current mirror circuit, and the PNP type bias transistors 301 and 302 constitute a second current mirror circuit. The biasing transistor 45 constitutes an emitter follower circuit. The connection configuration of the grounding capacitor 101 and the grounding resistor 102 constitutes a grounding means. The connection configuration of the bias inductor 103 and the bias resistor 104 constitutes a bias application unit. The bias applying means is connected to the emitter of the biasing transistor 45 constituting the emitter follower circuit, and the connection point is grounded by a series connection body of the grounding resistor 102 and the grounding capacitor 101 as the grounding means.

  In the above configuration, in the bias circuit 300, the current adjusting resistor 303 and the current adjusting resistor are respectively connected to the emitter of the PNP bias transistor 301 and the emitter of the PNP bias transistor 302 that constitute the second current mirror circuit. A reference voltage is applied through the resistor 304 for use. The bases of the bias transistors 301 and 302 are connected in common. The common connection point is connected to the collector of the PNP bias transistor 302. The collector of the PNP bias transistor 302 is connected to the collector of the bias transistor 45 and grounded by the current adjustment resistor 305, and the collector of the PNP bias transistor 301 is connected to the current adjustment resistor 41. Connected to.

By adopting the above configuration, the same effects as those of the first embodiment can be obtained, and the resistance ratio between the current adjustment resistor 303 and the current adjustment resistor 304 can be selected to an appropriate value so that at a strong input level, If the current flowing through the bias transistor 43 of the first current mirror circuit is increased, supply of bias current due to a decrease in the base-emitter voltage V _BE of the amplifying transistor 5 at a high input level can be suppressed. . For this reason, deterioration of input / output characteristics can be further suppressed.

With the above configuration, the current flowing through the collector of the bias transistor 45 through the PNP bias transistor 302 is Ib1, the current flowing through the bias transistor 43 through the PNP bias transistor 301 is Ib2, Assuming that the resistance value of the current adjustment resistor 303 is Rb2 and the resistance value of the current adjustment resistor 304 is Rb1, Ib2 is obtained from the following equation 1 as an approximate value. That is,
Ib2≈ (Rb1 / Rb2) × Ib1 (Equation 1)
From the above equation (1), a strong level RF signal is inputted so that the base and emitter of the amplifying transistor 5 are turned on as a diode, the base-emitter voltage V _BE decreases, and the PNP bias transistor 302 When the bias current Ib1 flowing through the bias transistor 45 of the emitter follower circuit increases, a bias current equal to the ratio of the resistance values Rb1 and Rb2 of the current adjustment resistors 304 and 303 is biased through the PNP bias transistor 301. It flows to transistor 43. Therefore, when the base-emitter voltage V _BE at the strong input level is reduced by selecting an appropriate ratio of the resistance values Rb1 and Rb2 of the current adjustment resistors 304 and 303, the bias adjustment If the bias current flowing through the transistor 43 is increased, it is possible to suppress deterioration in input / output characteristics due to a shortage of bias current at a high input level.

  FIG. 4 is a configuration example diagram of a power amplifier circuit according to a fourth embodiment of the present invention. The fourth embodiment is a case where a current mirror circuit using a field effect transistor is included in the bias circuit.

In FIG. 4, reference numeral 400 denotes a bias circuit, and 401 and 402 denote P-channel field effect transistors. Other parts corresponding to those in FIG.
The power amplifier circuit as the fourth embodiment in FIG. 4 is different from the power amplifier circuit as the third embodiment in FIG. 3 in that the second current mirror circuit is replaced with a PNP transistor and a P-channel transistor is used. It consists of a field effect transistor (FET). With the configuration using the P-channel type field effect transistor, the chip area can be reduced when the power amplifier circuit is integrated.

FIG. 5 is a configuration example diagram of a power amplifier circuit according to a fifth embodiment of the present invention.
In FIG. 5, reference numeral 500 denotes an IC package. Other parts corresponding to those in FIG.
The power amplifier circuit shown in FIG. 5 shows a configuration when the power amplifier circuit of the first embodiment of FIG. 1 is integrated. In FIG. 5, the amplifying transistor 5, the bias circuit 40, the grounding capacitor 101, the grounding resistor 102, the biasing inductor 103, and the biasing resistor 104 are integrated on the same semiconductor substrate and enclosed in an IC package 500. Yes. The input matching circuit 20 and the output matching circuit 30 are externally provided, and the amplification transistor 5, the grounding capacitor 101, and the ground terminal of the bias circuit 40 are provided separately.

  In the case where the power amplifier circuit as the first embodiment of FIG. 1 is integrated, if the grounding of the amplifying transistor 5 and the grounding capacitor 101 is common, the isolation between the amplifying transistor 5 and the grounding capacitor 101 is isolated. Deteriorates. For this reason, the RF signal amplified by the amplifying transistor 5 leaks to the bias circuit 40 via the grounding capacitor 101 and the grounding resistor 102 via the ground common connection point of the amplifying transistor 5 and the grounding capacitor 101. Include. Due to leakage of the RF signal, distortion occurs in the bias circuit 40 and the distortion characteristics of the amplifying transistor 5 deteriorate. By separately providing the ground terminal of the amplifying transistor 5 and the ground terminal of the grounding capacitor 101, it is possible to suppress the deterioration of the distortion characteristics even when they are integrated.

6, 7 and 8 are explanatory diagrams of the effect of the present invention.
FIG. 6 shows the experimental results of the third-order distortion characteristics of the power amplifier circuit of the first embodiment shown in FIG.
In FIG. 6, the experiment is performed on the power amplification circuit at the final stage of the transmission unit of the 2.4 GHz band wireless LAN, when the RF signal input level is −15 dBm, the power supply voltage is 3.3 V, and 3 V is applied to the voltage reference terminal. The third-order distortion characteristics are measured. The horizontal axis represents the input RF signal frequency, and the vertical axis represents the third-order distortion suppression ratio. Moreover, the characteristic of FIG. 6 is a characteristic of 1st Embodiment of the power amplifier circuit of FIG. The inductance value of the bias inductor 103 is 5 nH, the bias resistor 104 is 50Ω, the grounding capacitor 101 is 2 pF, and the grounding resistor 102 is 10Ω. Integration of a power amplifier circuit including these elements is easily possible. The resonance frequency of the bias inductor 103 and the grounding capacitor 101 is about 1.6 GHz, which is lower than the frequency of the input RF signal. Thereby, degradation of the RF signal due to resonance is reduced. By adding the grounding capacitor 101, leakage of the input RF signal to the bias circuit is suppressed, so that the third order distortion characteristic is improved.

  FIG. 7 is a diagram illustrating a simulation result of input / output characteristics of the power amplifier circuit according to the third embodiment of FIG. 3. This simulation was performed for the input / output characteristics of the power amplifier circuit at the final stage of the transmission unit of the 5 GHz band wireless LAN. The RF signal frequency was 5.2 GHz, the power supply voltage was 3.3 V, and 3 V was applied to the voltage reference terminal. To do. The horizontal axis is input power, and the vertical axis is power gain. From this simulation result, by providing the second current mirror circuit composed of PNP type transistors in the bias circuit, the shortage of bias current at the time of strong input is improved, so the deterioration of power gain at the time of strong input is suppressed. It is done.

FIG. 8 is a diagram illustrating a simulation result of the third-order distortion characteristics of the power amplifier circuit (FIG. 5) according to the fifth embodiment.
From the simulation results, when the ground of the amplification transistor and the ground of the grounding capacitor are integrated separately, the isolation between the amplification transistor and the grounding capacitor is sufficiently secured, so the input RF signal is a bias circuit. Degradation of distortion characteristics due to leaking into the substrate can be suppressed.

FIG. 9 shows a configuration example of a transceiver using the power amplifier circuit of the present invention. Hereinafter, a transmitter, a receiver, and a transceiver will be described with reference to FIG.
FIG. 9 is a configuration example of a transceiver of a 5.2 GHz band wireless LAN system. In FIG. 9, 901 is a transmission / reception antenna, 902 is a switching circuit, 903 is a low noise amplification circuit, 904, 906, 914 and 916 are band pass filters, 905 and 913 are mixer circuits, 907 is an orthogonal signal demodulator, and 908 base A band signal processing unit, 909 is a control unit, 910 is a local transmission circuit, 911 is a PLL circuit, 912 is an orthogonal signal modulation unit, and 915 is a power amplification circuit. In this transceiver, data transmission / reception is performed by alternately switching between transmission and reception using the same frequency band, and the low noise amplifier circuit 903 and the power amplifier circuit 915 shown in FIG. Assume that any of the power amplifier circuits shown is used.

With respect to the transceiver in the wireless LAN system of FIG. 9, a case where a 5.2 GHz band RF signal transmitted from a wireless LAN access point or a personal computer equipped with another wireless LAN is received will be described first.
In FIG. 9, the control unit 909 of the baseband signal processing unit 908 switches the switching circuit 902 to the reception side, turns the transmission unit off, and turns the reception unit on. The RF signal transmitted from the access point or another personal computer is received from the transmission / reception antenna 901 and input to the low noise amplification circuit 903 via the switching circuit 902. The input RF signal is amplified and input to the mixer circuit 905 via the band pass filter 904. In the mixer circuit 905, the input RF signal is frequency-converted into an intermediate frequency signal of 1 GHz band by a local oscillation signal from the transmission / reception local oscillation circuit 910 whose transmission frequency is controlled by the PLL circuit 911, and a band-pass filter 906. Is input to the orthogonal signal demodulator 907. The orthogonal signal demodulation unit 907 demodulates the input intermediate frequency signal into an I / Q orthogonal signal, and then the baseband signal processing unit 908 demodulates the baseband data signal. The demodulated data signal is stored in a memory of a personal computer or the like equipped with the transceiver via an interface.

Next, a case where a data signal is transmitted from a wireless LAN transceiver to an access point or another personal computer equipped with the wireless LAN will be described.
In FIG. 9, the control unit 909 of the baseband signal processing unit 908 switches the switching circuit 902 to the transmission side, turns off the reception unit, and turns on the transmission unit.
The baseband signal processing unit 908 modulates the data signal into an I / Q quadrature signal and inputs it to the quadrature signal modulator 912. The input I / Q quadrature signal is modulated and output as an intermediate frequency signal in the 1 GHz band by the quadrature signal modulation unit 912 and input to the mixer circuit 913. The input intermediate frequency signal is frequency-converted and output to a 5.2 GHz band RF signal in the mixer circuit 913 by the local oscillation signal from the transmission / reception local oscillation circuit 910 whose transmission frequency is controlled by the PLL circuit 911. The signal is input to the power amplifier circuit 915 via the pass filter 914. The power amplifier circuit 915 amplifies the input RF signal and transmits the amplified RF signal through the band-pass filter 916 and the switching circuit 902 through the transmission / reception antenna 901.

In the transmitter / receiver in the wireless LAN system of FIG. 9 described above, any of the power amplifier circuits shown in FIGS. 1 to 5 is used for the low noise amplifier circuit 903 and the power amplifier circuit 915, so that distortion characteristics and input / output Even when these circuits are integrated, it is possible to obtain a transmitter / receiver with excellent distortion characteristics and little deterioration in distortion characteristics and input / output characteristics.
The present invention relates to a transceiver such as a wireless LAN or a cellular phone, a receiver for TV, CATV, satellite broadcast, satellite communication, and the like, and a low noise amplifier circuit and a power amplifier circuit used for them.

It is a figure which shows the 1st Embodiment of this invention. It is a figure which shows the 2nd Embodiment of this invention. It is a figure which shows the 3rd Embodiment of this invention. It is a figure which shows the 4th Embodiment of this invention. It is a figure which shows the 5th Embodiment of this invention. It is a figure which shows the experimental result of the tertiary distortion characteristic of 1st Embodiment. It is a figure which shows the simulation result of the input-output characteristic of 3rd Embodiment. It is a figure which shows the simulation result of the 3rd order distortion characteristic of 5th Embodiment. It is a figure which shows the structural example of the transmitter / receiver using the power amplifier circuit of this invention. It is a figure which shows a prior art example.

Explanation of symbols

1 ... RF signal input terminal,
2 ... RF signal output terminal,
3 ... Power terminal,
4 ... Reference voltage terminal,
5 ... Amplifying transistor,
20: Input matching circuit,
30: Output matching circuit,
40, 200, 300, 400 ... bias circuit,
43, 44, 45, 202, 203, 301, 302, 401, 402 ... Biasing transistor,
41, 42, 201, 303, 304, 305 ... current adjusting resistors,
7, 104: Bias resistor,
101: Grounding capacity,
102: resistance for grounding,
103. Inductor for bias,
23, 31, 33 ... inductor,
21, 22, 31 ... capacity,
500 ... IC package,
901 .. Transmitting and receiving antenna,
902 ... switching circuit,
903: Low noise amplifier circuit,
904, 706, 714, 716 ... band pass filter,
905, 906 ... mixer circuit,
907 ... orthogonal signal demodulator,
908 ... Baseband signal processing unit,
909 ... control unit,
910 ... Local transmitter circuit,
911 ... PLL circuit,
912 ... Quadrature signal modulator,
915: A power amplifier circuit.

Claims (12)

A power amplification circuit that performs power amplification by applying a bias voltage to an amplification transistor from a bias circuit including a current mirror circuit,
Bias applying means connected to the bias circuit for applying the bias voltage to the amplifying transistor;
A grounding means for grounding a connection point between the bias circuit and the bias applying means;
And a bias voltage obtained by the current mirror circuit is applied to the base of the amplifying transistor from the bias circuit via the bias applying means. A power amplification circuit that performs power amplification by applying a bias voltage to an amplification transistor from a bias circuit including a current mirror circuit and an emitter follower circuit,
Bias applying means connected to the emitter follower circuit for applying the bias voltage to the amplifying transistor;
A grounding means for grounding a connection point between the emitter follower circuit and the bias applying means;
And a bias voltage obtained by the current mirror circuit is applied to the base of the amplifying transistor via the emitter follower circuit whose connection point is grounded and the bias applying means. Amplification circuit. A power amplification circuit that performs power amplification by applying a bias voltage to an amplification transistor from a bias circuit including a current mirror circuit,
A current mirror circuit comprising a first biasing transistor and a second biasing transistor, and outputting the bias voltage from the emitter of the second biasing transistor;
Bias applying means connected to the emitter of the second biasing transistor for applying the bias voltage to the amplifying transistor;
Grounding means for grounding a connection point between the emitter of the second bias transistor and the bias applying means;
And a bias voltage obtained by the current mirror circuit is applied to the base of the amplifying transistor from the bias circuit via the bias applying means. A power amplification circuit that performs power amplification by applying a bias voltage to an amplification transistor from a bias circuit including a current mirror circuit and an emitter follower circuit,
A current mirror circuit comprising a first current mirror circuit having NPN-type first and second bias transistors and a second current mirror circuit having PNP-type first and second bias transistors. When,
An emitter follower circuit connected to the first current mirror circuit and the second current mirror circuit and outputting a bias voltage formed by both current mirror circuits;
Bias applying means connected to the emitter follower circuit for applying the bias voltage to the amplifying transistor;
A grounding means for grounding a connection point between the emitter follower circuit and the bias applying means;
And a bias voltage obtained by the bias circuit is applied to the base of the amplifying transistor via the emitter follower circuit and the bias applying means. A power amplification circuit that performs power amplification by applying a bias voltage to an amplification transistor from a bias circuit including a current mirror circuit and an emitter follower circuit,
A first current mirror circuit composed of NPN-type first and second bias transistors; and a second current mirror circuit composed of P-channel field effect type first and second bias transistors; A current mirror circuit comprising:
An emitter follower circuit connected to the first current mirror circuit and the second current mirror circuit and outputting a bias voltage formed by both current mirror circuits;
Bias applying means connected to the emitter follower circuit for applying the bias voltage to the amplifying transistor;
A grounding means for grounding a connection point between the emitter follower circuit and the bias applying means;
And a bias voltage obtained by the bias circuit is applied to the base of the amplifying transistor via the emitter follower circuit and the bias applying means.   6. The power amplifier circuit according to claim 1, wherein the bias applying unit includes a biasing resistor, and the grounding unit includes a capacitor.   The bias applying means includes a bias inductor, and the grounding means includes a capacitor. A resonance frequency due to the inductor and the capacitor is determined by a frequency of an RF frequency signal input to the amplification transistor. The power amplifier circuit according to claim 1, wherein the power amplifier circuit is also lowered.   9. The power amplifier circuit according to claim 1, wherein the bias circuit and the amplification transistor are configured on a single semiconductor substrate.   The power amplification circuit according to any one of claims 1 to 5, wherein the grounding means is configured to perform grounding by a ground terminal different from the amplification transistor. A receiver for receiving an RF signal,
A low noise amplifier circuit that amplifies the received RF signal, a mixer circuit that converts the RF signal output from the low noise amplifier circuit into an intermediate frequency signal by a local oscillation signal, and an intermediate frequency signal output from the mixer circuit And a demodulation circuit for demodulating
The low noise amplifier circuit is
A power amplifying circuit for performing power amplification by applying a bias voltage to an amplifying transistor from a bias circuit having a current mirror circuit, the bias applying being connected to the bias circuit and applying the bias voltage to the amplifying transistor And a grounding means for grounding a connection point between the bias circuit and the bias applying means, and a bias voltage obtained by the current mirror circuit is supplied from the bias circuit via the bias applying means to the amplifying transistor. A receiver comprising a power amplifier circuit configured to be applied to the base of the receiver. A transmitter for transmitting an RF signal,
A modulation circuit that outputs an intermediate frequency signal by modulation, a mixer circuit that converts the output intermediate frequency signal into an RF signal by a local oscillation signal, and a power amplification circuit that amplifies the RF signal output from the mixer circuit; Comprising
The power amplifier circuit is
A bias application unit configured to apply a bias voltage to an amplifying transistor from a bias circuit including a current mirror circuit to perform power amplification, and is connected to the bias circuit and applies the bias voltage to the amplifying transistor; Grounding means for grounding a connection point between the bias circuit and the bias applying means, and a bias voltage obtained by the current mirror circuit is transmitted from the bias circuit to the base of the amplifying transistor via the bias applying means. A transmitter characterized by being applied to the transmitter. A transceiver capable of receiving and transmitting RF signals,
A low noise amplifier circuit that amplifies the received RF signal, a mixer circuit that converts the RF signal output from the low noise amplifier circuit into an intermediate frequency signal by a local oscillation signal, and an intermediate frequency signal output from the mixer circuit A demodulation circuit that demodulates the output signal, a modulation circuit that outputs an intermediate frequency signal by modulation, a mixer circuit that converts the frequency of the output intermediate frequency signal into an RF signal using a local oscillation signal, and an RF signal output from the mixer circuit And a power amplifier circuit for amplifying
The low noise amplifier circuit and the power amplifier circuit are:
A bias application unit configured to apply a bias voltage to an amplifying transistor from a bias circuit including a current mirror circuit to perform power amplification, and is connected to the bias circuit and applies the bias voltage to the amplifying transistor; Grounding means for grounding a connection point between the bias circuit and the bias applying means, and a bias voltage obtained by the current mirror circuit is transmitted from the bias circuit to the base of the amplifying transistor via the bias applying means. A transmitter / receiver characterized in that the transmitter / receiver is configured to be applied to the transmitter.

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