JP2005190288A - Memory controller, flash memory system therewith, and method for controlling flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller, a flash memory system therewith, and a method for controlling the flash memory whereby when a block with new data (rewritten data) written therein and another block with old data (data yet to be rewritten) written therein coexist, a determination can be made as to which of the blocks has the newest data (valid data) written therein. <P>SOLUTION: The memory controller includes an access control function for controlling access to the flash memory; logic block addresses provided by a host system; an address management function for managing the correspondence between physical block addresses within the flash memory; a new/old identification information setting function for describing new/old identification information in the redundant area of the flash memory; and a new/old identification function for identifying on the basis of the new/old identification information the block in which the latest data matching the same logic block address is written. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.

  In recent years, a flash memory is often used as a semiconductor memory used in a memory system such as a memory card or a silicon disk. This flash memory is a kind of non-volatile memory, and is required to retain data regardless of whether power is turned on.

  By the way, the NAND flash memory that is often used in the above-described devices is used when a memory cell is changed from an erased state (logical value “1”) to a written state (logical value “0”). Can be performed in units of memory cells. However, when a memory cell is changed from a written state (logical value “0”) to an erased state (logical value “1”), it must be performed in memory cells. This can only be done with a predetermined erase unit (block) consisting of a plurality of memory cells. Such a batch erase operation is generally called block erase.

  Therefore, when data is rewritten in the NAND flash memory, new data (data after rewriting) is written to the erased block which has been erased, and old data (data before rewriting) is written. A process of erasing the written block is generally performed. When data is rewritten in this way, the data after rewriting is written in a different block from before rewriting, so the correspondence between the logical block address given by the host system and the physical block address in the flash memory Changes dynamically every time data is rewritten. Therefore, in a flash memory system (a memory system using a flash memory), information regarding this correspondence must be held.

For the reasons described above, in a general flash memory system, the logical block address corresponding to the written data is written in the redundant area of the block in which the data is written, and the logical block address and the physical block are based on this information. It manages address correspondence. Such management is disclosed in, for example, Japanese Patent Application Laid-Open No. 10-124384. The address conversion table (table showing the correspondence between logical block addresses and physical block addresses) used when accessing the flash memory is created with reference to the logical block addresses written in the redundant area. The
Japanese Patent Laid-Open No. 10-124384

As described above, in the data rewriting process, new data (data after rewriting) is written to the erased block that has been erased, and then old data (data before rewriting) is written. The block is being erased. Therefore, if erasure of a block in which old data (data before rewriting) has been normally performed, a state in which the same logical block address is written in a redundant area of a different block is left unattended. There is nothing. However, if the power is turned off before block erasure of a block in which old data (data before rewriting) has been written, the same logical block address is written to the redundant area of a different block. The rare state is left unattended. If such a state is left unattended, it is difficult to determine in which processing the data written in which block is new data (data after rewriting). New data (data after rewriting) may be erased by mistake.

  In view of this, the present invention provides a block in which a block in which new data (data after rewriting) is written and a block in which old data (data before rewriting) is written coexist. To provide a memory controller, a flash memory system including the memory controller, and a flash memory control method that can determine whether the data written in the memory is the latest data (valid data) To do.

An object of the present invention is to provide an access control function for controlling access to a flash memory,
An address management function for managing the correspondence between the logical block address given from the host system side and the physical block address in the flash memory;
New and old identification information setting function for writing old and new identification information in the redundant area of flash memory,
This is achieved by a memory controller having a new / old identification function for identifying a block in which the latest data corresponding to the same logical block address is written based on the new / old identification information. The object of the present invention is also achieved by a flash memory system comprising the memory controller and a flash memory.

Further, the object according to the present invention is a write process for writing data to a user area of a flash memory,
A flash memory including a setting process for setting new and old identification information in a redundant area of the flash memory and an identification process for identifying a block in which the latest data corresponding to the same logical block address is written based on the new and old identification information. This is also achieved by the control method.

  Here, the new / old identification information is information described in a plurality of bits of the redundant area, and the new / old identification information described in the block after rewriting is changed according to the set rule during the rewriting process. The

  According to the present invention, it is preferable that the new and old identification information is numerical information that increases or decreases each time data corresponding to the same logical block address is rewritten.

  That is, the new and old identification information is numerical information that is added or subtracted according to a set rule every time data corresponding to the same logical block address is rewritten.

  According to the present invention, it is preferable that the new and old identification information is information based on a physical block address of a block in which previous data corresponding to the same logical block address is stored.

  Here, the information based on the physical block address is information that directly or indirectly indicates the physical block address, and may be information that can be converted into a physical block address according to a set rule.

According to the present invention, a block in which new data (data after rewriting) is written and old data (data before rewriting) are written due to power-off or unauthorized operation during processing. Even if there are coexisting blocks, the data written in which block is the latest data (valid data) based on the information written in the redundant area of those blocks. Therefore, it can be avoided that the latest data (valid data) is deleted by mistake.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Description of flash memory system 1]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2. The flash memory system 1 is normally used by being detachably attached to the host system 4, and is used as a kind of external storage device for the host system 4.

  Examples of the host system 4 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.

  The flash memory 2 is a device that executes reading or writing in units of pages and erasing in units of blocks. For example, one block is composed of 32 pages, and one page is a 512-byte user area and a 16-byte redundant area. It is configured.

  The controller 3 includes a host interface control block 5, a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, And a flash memory sequencer block 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. The function of each block will be described below.

  The microprocessor 6 is a functional block that controls the operation of the entire functional blocks constituting the controller 3.

  The host interface control block 5 is a functional block that controls the operation of the host interface block 7. Here, the host interface control block 5 includes an operation setting register (not shown) for setting the operation of the host interface block 7, and the host interface block 7 operates based on the operation setting register.

  The host interface block 7 is a functional block that exchanges data, address information, status information, and external command information with the host system 4. That is, when the flash memory system 1 is attached to the host system 4, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13, and in this state, the host system 4 connects to the flash memory system 1. The supplied data or the like is taken into the controller 3 using the host interface block 7 as an entrance, and the data or the like supplied from the flash memory system 1 to the host system 4 is sent to the host system 4 using the host interface block 7 as an exit. To be supplied.

  Further, the host interface block 7 includes a task file register (not shown) for temporarily storing a host address and an external command supplied from the host system 4 and an error register (not shown) set when an error occurs. ) Etc.

The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and a plurality of SRAMs (Static Random Access Memory).
ry) is a functional block composed of cells.

  The buffer 9 is a functional block that temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive data, and data to be written to the flash memory 2 is stored in the buffer 9 until the flash memory 2 becomes writable. Retained.

  The flash memory sequencer block 12 is a functional block that controls the operation of the flash memory 2 based on internal commands. The flash memory sequencer block 12 includes a plurality of registers (not shown), and information necessary for executing an internal command is set in the plurality of registers. When information necessary for executing an internal command is set in the plurality of registers, the flash memory sequencer block 12 executes processing based on the information. Here, the “internal command” is a command given from the controller 3 to the flash memory 2 and is distinguished from an “external command” which is a command given from the host system 4 to the flash memory system 1.

  The flash memory interface block 10 is a functional block that exchanges data, address information, status information, and internal command information with the flash memory 2 via the internal bus 14.

The ECC block 11 generates an error correction code to be added to data to be written to the flash memory 2, and detects and corrects errors included in the read data based on the error correction code added to the read data. Function block.
[Description of memory cell]
Next, a specific structure of the memory cell 16 constituting the flash memory 2 shown in FIG. 1 will be described with reference to FIGS.

  FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell 16 constituting the flash memory. As shown in the figure, the memory cell 16 includes an N-type source diffusion region 18 and a drain diffusion region 19 formed in the P-type semiconductor substrate 17, and a P between the source diffusion region 18 and the drain diffusion region 19. Tunnel oxide film 20 formed to cover type semiconductor substrate 17, floating gate electrode 21 formed on tunnel oxide film 20, insulating film 22 formed on floating gate electrode 21, and insulating film 22 The control gate electrode 23 is formed on the top. A plurality of memory cells 16 having such a configuration are connected in series in the flash memory.

  The memory cell 16 has either an “erased state (a state where no electrons are accumulated)” or a “written state (a state where electrons are accumulated)” depending on whether electrons are injected into the floating gate electrode 21 or not. Is shown. Here, one memory cell 16 corresponds to 1-bit data, the “erased state” of the memory cell 16 corresponds to data of “1” of the logical value, and the “written state” of the memory cell 16 corresponds to the logical value. Corresponds to “0” data.

In the “erased state”, since electrons are not accumulated in the floating gate electrode 21, when the read voltage (high level voltage) is not applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 In the meantime, no channel is formed on the surface of the P-type semiconductor substrate 17, and the source diffusion region 18 and the drain diffusion region 19 are electrically insulated. On the other hand, when a read voltage (high level voltage) is applied to the control gate electrode 23, a channel (not shown) is formed on the surface of the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19. The source diffusion region 18 and the drain diffusion region 19 are electrically connected by this channel.

  That is, in the “erased state”, when the read voltage (high level voltage) is not applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 are electrically insulated, and the control gate electrode 23 In the state where the read voltage (high level voltage) is applied, the source diffusion region 18 and the drain diffusion region 19 are electrically connected.

  FIG. 3 is a cross-sectional view schematically showing the memory cell 16 in the “written state”. As shown in the figure, the “written state” refers to a state in which electrons are accumulated in the floating gate electrode 21. Since the floating gate electrode 21 is sandwiched between the tunnel oxide film 20 and the insulating film 22, the electrons once injected into the floating gate electrode 21 stay in the floating gate electrode 21 for a very long time. In this “write state”, since electrons are accumulated in the floating gate electrode 21, regardless of whether or not a read voltage (high level voltage) is applied to the control gate electrode 23, A channel 24 is formed on the surface of the P-type semiconductor substrate 17 between the drain diffusion region 19. Therefore, in the “written state”, the source diffusion region 18 and the drain diffusion region 19 are always electrically connected by the channel 24 regardless of whether or not a read voltage (high level voltage) is applied to the control gate electrode 23. Connection state.

  Whether the memory cell 16 is in an erased state or a written state can be read as follows. A plurality of memory cells 16 are connected in series in the flash memory. A low level voltage is applied to the memory cell 16 selected in the series body, and a high level voltage is applied to the control gate electrode 23 of the other memory cells 16. In this state, it is detected whether or not the serial body of the memory cells 16 is in a conductive state. As a result, if the serial body is in a conductive state, it is determined that the selected memory cell 16 is in a written state, and if it is in an isolated state, it is determined that the selected flash memory cell 16 is in an erased state. The In this way, it is possible to read out whether the data held in any memory cell 16 included in the serial body is “0” or “1”.

When the memory cell 16 in the erased state is changed to the written state, a high voltage is applied so that the control gate electrode 23 is on the high potential side, and electrons are injected into the floating gate electrode 21 through the tunnel oxide film 20. To do. At this time, an FN (Fowler-Nordheim) tunnel current flows and electrons are injected into the floating gate electrode 21. On the other hand, when changing the flash memory cell 16 in the written state to the erased state, a high voltage is applied to the control gate electrode 23 on the low potential side, and the voltage is stored in the floating gate electrode 21 via the tunnel oxide film 20. Discharge electrons.
[Description of flash memory structure]
Next, the memory structure of the flash memory will be described. FIG. 4 schematically shows a memory structure of the flash memory. As shown in FIG. 4, the flash memory is composed of pages, which are processing units for reading and writing data, and blocks, which are data erasing units.

  The page is composed of, for example, a user area 25 of 512 bytes and a redundant area 26 of 16 bytes. The user area 25 is an area mainly storing data supplied from the host system 4, and the redundant area 26 stores additional information such as an error collection code, a corresponding logical block address and a block status. It is an area.

The error collection code is additional information for correcting an error included in the data stored in the user area 25, and is generated by an ECC block. Based on the error collection code, if the number of errors included in the data stored in the user area 25 is equal to or less than a predetermined number, the error is corrected.

  The corresponding logical block address indicates to which logical block address the block corresponds when data is stored in the block. If no data is stored in the block, the corresponding logical block address is not stored. Therefore, whether or not the block is an erased block depends on whether or not the corresponding logical block address is stored. Judgment can be made. That is, if the corresponding logical block address is not stored, it is determined that the block is an erased block.

The block status is a flag indicating whether or not the block is a bad block (a block in which data cannot be normally written). If it is determined that the block is a bad block, the block status is bad. A flag indicating a block is set. [Description of logical block address and physical block address]
Since data cannot be overwritten in the flash memory, when rewriting data, new data (data after rewriting) is written to the erased block that has been erased, and old data (data before rewriting). The process of erasing the block in which "." Has been written must be performed. At this time, since erasure is processed in units of blocks, data of all pages of a block including a page in which old data (data before rewriting) is written is erased. Therefore, when data is rewritten, it is necessary to perform processing for moving the data of other pages of the block including the page to be rewritten to the erased block.

When rewriting data as described above, since the data after rewriting is written in a different block from before rewriting, the logical block address given from the host system side and the physical block which is the block address in the flash memory The correspondence with the address changes dynamically every time data is rewritten. For this reason, an address conversion table showing the correspondence between logical block addresses and physical block addresses is required. This address conversion table is created based on the corresponding logical block address written in the redundant area of the flash memory, and each time the data is rewritten, the correspondence relationship of the part involved in the rewriting is updated.
[Description of zone configuration]
The flash memory system according to the present invention employs a method of dividing an area in the flash memory into a plurality of zones, and each zone is composed of a plurality of blocks in the flash memory. FIG. 5 shows an example in which a zone is composed of 1024 blocks. In this example, the zone is composed of 1024 blocks B0000 to B1023, and each block is composed of 32 pages P00 to P31. Here, the block is a unit of erasing processing, and the page is a unit of reading and writing processing. Note that the storage capacity of each block and the number of pages of each block differ depending on the specifications of the flash memory.

  This zone is assigned to a certain range of logical block address space. For example, in the example shown in FIG. 6, a zone composed of 1024 blocks is allocated to a space of 1000 blocks of logical block addresses. Here, the reason why the blocks constituting the zone are allocated to the extra 24 blocks is because of the occurrence of defective blocks. However, when data is rewritten and new data is once written to another block, and then the block where the old data has been written is erased, a spare block for writing the new data is necessary. In effect, an extra 23 blocks are allocated. The number of blocks constituting the zone is appropriately set according to the use of the flash memory system and the specification of the flash memory.

Also, when writing the corresponding logical block address to the redundant area of each block, the logical block address given from the host system side is written as it is, or the serial number in each logical block address space assigned to each zone (each If a zone is assigned to a logical block address space for 1000 blocks, a serial number from 0 to 999 may be written (hereinafter, a serial number in the logical block address space assigned to each zone is called a logical serial number. .) Here, the logical sequence number can be converted into an actual logical block address by adding an offset corresponding to each zone. For example, when the top address of the logical block address space assigned to zone 0 in FIG. 6 is ADD0, the following offset is assigned to each zone.
Zone 0: ADD0
Zone 1: ADD0 + 1000x1
Zone 2: ADD0 + 1000x2
・
・
・
Zone N: ADD0 + 1000 × N
[Description of data rewrite processing]
In the data rewriting process in the flash memory system according to the present invention, new data (data after rewriting) is written to the erased block that has been erased, and then old data (data before rewriting) is written. The block that was included is erased. In such a rewriting process, new data (after rewriting) is generated when the power is turned off before executing block erasure of the block in which old data (data before rewriting) has been written. Data) and a block in which old data (data before rewriting) is written coexist. In such a case, the new data (data after rewriting) is valid data, so the old data (data before rewriting) remains with the block where the new data (data after rewriting) is written. ) Needs to be erased.

  In the flash memory system according to the present invention, a new and old block for identifying a block in which new data (data after rewriting) is written and a block in which old data (data before rewriting) is written Identification information is written in the redundant area of each block, and a block in which old data (data before rewriting) is written is identified based on the new and old identification information. Hereinafter, the new and old identification information and the identification process based on the new and old identification information will be described with reference to the drawings.

  FIG. 7 shows new and old identification information and corresponding logical block address (corresponding logical block address described by logical serial number) written in the redundant area of each block of one zone (zone composed of 1023 blocks). It is a figure which shows an example. In this example, 4 bits are assigned to the old and new identification information, and 11 bits are assigned to the corresponding logical block address. Here, the corresponding logical block address is set to 11 bits because no data is written in 10 bits for indicating the logical sequence numbers (0 to 999) for 1000 blocks allocated to one zone. This is because 1 bit (first bit) indicating this is added. Therefore, an actual logical block address can be obtained by adding an offset assigned to this zone to 10 bits excluding the first bit. Note that the logical sequence number 1023 (11 1111 1111b (binary number)) may be assigned to information indicating that data is not written without providing one bit indicating that data is not written.

  In the example shown in FIG. 7, the new / old identification information of a block in which no data is written is set to 15 (1111b (binary number)), and the corresponding logical block address of the block in which no data is written is 111. 1111 1111b (binary number) is set. In an ordinary flash memory, the “erased state” corresponds to the logical value “1”. Therefore, if the erasing process is performed, the old and new identification information is set to 15 (1111b (binary number)), and the corresponding logical block address is 111 1111 1111b (binary number) is set.

The numbers 0 to 1023 given to the left side of the new and old identification information in FIG. 7 are serial numbers assigned in the order of physical block addresses in each zone. Hereinafter, a serial number assigned in the order of physical block addresses in each zone is referred to as a physical serial number. This physical serial number (0 to 1023) can be converted into an actual address in the flash memory by adding an offset corresponding to each zone. For example, when blocks in the flash memory are assigned to zones 0 to N in the order of addresses, the following offsets are assigned to each zone.
Zone 0: 0
Zone 1: 1024x1
Zone 2: 1024x2
・
・
・
Zone N: 1024 x N
Next, the update processing of the new and old identification information shown in FIG. 7 will be described with reference to FIG. FIG. 8 is a diagram showing changes in the old and new identification information when data rewrite processing corresponding to the logical sequence number 0 (00 0000 0000b (binary number)) is performed. First, in step 0 (# 0), data corresponding to the logical sequence number 0 is written in the physical sequence number 0. Thereafter, each time data corresponding to the logical sequence number 0 is rewritten, the old and new identification information is also updated as follows. In this example, each time data is rewritten, the new / old identification information is incremented by 1 and when the old / new identification information becomes 15 (1111b (binary number)), 0 (0000b (binary number)). ).
Step 1 (# 1):
New data (data after rewriting) is written in the block corresponding to the physical serial number 6, and 1 (0001b (binary number)) is described as the old and new identification information in the redundant area of the block.
Step 2 (# 2):
New data (data after rewriting) is written in the block corresponding to the physical serial number 17, and 2 (0010b (binary number)) is described as the old and new identification information in the redundant area of the block.
Step 3 (# 3):
New data (data after rewriting) is written in the block corresponding to the physical serial number 175, and 3 (0011b (binary number)) is described as the old and new identification information in the redundant area of the block.
Step 4 (# 4):
New data (data after rewriting) is written in the block corresponding to the physical serial number 503, and 4 (0100b (binary number)) is described as new / old identification information in the redundant area of the block.
Step 5 (# 5):
New data (data after rewriting) is written in the block corresponding to the physical serial number 875, and 5 (0101b (binary number)) is described as new / old identification information in the redundant area of the block.
Thereafter, the new and old identification information is updated in the same manner. In step 15 (# 15), the new and old identification information becomes 15 (1111b (binary number)), and in step 16 (# 16), the old and new identification information becomes 0 ( 0000b (binary number)).
Step 15 (# 15):
New data (data after rewriting) is written in the block corresponding to the physical serial number 1017, and 15 (1111b (binary number)) is described as new / old identification information in the redundant area of the block.
Step 16 (# 16):
New data (data after rewriting) is written in the block corresponding to the physical serial number 26, and 0 (0000b (binary number)) is described as new / old identification information in the redundant area of the block.

Next, when a block in which new data (data after rewriting) is written and a block in which old data (data before rewriting) are written side by side, based on the old and new identification information A method for identifying a block in which new data (data after rewriting) is written and a block in which old data (data before rewriting) is written will be described. For example, when the old and new identification information of one block in which data corresponding to the same logical serial number is written is Na and the old and new identification information of the other block is Nb (Nb> Na),
Nb-Na = 1
If so, new data (data after rewriting) is written in the block whose identification information is Nb. Nb-Na> 1
If so, new data (data after rewriting) is written in a block whose old and new identification information is Na.

In the example shown in FIG. 9 (an example in which a block in which new data (data after rewriting) is written and a block in which old data (data before rewriting) are written coexist). In both the block corresponding to the physical sequence number 0 and the block corresponding to the physical sequence number 6, data corresponding to the logical sequence number 0 (00 0000 0000b (binary number)) is written. Here, 0 (0000b (binary number)) is described in the old and new identification information of the block corresponding to the physical serial number 0, and 1 (0001b (binary number)) is included in the old and new identification information of the block corresponding to the physical serial number 6. ) Is described. When this is applied to the above Na and Nb,
Na = 0
Nb = 1
Nb-Na = 1
Therefore, new data (data after rewriting) is written in the block corresponding to the physical serial number 6. If 15 (1111b (binary number)) is described in the old and new identification information of the block corresponding to the physical serial number 6,
Na = 0
Nb = 15
Nb-Na = 15
Therefore, new data (data after rewriting) is written in the block corresponding to the physical sequence number 0.

Next, a method for identifying a block in which the latest data is written based on the new and old identification information when three blocks in which data corresponding to the same logical serial number are written side by side will be described. . For example, when the old and new identification information of three blocks in which data corresponding to the same logical serial number is written is Na, Nb, and Nc (Na <Nb <Nc), the old and new identification information is Na blocks and Nb. For block relationships,
Nb-Na = 1
If so, new data is written in the Nb block with the new and old identification information in the Na block.
Nb-Na> 1
If so, new data is written in the Na block with the new and old identification information in the Nb block.
In addition, regarding the relationship between the Nb block and the Nc block, the old and new identification information:
Nc-Nb = 1
If so, new data is written in the block of Nc than the block of Nb in the old and new identification information.
Nc-Nb> 1
If so, new data is written in the Nb block than in the Nc block.
In addition, regarding the relationship between the old and new identification information blocks of Na and Nc,
Nc-Na = 2
Then, new data is written in the block of Nc than the block of Na in the old and new identification information.
Nc-Na> 2
If so, the new data is written in the Na block with the new and old identification information in the block with Nc.

For example, the old and new identification information of three blocks in which data corresponding to the same logical serial number is written
Na = 0
Nb = 1
Nc = 2
If,
Nb-Na = 1
Nc-Nb = 1
Therefore, the new and old identification information is written in the Nb block rather than the Na block and the data is newer, and the new and old identification information is written in the Nc block than the Nb block and the data is newer. The latest data is written in the block whose old and new identification information is Nc.

Also, the old and new identification information of the three blocks in which data corresponding to the same logical serial number is written
Na = 0
Nb = 1
Nc = 15
If,
Nb-Na = 1
Nc−Nb = 14
Therefore, the new and old identification information is written in the Nb block from the Na block and the data is newer, and the new and old identification information is written in the Nb block than the Nc block and the data is newer. The latest data is written in the block whose old and new identification information is Nb.

Also, the old and new identification information of the three blocks in which data corresponding to the same logical serial number is written
Na = 0
Nb = 14
Nc = 15
If,
Nb-Na = 14
Nc-Na = 15
Therefore, since the new and old identification information is written in the Na block rather than the Nb block, the data is newer, and the old and new identification information is written in the Na block than the Nc block and the data is newer. The latest data is written in the block whose old and new identification information is Na.

  In normal rewrite processing, three or more blocks in which data corresponding to the same logical serial number is written do not coexist, but a block in which data corresponding to the same logical serial number is written. Even when there are three or more coexisting, the block in which the latest data is written can be identified as described above.

In the above example, the old and new identification information is added to the user area one by one, but when one is subtracted from 15 (1111b (binary number)) and becomes 0 (0000b (binary number)), 15 ( Even if the old and new identification information is updated back to 1111b (binary number), the block in which the latest data is written can be identified based on the new and old identification information. When the new and old identification information is subtracted by one, the block in which the latest data is written is identified as follows. For example, when the old and new identification information of one block in which data corresponding to the same logical serial number is written is Na and the old and new identification information of the other block is Nb (Nb> Na),
Nb-Na = 1
If so, new data is written in the Na block with the new and old identification information in the Nb block.
Nb-Na> 1
If so, new data is written in the Nb block with the new and old identification information in the Na block.

  Further, in the flash memory system according to the present invention, the new and old identification information is updated every time the data written in the user area is rewritten as described above. It is preferable to manage with a table. For example, in the table shown in FIG. 10, the correspondence relationship between the logical block address and the physical block address and the correspondence relationship between the logical block address and the old and new identification information are collectively managed. This table is for a logical block address space for 1000 blocks allocated to one zone (zone composed of 1023 blocks), and is in the order of logical serial numbers (in the order of logical block addresses). The old and new identification information and the physical block address (described by physical serial number) are written together. That is, for each logical serial number (0 to 999), the physical serial number of the block in which data corresponding to the logical serial number is written and the old and new identification information written in the redundant area of the block are described. . In FIG. 10, a logical serial number (0 to 999) is attached to the left side of the old and new identification information in order to illustrate that the logical serial numbers are arranged in the order (logical block address order). When data corresponding to the logical serial number is not written, 1111b (binary number) is stored in the old and new identification information, and 111 1111 1111b (binary number) is stored in the physical block address (described in physical serial number). Is described. Here, the first bit of the physical block address (described by the physical serial number) is assigned to information indicating that data corresponding to the logical serial number has not been written.

  Further, the table shown in FIG. 10 must be updated every time data rewrite processing is performed. For example, when the latest data corresponding to the logical sequence number 0 is written in an erased block different from the block in which the old data is written, 0100b (binary number) is used as new / old identification information in the redundant area of the block. The new and old identification information of the writing and table is also updated from 0011b (binary number) to 0100b (binary number). Note that the physical block address of the table (described by the physical serial number) is also rewritten to the physical serial number of the block in which the latest data corresponding to the logical serial number 0 is written.

  When the table shown in FIG. 10 is created, for example, an area where 1000 blocks of new and old identification information and a physical serial number (physical block address) can be described is secured on the SRAM, and the old and new identification information is described as an initial setting. 1111b (binary number) is set in the portion to be processed, and "111 1111 1111b (binary number)" (data indicating that no data is stored) is set in the portion describing the physical serial number (physical block address). After that, the redundant areas of the blocks assigned to the zone for creating the table are sequentially read out, and when the logical serial number indicating the logical block address is described in the part describing the corresponding logical block address of the redundant area, In the part corresponding to the logical serial number of the table (the part corresponding to the logical block address), the physical serial number of the block in which the logical serial number is described is described, and the old and new identification information described together with the logical serial number is also included. And described in the part corresponding to the logical serial number (the part corresponding to the logical block address). By sequentially performing this process for 1024 blocks constituting the zone, the table shown in FIG. 10 is created.

Next, a description will be given of a case where a physical block address (physical serial number) of a block in which old data (data before rewriting) is written is described as new and old identification information. In the example shown in FIG. 11, the physical block address (physical serial number) of the block in which old data (data before rewriting) has been written in the redundant area of each block is described by the corresponding logical block address (physical serial number). It is described with. Here, in the part describing the old and new identification information, the physical serial number (0 to 1023) of the block in which the old data (data before rewriting) is written is described in 10 bits. Further, in the portion describing the corresponding logical block address, 11 bits (10 bits for indicating the logical serial number (0 to 999) for 1000 blocks allocated to one zone) as described above, 1 bit indicating that no data is written) is allocated. Note that 11 1111 1111b (binary number) is set in the part describing the old and new identification information of the block in which no data is written, and the corresponding logical block address of the block in which no data is written is described in the part. Is set to 111 1111 1111b (binary number) indicating that data is not written.

Next, refer to FIG. 12 for the update processing (new / old identification information update processing) when the physical block address (physical serial number) of the block in which old data (data before rewriting) has been written is used as the old / new identification information. To explain. FIG. 12 is a diagram showing changes in the old and new identification information when data rewrite processing corresponding to the logical sequence number 0 (00 0000 0000b (binary number)) is performed. First, in step 0 (# 1), data corresponding to the logical sequence number 0 is written in the physical sequence number 0 (00 0000 0000b (binary number)). Thereafter, each time data corresponding to the logical sequence number 0 is rewritten, the old and new identification information is also updated as follows.
Step 1 (# 1):
New data (data after rewriting) is written in the block corresponding to physical serial number 4 (00 0000 0100b (binary number)), and old data (data before rewriting) is used as new / old identification information in the redundant area of the block. ) Is written in the physical serial number 0 (00 0000 0000b (binary number)) of the block in which it was written.
Step 2 (# 2):
New data (data after rewriting) is written in the block corresponding to the physical serial number 17 (00 0001 0001b (binary number)), and old data (data before rewriting) is used as new / old identification information in the redundant area of the block. ) Is written in the physical serial number 4 (00 0000 0100b (binary number)) of the block in which it was written.
Step 3 (# 3):
New data (data after rewriting) is written in the block corresponding to the physical serial number 175 (00 1010 1111b (binary number)), and old data (data before rewriting) is used as new / old identification information in the redundant area of the block. ) Is written in the physical serial number 17 (00 0001 0001b (binary number)) of the block in which it was written.

  Next, when the physical block address (physical serial number) of the block in which the old data (data before rewriting) has been written is described as new and old identification information, new data (data after rewriting) is written. A description will be given of a method for discriminating the block in which the old block (data before rewriting) is written based on the new and old identification information.

  In the update processing of the old and new identification information shown in FIG. 12, the old data (data before rewriting) is written in the redundant area of the block where new data (data after rewriting) is written. A physical serial number (physical block address) is described. If the new and old identification information is updated in this way, the physical serial number (physical number) of the block in which the latest data is written as the old and new identification information in the block in which the data corresponding to the same logical serial number is written. Block address) is not described. Therefore, when there are a plurality of blocks in which data corresponding to the same logical serial number is written, the physical serial number (physical block address) of those blocks and the old and new identification information described in those blocks Can be used to identify the block in which the latest data is written.

For example, in the example shown in FIG. 13, data corresponding to the logical sequence number 0 is written in the physical sequence number 0 block and the physical sequence number 4 block. In addition, the physical sequence number 102 is described as the old and new identification information in the physical sequence number 0 block, and the physical sequence number 0 (00 0000 0000b (as the old and new identification information) is written in the block of the physical sequence number 4. Binary))) is described. That is, the physical serial number of the block in which the data corresponding to the logical serial number 0 is written is
0 (00 0000 0000b (binary number))
4 (00 0000 0100b (binary number))
The physical sequence number described as the old and new identification information in the redundant area of the block in which the data corresponding to the logical sequence number 0 is written is
1023 (11 1111 1111b (binary number))
0 (00 0000 0000b (binary number))
It is. Here, the physical serial number of the block in which the data corresponding to the logical serial number 0 is written, and the physical serial number 4 is not described as the old and new identification information in the redundant area of these blocks. The latest data has been written.

In addition, data corresponding to the logical sequence number 0 is also written in the block of the physical sequence number 17, and the physical sequence number 4 (00 0000 0100b (binary number)) is described as the old and new identification information in the redundant area of the block. The physical sequence number of the block in which the data corresponding to the logical sequence number 0 is written is
0 (00 0000 0000b (binary number))
4 (00 0000 0100b (binary number))
17 (00 0001 0001b (binary number))
The physical sequence number described as the old and new identification information in the redundant area of the block in which the data corresponding to the logical sequence number 0 is written is
1023 (11 1111 1111b (binary number))
0 (00 0000 0000b (binary number))
4 (00 0000 0100b (binary number))
It is. Here, the physical sequence number of the block in which data corresponding to the logical sequence number 0 is written, and the physical sequence number 17 is not described as the old and new identification information in the redundant area of these blocks. The latest data has been written.

  Next, with reference to the drawings, a description will be given of searching for an erased block as a writing destination of new data (data after rewriting) in the above rewriting process. This search is performed using, for example, an erased block search table as shown in FIG. In this erased block search table, each block constituting the zone is associated with each bit on the SRAM, and data is written according to the logical value (“0” or “1”) of each bit. Or a state in which no data is written. Here, the bits on the erased block search table correspond to 1024 blocks (physical serial numbers 0 to 1023) constituting the zone. With respect to this correspondence, the bits on the erased block search table are associated with each other in the physical sequence number order (physical block address order) from the upper row to the lower row and from the left to the right. Therefore, the upper left bit of the erased block search table corresponds to the block having the physical sequence number 0, and the lower right bit corresponds to the block having the physical sequence number 1023.

The erased block search table shown in FIG. 14A indicates that data is written in a block corresponding to each bit on the erased block search table or that it is a defective block. When the block status is described, “0” is set to the bit, and when the data is not written (in the case of the erased block), “1” is set to the bit. The erased block search table can be created together with the address conversion table (table shown in FIG. 10). For example, “0” is set in the SRAM area for creating the erased block search table, and the corresponding logical block address is not described in the redundant area of each block and the block status indicating that it is a bad block is not described. Sometimes, if the bit corresponding to the block is set to “1”, the address conversion table can be created together. In other words, if this process is performed when the data described in the redundant area of the blocks constituting the zone is read out, only “1” is set to the bit corresponding to the erased block, and this corresponds to the block that is not the erased block. The bit to be maintained remains “0” set in advance. After creation, when data is written to an erased block, the bit corresponding to that block is changed from “1” to “0”, and the block in which data is written is erased. Therefore, it is necessary to sequentially perform update processing for changing the bit corresponding to the block from “0” to “1”.

  Next, retrieval of erased blocks using the erased block search table will be described with reference to FIG. In this erased block search, the bit corresponding to the block with the physical sequence number 1023 (from the leftmost bit in the top row) to the bit corresponding to the block with the physical sequence number 1023 (in the bottom row, (The rightmost bit) is scanned, and a bit of “1” corresponding to the erased block is searched. Here, the scanning is performed from the upper row to the lower row and from the left to the right in each row.

  In the erased block search table shown in FIG. 14B, when scanning is started from the leftmost bit in the top row, the fifth bit from the left in the fourth row from the top is Since it is “1”, the search is terminated here, and new data (data after rewriting) is written in the block of the physical serial number 28 corresponding to this bit. In the next search, scanning starts from the sixth bit from the left in the fourth row from the top. Further, such a search is continued, and when scanning proceeds to the rightmost bit in the bottom row, scanning returns to the leftmost bit in the top row and scanning is continued.

Next, a process of writing new data (data after rewriting) to the erased block searched using the erased block search table will be described. In this write process, after the write data is taken into the buffer 9 shown in FIG. 1, the following write process is set in the register of the flash memory sequencer block 12.
1) An internal write command is set in a predetermined register in the flash memory sequencer block 12 as an internal command.
2) The offset assigned to each zone is added to the physical sequence number of the erased block retrieved using the erased block search table, and the page number is added to the physical block address generated by the addition of this offset. The page address to which the corresponding 5 bits (bits for identifying 32 pages) are added is set in a predetermined register in the flash memory sequencer block 12.

  Thereafter, the flash memory sequencer block 12 executes processing based on the setting of the write processing. When this processing is executed, command information and address information for executing an internal write command are supplied from the flash memory interface block 10 to the flash memory 2 via the internal bus 14. The write data held in the buffer 9 is also supplied to the flash memory 2 via the internal bus 14, and the data is written to a page set in a predetermined register in the flash memory sequencer block 12.

After the write process is completed, new / old identification information is set in the redundant area of the block in which the data has been written, and the logical sequence number of the data written in the block is described in the portion describing the corresponding logical block address. . This write processing to the redundant area is performed by setting data such as the above-mentioned old / new identification information and logical serial number in a buffer for setting data to be written in the redundant area, and then executing a command or a command in a predetermined register in the flash memory sequencer block 12. By setting the address, it can be executed in the same manner as the above-described writing process.

FIG. 1 is a block diagram schematically showing a flash memory system according to the present invention. FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell constituting the flash memory. FIG. 3 is a cross-sectional view schematically showing a memory cell in a written state. FIG. 4 is a diagram schematically showing the structure of the address space of the flash memory. FIG. 5 is a diagram showing an example in which a zone is composed of 1024 blocks. FIG. 6 is a diagram showing the correspondence between each zone and the logical block address space. FIG. 7 is a diagram showing old and new identification information and corresponding logical block addresses written in the redundant area. FIG. 8 is a diagram for explaining the update processing of the new and old identification information. FIG. 9 is a diagram showing old and new identification information and corresponding logical block addresses written in the redundant area. FIG. 10 is a diagram showing a table describing the correspondence between logical block addresses and physical block addresses and the correspondence between logical block addresses and old and new identification information. FIG. 11 is a diagram showing old and new identification information and corresponding logical block addresses written in the redundant area. FIG. 12 is a diagram for explaining the update processing of the new and old identification information. FIG. 13 is a diagram showing old and new identification information and corresponding logical block addresses written in the redundant area. FIG. 14 is a conceptual diagram showing an example of an erased block search table.

Explanation of symbols

1 Flash memory system 2, 35, 36 Flash memory 3 Controller 4 Host computer 5 Host interface control block 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 Flash memory sequencer block 13 External bus 14 Internal bus 16 Memory cell 17 P-type semiconductor substrate 18 Source diffusion region 19 Drain diffusion region 20 Tunnel oxide film 21 Floating gate electrode 22 Insulating film 23 Control gate electrode 24 Channel 25 User region 26 Redundant region

Claims (7)

An access control function for controlling access to the flash memory;
An address management function for managing the correspondence between the logical block address given from the host system side and the physical block address in the flash memory;
New and old identification information setting function for writing old and new identification information in the redundant area of flash memory,
A memory controller comprising a new / old identification function for identifying a block in which the latest data corresponding to the same logical block address is written based on the new / old identification information. 2. The memory controller according to claim 1, wherein the old and new identification information is numerical information that increases or decreases every time data corresponding to the same logical block address is rewritten. 2. The memory controller according to claim 1, wherein the old and new identification information is information based on a physical block address of a block in which previous data corresponding to the same logical block address is stored. A flash memory system comprising the memory controller according to any one of claims 1 to 3 and a flash memory. Write processing to write data to the user area of flash memory,
A flash memory including a setting process for setting new and old identification information in a redundant area of the flash memory and an identification process for identifying a block in which the latest data corresponding to the same logical block address is written based on the new and old identification information. Control method. 6. The flash memory control method according to claim 5, wherein the old and new identification information is numerical information that increases or decreases each time data corresponding to the same logical block address is rewritten. 6. The flash memory control method according to claim 5, wherein the new and old identification information is information based on a physical block address of a block in which previous data corresponding to the same logical block address is stored.