[go: up one dir, main page]

JP2005191590A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2005191590A
JP2005191590A JP2005033801A JP2005033801A JP2005191590A JP 2005191590 A JP2005191590 A JP 2005191590A JP 2005033801 A JP2005033801 A JP 2005033801A JP 2005033801 A JP2005033801 A JP 2005033801A JP 2005191590 A JP2005191590 A JP 2005191590A
Authority
JP
Japan
Prior art keywords
circuit
semiconductor device
voltage
voltage setting
fuse element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005033801A
Other languages
Japanese (ja)
Inventor
Hiroyuki Hatano
裕之 秦野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2005033801A priority Critical patent/JP2005191590A/en
Publication of JP2005191590A publication Critical patent/JP2005191590A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of adjusting the electrical characteristics of a semiconductor chip after resin sealing without drastically increasing the number of terminals of the semiconductor device. <P>SOLUTION: The semiconductor device is formed as one chip integrated circuit, and has a plurality of status setting circuits comprising a fuse element with one end being connected to standard potential, and a voltage setting portion connected between the other end of the fuse element and a terminal for adjusting characteristics. Each voltage setting portion consists of a circuit connected with different numbers of voltage setting elements, or a circuit having only wirings without the voltage setting element, and the respective connection points of the voltage setting portion and the fuse element is connected to an internal circuit in which an adjustment of the electric characteristic value is required. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は半導体装置に関し、詳しくは半導体装置の組立後に内部回路の状態を複数設定することのできる半導体装置の回路構成に関する。   The present invention relates to a semiconductor device, and more particularly to a circuit configuration of a semiconductor device in which a plurality of internal circuit states can be set after the semiconductor device is assembled.

従来、半導体装置内に設けられたトランジスタ、ダイオード、抵抗、コンデンサ素子等からなる回路では、製造条件のばらつき等のために素子の電気的特性がばらつくことにより発振周波数、電圧値、電流値等の特性値が、所望の精度範囲以上にばらつくことが多い。   Conventionally, in a circuit made up of transistors, diodes, resistors, capacitor elements, etc. provided in a semiconductor device, the electrical characteristics of the elements vary due to variations in manufacturing conditions, etc., so that the oscillation frequency, voltage value, current value, etc. The characteristic value often varies beyond a desired accuracy range.

従って、これらの特性に製造ばらつきによる精度(以下「作り込み精度」と称す)以上の精度が要求される場合には、半導体装置に特性を調整するための外部接続用端子(特性調整用端子)を複数個予め形成しておいて、半導体装置組立後の特性測定結果に応じて必要な特性調整用端子を選択的に設定することにより要求の精度が得られるようにしていた。また別の方法として、半導体装置形成時に特性選択用の回路を予め複数形成しておいて、ウェハ状態での電気的特性測定の結果に応じて必要な回路を残し他の回路をレーザ光線等で切断することにより、要求される精度が得られる回路構成の半導体チップを得て、これを樹脂封止して半導体装置を完成するようにしていた。   Therefore, when these characteristics require accuracy higher than manufacturing accuracy (hereinafter referred to as “built-in accuracy”), external connection terminals (characteristic adjustment terminals) for adjusting the characteristics of the semiconductor device Are formed in advance, and the required accuracy can be obtained by selectively setting the necessary characteristic adjustment terminals according to the characteristic measurement results after assembling the semiconductor device. As another method, a plurality of characteristic selection circuits are formed in advance at the time of forming a semiconductor device, and necessary circuits are left in accordance with the result of electrical characteristic measurement in a wafer state, and other circuits are replaced with a laser beam or the like. By cutting, a semiconductor chip having a circuit configuration capable of obtaining the required accuracy was obtained, and this was resin-sealed to complete the semiconductor device.

しかしながら、前者の方法の場合には、最終的に不要となる特性調整用端子及びそれに接続される半導体チップ内の端子(パッド)が多数必要となるので、半導体チップのチップサイズ及び半導体装置のパッケージサイズが大きくなるとともに、半導体装置の単価が高くなるという問題がある。また、後者の場合には、ウェハ状態で一度調整された電気的特性が、調整後に行われる半導体チップの樹脂封止時の温度や応力等の影響により再び変化してしまい、所望の精度が得られないで歩留りが大幅に低下することがある。   However, the former method requires a large number of characteristic adjustment terminals that are finally unnecessary and terminals (pads) in the semiconductor chip connected thereto, so that the chip size of the semiconductor chip and the package of the semiconductor device are required. There is a problem that the unit size of the semiconductor device increases as the size increases. In the latter case, the electrical characteristics once adjusted in the wafer state are changed again due to the influence of temperature, stress, etc. during the resin sealing of the semiconductor chip performed after the adjustment, and the desired accuracy is obtained. Otherwise, the yield may be significantly reduced.

そこで本発明はこれらの問題を解決し、半導体装置の端子数を大幅に増やすことなく、半導体チップの樹脂封止後に電気的特性を調整することのできる半導体装置を提供することを目的とする。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve these problems and to provide a semiconductor device capable of adjusting electrical characteristics after resin sealing of a semiconductor chip without significantly increasing the number of terminals of the semiconductor device.

上記の問題を解決するために、請求項1の記載に係わる半導体装置は、1チップの集積回路として形成されるとともに電気的特性値の調整が必要な内部回路を有する半導体装置において、一端が基準電位に接続されたヒューズ素子と、ヒューズ素子の他端と特性調整用端子との間に接続された電圧設定部と、からなる状態設定回路を複数個有し、電圧設定部は各々異なる数の電圧設定素子が接続された回路もしくは電圧設定素子のない配線のみの回路から構成され、電圧設定部とヒューズ素子とのそれぞれの接続点を内部回路に接続することとともに、前記特性調整用端子に所定の電圧を印加することにより前記状態回路の所定のヒューズ素子を切断するようにしたことを特徴とする。   In order to solve the above problem, a semiconductor device according to claim 1 is a semiconductor device that is formed as a one-chip integrated circuit and has an internal circuit that requires adjustment of electrical characteristic values. A plurality of state setting circuits each including a fuse element connected to the potential and a voltage setting unit connected between the other end of the fuse element and the characteristic adjustment terminal. It consists of a circuit with a voltage setting element connected or a circuit only with no voltage setting element, and connects each connection point between the voltage setting unit and the fuse element to the internal circuit, and at the predetermined terminal for the characteristic adjustment A predetermined fuse element of the state circuit is cut by applying a voltage of

また、請求項2の記載に係わる半導体装置は、1チップの集積回路として形成されるとともに電気的特性値の調整が必要な内部回路を有する半導体装置において、半導体装置の基準電位と特性調整用端子との間に、ヒューズ素子としての機能を有する電圧設定素子が各々異なる数接続された状態設定回路を複数個有し、
することとともに、前記特性調整用端子に所定の電圧を印加することにより前記状態回路の所定のヒューズ素子を切断するようにしたことを特徴とする。
一端を基準電位に接続された電圧設定素子の他端側を内部回路にそれぞれ接続
According to a second aspect of the present invention, there is provided a semiconductor device that is formed as a one-chip integrated circuit and has an internal circuit that requires adjustment of electrical characteristic values. A plurality of state setting circuits each having a different number of voltage setting elements connected as fuse elements,
In addition, a predetermined fuse element of the state circuit is cut by applying a predetermined voltage to the characteristic adjustment terminal.
Connect the other end of the voltage setting element with one end connected to the reference potential to the internal circuit.

従って、本発明の半導体装置の回路構成によれば、半導体装置の端子数を大幅に増やす必要がないとともに、簡単な回路構成で半導体装置が完成した後に特性値の調整ができるようになる。   Therefore, according to the circuit configuration of the semiconductor device of the present invention, it is not necessary to greatly increase the number of terminals of the semiconductor device, and the characteristic value can be adjusted after the semiconductor device is completed with a simple circuit configuration.

以下、本発明の実施の形態を図1乃至図4を参照しながら詳細に説明する。尚、本明細書では、全図面を通して、同一または同様の部位には同一の符号を付して説明することにより重複する説明を省略している。
図1は本発明の第1の実施の形態としての半導体装置の要部を示す回路図で、半導体装置の半導体チップ10は、チップ内に設けられた状態設定回路SL1a乃至SL4aと、各状態設定回路の設定状態を検出するための定電流源回路13a乃至13dからなる電流源回路13と、製造ばらつきによる電気的特性の精度(以下「作り込み精度」と称す)以上の精度が要求される回路の定数を変更するための調整回路15と、各状態設定回路、定電流源回路13及び調整回路15との間をそれぞれ対応して接続する配線L1乃至L4と、各状態設定回路の一端を半導体装置の外部接続用端子(以下「特性調整用端子」と称す)に金属細線等で接続するための端子(パッド)T1とから構成されている。
Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. In the present specification, the same or similar parts are denoted by the same reference numerals throughout the drawings, and redundant description is omitted.
FIG. 1 is a circuit diagram showing a main part of a semiconductor device according to a first embodiment of the present invention. A semiconductor chip 10 of the semiconductor device includes state setting circuits SL1a to SL4a provided in the chip and respective state setting circuits. A current source circuit 13 composed of constant current source circuits 13a to 13d for detecting the setting state of the circuit, and a circuit that requires an accuracy higher than the accuracy of electrical characteristics due to manufacturing variations (hereinafter referred to as "built-in accuracy"). The adjustment circuit 15 for changing the constants of the circuit, wirings L1 to L4 that connect the state setting circuits, the constant current source circuit 13 and the adjustment circuit 15 in correspondence with each other, and one end of each state setting circuit as a semiconductor. It comprises a terminal (pad) T1 for connecting to an external connection terminal (hereinafter referred to as “characteristic adjustment terminal”) of the apparatus with a thin metal wire or the like.

各状態設定回路は、端子T1と基準電位(GND)との間に並列して設けられるとともに、基準電位と各配線との間に設けられて過電流が流されることにより溶断するヒューズ素子11a乃至11dと、各配線と端子T1との間に電圧設定素子としてダイオード素子12a乃至12fが各々異なる数接続された電圧設定部とから構成され、電流源回路13の各定電流源回路には、定電流源回路の動作を一括して制御するための制御線L5が接続されている。   Each state setting circuit is provided in parallel between the terminal T1 and the reference potential (GND), and is provided between the reference potential and each wiring, so that the fuse elements 11a to 11a are blown by an overcurrent. 11d and a voltage setting unit in which different numbers of diode elements 12a to 12f are connected as voltage setting elements between each wiring and the terminal T1, and each constant current source circuit of the current source circuit 13 includes a constant current source circuit. A control line L5 for collectively controlling the operation of the current source circuit is connected.

図1の各状態設定回路の設定手順及び本発明の半導体装置の使用方法について説明する。まづ、トランジスタ、ダイオード、抵抗及びコンデンサ素子等からなる回路(図示なし)を有する半導体チップを樹脂封止した後の半導体装置において、作り込み精度以上の精度または半導体装置の高歩留りを実現するために特性値の調整が必要な電気的特性、例えば、発振周波数、電圧値、電流値等を半導体テスタ等の測定装置により測定し、測定結果に応じて1つもしくは複数の状態設定回路の切断すべきヒューズ素子を決定する。   A setting procedure of each state setting circuit in FIG. 1 and a method of using the semiconductor device of the present invention will be described. First, in a semiconductor device after a semiconductor chip having a circuit (not shown) including a transistor, a diode, a resistor, a capacitor element, and the like is sealed with a resin, in order to achieve an accuracy higher than the fabrication accuracy or a high yield of the semiconductor device. Electrical characteristics that require characteristic value adjustment such as oscillation frequency, voltage value, current value, etc. are measured by a measuring device such as a semiconductor tester, and one or more state setting circuits are disconnected according to the measurement result. Determine the fuse element to be used.

次に、端子T1に図示しない外部電源から、状態設定回路の電圧設定部に応じた電圧を印加して、選択されたヒューズ素子のみに許容電流以上の電流を流して溶断させることにより、所望の電気的特性の調整情報が記録された半導体装置が得られる。
このようにして得られた半導体装置を応用基板に搭載して使用する場合には、応用基板の動作開始前に半導体装置の事前動作として、電流源回路13の各定電流源を制御線L5により動作させれば、溶断されていないヒューズ素子のみに電流が流れるので、各ヒューズ素子の接続状態(調整情報)を調整回路15で検出して結果をRAM等の記憶回路に記憶し、所望の精度が要求される回路の回路定数を記憶データに応じて設定するように動作させる。これにより、半導体装置の電気的特性のばらつきが抑えられ、作り込み精度以上に特性精度を向上することができるようになる。尚、応用基板に搭載した半導体装置の特性調整用端子は非接続にしておけば良い。
Next, a voltage according to the voltage setting unit of the state setting circuit is applied from an external power source (not shown) to the terminal T1, and a desired current is blown by flowing a current exceeding the allowable current only to the selected fuse element. A semiconductor device in which adjustment information of electrical characteristics is recorded is obtained.
When the semiconductor device obtained in this way is mounted on an application board and used, each constant current source of the current source circuit 13 is controlled by the control line L5 as a pre-operation of the semiconductor device before the operation of the application board is started. When operated, the current flows only to the fuse elements that are not blown. Therefore, the connection state (adjustment information) of each fuse element is detected by the adjustment circuit 15 and the result is stored in a storage circuit such as a RAM. Is operated so as to set the circuit constant of the circuit required for the stored data. As a result, variations in electrical characteristics of the semiconductor device can be suppressed, and the characteristic accuracy can be improved beyond the fabrication accuracy. The characteristic adjustment terminal of the semiconductor device mounted on the application board may be left unconnected.

次に、各ヒューズ素子の選択的な溶断方法について更に詳しく説明する。例えば、テスタでの特性測定の結果ヒューズ素子11a乃至11cを溶断する場合には、外部電源から端子T1にダイオード素子2個分の順方向電圧(2VF )を越え且つダイオード素子3個分の順方向電圧(3VF )未満の電圧を印加すれば、状態設定回路SL4aの設定電圧(3VF )よりは低い電圧なのでヒューズ素子11dには電流が流れないとともに、ヒューズ素子11a乃至11cにはヒューズ素子の許容電流以上の電流値、例えば、数10mAから数100mAの範囲の中の一定電流が流れることになり、ヒューズ素子11a乃至11cのみが溶断される。   Next, the method for selectively fusing each fuse element will be described in more detail. For example, when the fuse elements 11a to 11c are blown as a result of the characteristic measurement by the tester, the forward voltage (2VF) for two diode elements exceeds the forward voltage for two diode elements from the external power source to the terminal T1. If a voltage lower than the voltage (3VF) is applied, the voltage is lower than the setting voltage (3VF) of the state setting circuit SL4a, so that no current flows through the fuse element 11d, and the fuse element 11a to 11c has an allowable current of the fuse element. The above current value, for example, a constant current in the range of several tens mA to several hundred mA flows, and only the fuse elements 11a to 11c are blown.

同様に、端子T1に1VF 未満の電圧を印加すればヒューズ素子11aのみが溶断され、1VF を越え且つ2VF 未満の電圧を印加すればヒューズ素子11a及び11bが溶断され、3VF を越える電圧を印加すればヒューズ素子11a乃至11dの全てが溶断されるので、図1の回路により5つの状態設定が可能となる。   Similarly, if a voltage less than 1 VF is applied to the terminal T1, only the fuse element 11a is blown, and if a voltage exceeding 1 VF and less than 2 VF is applied, the fuse elements 11a and 11b are blown and a voltage exceeding 3 VF is applied. For example, since all of the fuse elements 11a to 11d are blown, five states can be set by the circuit of FIG.

図2は、本発明に使用するヒューズ素子の形状例を示し、半導体装置の内部に設けられたアルミニウムやポリシリコン等による配線、又は拡散層やポリシリコン等による抵抗素子等の一部を他の部分の層厚と同じ層厚のまま細くし、その部分の許容電流容量を小さくしたものをヒューズ素子として用いている。ヒューズ素子の溶断される部分の幅(W2)は、半導体素子のデザインルールの最小線幅(W1)の半分程度であれば、部分的なデザインルール違反とはなるが、製造ばらつきによりヒューズ素子が断線した状態で形成されてしまって歩留りが低下するという問題が殆どないとともに、溶断のための電流値が比較的少なくて済む。W2の具体的な幅値としては0.1μm乃至1μm程度が良い。   FIG. 2 shows an example of the shape of a fuse element used in the present invention. A part of a wiring element made of aluminum, polysilicon, or the like provided in the semiconductor device, or a resistance element made of a diffusion layer, polysilicon, etc. is replaced with another part. The fuse element is made thin with the same layer thickness as that of the portion and the allowable current capacity of the portion is reduced. If the width (W2) of the part to be fused of the fuse element is about half of the minimum line width (W1) of the design rule of the semiconductor element, it is a violation of the partial design rule. There is almost no problem that the yield is lowered due to being formed in a disconnected state, and the current value for fusing is relatively small. A specific width value of W2 is preferably about 0.1 μm to 1 μm.

図3は、第1の実施の形態の他の実施の形態の要部を示す回路図で、半導体チップ10aは、図1の各ダイオード素子の変わりに、ツェナダイオード素子14a乃至14fを電圧設定素子として使用した状態設定回路SL1b乃至SL4bが設けられた回路になっている。従って、各ヒューズ素子を溶断するときに、端子T1に印加する電圧がツェナダイオード素子のツェナ電圧(Vz)の倍数が基準になること以外は図1の回路と同様にして使用すれば良く、詳細な説明は省略する。   FIG. 3 is a circuit diagram showing a main part of another embodiment of the first embodiment. A semiconductor chip 10a is configured by replacing Zener diode elements 14a to 14f with voltage setting elements instead of the diode elements of FIG. This is a circuit provided with the state setting circuits SL1b to SL4b used. Accordingly, when each fuse element is blown, the voltage applied to the terminal T1 may be used in the same manner as the circuit of FIG. 1 except that a multiple of the Zener voltage (Vz) of the Zener diode element is used as a reference. The detailed explanation is omitted.

図4は、本発明の第2の実施の形態の要部を示す回路図で、半導体装置の半導体チップ10bは、端子T1と基準電位との間に電圧設定素子とヒューズ素子との機能を兼ねたツェナダイオード素子14a乃至14jが並列して設けられた状態設定回路SL1c乃至SL4cと、各状態設定回路の設定状態を検出するためのスイッチ回路16a乃至16dを介して電源に各々接続される抵抗17a乃至17dとからなる電圧源回路16と、作り込み精度以上の精度が要求される回路の定数を変更するための調整回路15bと、各状態設定回路、電圧源回路16及び調整回路15bとの間をそれぞれ対応して接続する配線L1′乃至L4′とから構成されている。   FIG. 4 is a circuit diagram showing the main part of the second embodiment of the present invention. The semiconductor chip 10b of the semiconductor device functions as a voltage setting element and a fuse element between the terminal T1 and the reference potential. Resistors 17a connected to the power supply via state setting circuits SL1c to SL4c provided with the Zener diode elements 14a to 14j in parallel and switch circuits 16a to 16d for detecting the setting states of the respective state setting circuits. Between the voltage source circuit 16 including 17 to 17d, the adjustment circuit 15b for changing the constants of the circuit that requires accuracy higher than the built-in accuracy, and each state setting circuit, the voltage source circuit 16 and the adjustment circuit 15b. Are respectively connected to wirings L1 ′ to L4 ′.

配線L1′乃至L4′は電圧源回路16の各抵抗の一端にそれぞれ接続されるとともに、各配線の接続状態を検出するための検出回路18と、基準電位に接続されたツェナダイオードの他端側とに接続され、電圧源回路16のスイッチ回路にはスイッチ回路の数に応じた数(n本)の制御線L6が接続されている。
この回路で各状態設定回路を設定するには、第1の実施の形態と同様に、組立後の特性測定結果に応じた一定電圧を外部電源から端子T1に印加し、状態設定回路の設定電圧が外部電源電圧未満のツェナダイオード素子のみに許容以上の電流を流すようにする。これにより、許容電流以上の電流が流れた状態設定回路のツェナダイオード素子は全て破壊され、破壊された状態設定回路に接続された各配線L1′乃至L4′が開放状態の半導体装置が得られる。
The wirings L1 'to L4' are connected to one end of each resistor of the voltage source circuit 16, respectively, and a detection circuit 18 for detecting the connection state of each wiring, and the other end side of the Zener diode connected to the reference potential The number (n) of control lines L6 corresponding to the number of switch circuits are connected to the switch circuit of the voltage source circuit 16.
In order to set each state setting circuit with this circuit, as in the first embodiment, a constant voltage corresponding to the characteristic measurement result after assembly is applied from the external power source to the terminal T1, and the setting voltage of the state setting circuit is set. However, the current exceeding the allowable value is allowed to flow only in the Zener diode element whose voltage is less than the external power supply voltage. As a result, all the Zener diode elements of the state setting circuit in which a current exceeding the allowable current flows are destroyed, and a semiconductor device in which the wirings L1 ′ to L4 ′ connected to the destroyed state setting circuit are open is obtained.

このようにして得られた半導体装置を応用基板に搭載して使用する場合には、応用基板の動作開始前に半導体装置の事前動作として、電圧源回路16の各スイッチ回路を制御線L6により各々動作させながら各配線の電圧を調整回路15aで検出することにより、各ツェナダイオード素子が接続されているか否かを検出でき、各制御線に対する各状態設定回路の設定状態の対応データを図示しないRAM等の記憶回路に記憶させ、記憶された対応データを基に所望の特性精度が要求される回路の回路定数を調整回路15aで制御するように動作させる。   When the semiconductor device obtained in this way is mounted on an application board and used, each switch circuit of the voltage source circuit 16 is controlled by the control line L6 as a pre-operation of the semiconductor device before the operation of the application board is started. By detecting the voltage of each wiring by the adjustment circuit 15a while operating, it is possible to detect whether or not each Zener diode element is connected, and the RAM corresponding to the setting state of each state setting circuit for each control line is not shown. The circuit constant of a circuit that requires a desired characteristic accuracy is controlled by the adjustment circuit 15a based on the stored correspondence data.

尚、本発明の半導体装置は上述の実施の形態のみに限定されるものではなく、例えば、状態設定回路の数は2つ以上であれば良いとともに、電圧設定素子は一定の電圧設定が可能な回路、例えば、トランジスタのベース−エミッタ間電圧やMOSトランジスタのスレッショルド電圧等の特性を使用した回路で構成しても良い。また、調整回路はヒューズ素子に流れる電流または電圧設定素子による電圧を確認できる回路、例えば、コンパレータ回路等を使用した回路で構わない。ツェナ電圧が電源電圧よりも高い場合や、消費電流を気にしない場合には電圧源回路のスイッチ回路を省略しても良い。ヒューズ素子は、配線に比べて比抵抗値が高く融点温度の低い材料を使用して、配線以上の幅または層厚にヒューズ素子を形成しても良い。   The semiconductor device of the present invention is not limited to the above embodiment. For example, the number of state setting circuits may be two or more, and the voltage setting element can set a constant voltage. A circuit, for example, a circuit using characteristics such as a base-emitter voltage of a transistor or a threshold voltage of a MOS transistor may be used. The adjustment circuit may be a circuit that can confirm the current flowing through the fuse element or the voltage by the voltage setting element, for example, a circuit using a comparator circuit or the like. When the Zener voltage is higher than the power supply voltage or when the current consumption is not a concern, the switch circuit of the voltage source circuit may be omitted. The fuse element may be formed with a width or layer thickness larger than that of the wiring by using a material having a higher specific resistance value and lower melting point temperature than the wiring.

更に、本実施の形態では、電圧設定素子として同一の電圧素子の数が異る場合についてのみ説明したが、ダイオードとツェナダイオード等を組み合わせることにより、同じ数の電圧設定素子で設定電圧を変えられるように状態設定回路を構成しても良い。また、各図の状態設定回路の電圧設定部は、電圧設定素子の数を少なくするために電圧選択回路SL1a、SL1b及びSL1cには電圧設定素子が一つもない場合を示し、他の電圧設定部は電圧設定素子を一個づつ増やす場合のみを示しているが、各状態設定回路に1つ以上の電圧設定素子を設けるようにしたり、電圧設定素子を複数個づつ増やすようにしても良い。   Furthermore, in the present embodiment, only the case where the number of the same voltage elements as the voltage setting elements is different has been described, but the set voltage can be changed with the same number of voltage setting elements by combining diodes and Zener diodes. The state setting circuit may be configured as described above. Further, the voltage setting unit of the state setting circuit in each figure shows a case where there is no voltage setting element in the voltage selection circuits SL1a, SL1b and SL1c in order to reduce the number of voltage setting elements, and other voltage setting units Shows only the case where the voltage setting elements are increased one by one, but one or more voltage setting elements may be provided in each state setting circuit, or a plurality of voltage setting elements may be increased.

以上説明したように、本発明の半導体装置の回路構成によれば、半導体装置の端子数を大幅に増やす必要がないとともに、半導体装置の組立後に簡単な回路構成で所望の特性値の調整ができるようになるので、小型で特性精度の良い半導体装置を容易に使用できるようになるという効果がある。更に、特性精度が良いので歩留まりが良くなり、半導体装置の単価が抑えられるという効果もある。   As described above, according to the circuit configuration of the semiconductor device of the present invention, it is not necessary to greatly increase the number of terminals of the semiconductor device, and a desired characteristic value can be adjusted with a simple circuit configuration after the semiconductor device is assembled. As a result, there is an effect that a small-sized semiconductor device with good characteristic accuracy can be easily used. Further, since the characteristic accuracy is good, the yield is improved and the unit price of the semiconductor device can be suppressed.

本発明の第1の実施の形態を示す回路図、A circuit diagram showing a first embodiment of the present invention, 本発明に使用するヒューズ素子の形状例を示す形状図、Shape diagram showing a shape example of the fuse element used in the present invention, 本発明の第1の実施の形態の他の例を示す回路図、The circuit diagram which shows the other example of the 1st Embodiment of this invention, 本発明の第2の実施の形態を示す回路図、A circuit diagram showing a second embodiment of the present invention,

符号の説明Explanation of symbols

10 :半導体チップ(半導体装置)
T1 :端子(特性調整用端子)
SL1〜SL4:状態設定回路
11a〜11c:ヒューズ素子
12a〜12f:電圧設定素子(ダイオード素子)
13 :電流源回路


10: Semiconductor chip (semiconductor device)
T1: Terminal (Characteristic adjustment terminal)
SL1 to SL4: state setting circuits 11a to 11c: fuse elements 12a to 12f: voltage setting elements (diode elements)
13: Current source circuit


Claims (2)

1チップの集積回路として形成されるとともに電気的特性値の調整が必要な内部回路を有する半導体装置において、
一端が基準電位に接続されたヒューズ素子と、前記ヒューズ素子の他端と特性調整用端子との間に接続された電圧設定部と、からなる状態設定回路を複数個有し、
前記電圧設定部は各々異なる数の電圧設定素子が接続された回路もしくは前記電圧設定素子のない配線のみの回路から構成され、
前記電圧設定部と前記ヒューズ素子とのそれぞれの接続点を前記内部回路に接続することとともに、前記特性調整用端子に所定の電圧を印加することにより前記状態回路の所定のヒューズ素子を切断するようにしたことを特徴とする半導体装置。
In a semiconductor device having an internal circuit formed as a one-chip integrated circuit and requiring adjustment of electrical characteristic values,
A plurality of state setting circuits comprising a fuse element having one end connected to a reference potential, and a voltage setting unit connected between the other end of the fuse element and a characteristic adjustment terminal;
The voltage setting unit is composed of a circuit in which a different number of voltage setting elements are connected or a circuit having only the wiring without the voltage setting element,
The connection point between the voltage setting unit and the fuse element is connected to the internal circuit, and the predetermined fuse element of the state circuit is disconnected by applying a predetermined voltage to the characteristic adjustment terminal. A semiconductor device characterized by that.
1チップの集積回路として形成されるとともに電気的特性値の調整が必要な内部回路を有する半導体装置において、
半導体装置の基準電位と特性調整用端子との間に、ヒューズ素子としての機能を有する電圧設定素子が各々異なる数接続された状態設定回路を複数個有し、
一端を基準電位に接続された前記電圧設定素子の他端側を前記内部回路にそれぞ
することとともに、前記特性調整用端子に所定の電圧を印加することにより前記状態回路の所定のヒューズ素子を切断するようにしたことを特徴とする半導体装置。
In a semiconductor device having an internal circuit formed as a one-chip integrated circuit and requiring adjustment of electrical characteristic values,
A plurality of state setting circuits each having a different number of voltage setting elements functioning as fuse elements connected between the reference potential of the semiconductor device and the characteristic adjustment terminal,
The other end side of the voltage setting element, one end of which is connected to a reference potential, is connected to the internal circuit, and a predetermined voltage is applied to the characteristic adjustment terminal to thereby apply a predetermined fuse element of the state circuit. A semiconductor device characterized by being cut.
JP2005033801A 2005-02-10 2005-02-10 Semiconductor device Pending JP2005191590A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005033801A JP2005191590A (en) 2005-02-10 2005-02-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005033801A JP2005191590A (en) 2005-02-10 2005-02-10 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP24279495A Division JP3927251B2 (en) 1995-09-21 1995-09-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2005191590A true JP2005191590A (en) 2005-07-14

Family

ID=34792769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005033801A Pending JP2005191590A (en) 2005-02-10 2005-02-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2005191590A (en)

Similar Documents

Publication Publication Date Title
JP4279825B2 (en) Integrated circuit die with temperature detection circuit and temperature detection circuit calibration system and method
JP3587300B2 (en) Integrated circuit device
JP2020035804A (en) Semiconductor device, electronic circuit, and inspection method of semiconductor device
US7616417B2 (en) Semiconductor device including protection circuit and switch circuit and its testing method
JP2007067340A (en) Semiconductor integrated circuit device and method for testing the same
JP2871661B1 (en) Semiconductor device
JP5435713B2 (en) Semiconductor device manufacturing method, manufacturing program, and semiconductor device
JP5014609B2 (en) Trimming circuit, electronic circuit and trimming control system
JP2006196159A (en) Multi-chip package having signature identification device capable of directly reading device information of individual chip
CN100414478C (en) Method and system for powering integrated circuits, and integrated circuits specially designed for use therein
JP4073552B2 (en) Semiconductor device
JP3927251B2 (en) Semiconductor device
JP2005191590A (en) Semiconductor device
KR102034008B1 (en) Semiconductor integrated circuit and method of driving the same
US20220412811A1 (en) Semiconductor module and method of manufacturing semiconductor module
JPH11121683A (en) Semiconductor integrated circuit
KR100673002B1 (en) E-Fuse Circuit Using Leakage Current Path of Transistor
US6944073B2 (en) Semiconductor integrated circuit device
US20050275062A1 (en) Semiconductor bare chip, method of recording ID information thereon, and method of identifying the same
JP2005308503A (en) Semiconductor sensor
JP2743457B2 (en) Semiconductor device
JPH0354841A (en) BiCMOS semiconductor device
US6747468B2 (en) Circuit trimming of packaged IC chip
JP2005302755A (en) Semiconductor integrated circuit and management method therefor
JP2024069066A (en) Semiconductor device and test method