JP2005116981A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of an insulated gate field effect transistor (SOIIGFET) formed on an SOI substrate.
An n-type IGFET (Tn) and a p-type IGFET (Tp) include a support substrate 1, a buried oxide film 2 formed on the support substrate 1, and a buried silicon film formed on the buried oxide film 2. 12, a buried gate insulating film 10 formed on the buried silicon film 12, and a single crystal silicon thin film 3 formed on the buried gate insulating film 10. The n-type source diffusion layer 6 and the n-type n-type drain diffusion layer 7 of the n-type IGFET (Tn) and the p-type source diffusion layer 8 and the n-type n-type drain diffusion layer 9 of the p-type IGFET (Tp) are Formed on the crystalline silicon thin film 3, the gate electrode 5 is formed on the single crystal silicon thin film 3 via the gate insulating film 4. No buried gate electrode is formed in the buried silicon film 12 below the gate electrode 5 by selectively introducing a high concentration impurity.
[Selection] FIG.

Description

  The present invention relates to a semiconductor device having an insulated gate field effect transistor, and more particularly to a technique effective when applied to a semiconductor device having an insulated gate field effect transistor provided in a semiconductor thin film on an insulating film.

  An insulating gate type field effect transistor (hereinafter referred to as SOIIGFET) formed on a supporting substrate and a thin single crystal thin film (referred to as SOI (Silicon On Insulator)) provided on the supporting substrate via an insulating film is provided. It is known.

  In addition, in the above SOIIGFET, a so-called double gate structure insulated gate field effect transistor is also known in which a buried gate electrode is provided via a second gate insulating film at a position facing the gate electrode below the channel region. Shows the cross-sectional structure. In the figure, reference numeral 100 denotes a supporting substrate, 101 denotes a buried oxide film, 110 denotes a single crystal silicon film, 102 denotes a buried gate electrode, 103 denotes a buried gate insulating film, 104 denotes a gate insulating film, 105 denotes a gate electrode, and 106 denotes source diffusion. Reference numeral 107 denotes a drain diffusion layer, and reference numeral 108 denotes an element isolation trench.

The double gate structure is an ideal structure of a transistor, and the channel region is controlled from both the upper and lower directions by electrically connecting the gate electrode 105 and the buried gate electrode 102 to the same potential. It is theoretically predicted that if the film 110 is sufficiently thin, the channel potential can be approximated by a rectangular shape, and the drive current will be twice or more. Note that a double gate transistor is described in, for example, Japanese Patent Application Laid-Open No. 2001-284596 (Patent Document 1).
JP 2001-284596 A

  In the SOI II FET including the above-mentioned double gate transistor, the structure in which the single crystal silicon film is sufficiently thin and the impurity introduced into the channel region is extremely low in concentration is called a fully depleted type, and the accumulation state Therefore, the punch-through path is difficult to occur.

Therefore, it is essential that future ultrafine IGFETs be formed from a normal semiconductor substrate to an SOI substrate. This is because, in an ultra-fine IGFET using a normal semiconductor substrate, the accumulation region and the neutral region are necessarily adjacent to the inversion layer in the semiconductor substrate region, so that the punch-through current through this accumulation region is eliminated. Therefore, it is necessary to increase the impurity concentration of the substrate. However, in the ultrafine IGFET having a gate length of 50 nm or less, the required maximum impurity concentration is 5 × 10 ¹⁸ / cm ³ or more. This is because the drain leakage current (GIDL) caused by the gate electric field and the drain-substrate leakage current due to the band-to-band tunneling current cannot be ignored in this state.

  The fully-depleted double gate SOIIGFET has an ideal structure as an ultrafine IGFET that can solve the above-described problem of leakage current and can be increased in driving current, but the ultrafine IGFET has not yet been put into practical use.

  Various manufacturing methods have been proposed for conventionally known double gate SOIIGFETs. In the technique proposed by the present inventors, the buried gate electrode 102 shown in FIG. 2 is composed of a low resistance diffusion layer formed by ion-implanting impurities at a high concentration into the single crystal silicon film 110, and the gate electrode 105 is electrically connected.

Further, in the known double gate SOIIGFET, the low resistance diffusion layer constituting the buried gate electrode 102 is formed by ion implantation of impurities using acceleration energy penetrating the buried gate insulating film 103 and the single crystal silicon film 110. . However, in such high-energy ion implantation, contaminants adhere to the vicinity of the sample surface (referred to as beamline contamination) due to crystal damage in the penetration region or sputtering phenomenon from the ion beam path partition in the ion implantation apparatus. In other words, the present technology cannot avoid the introduction of impurities of about 1 × 10 ⁻³ times the injection amount), and it has been impossible to avoid a decrease in the yield of good products.

  Further, along with the miniaturization of the double gate SOIIGFET, the difficulty of electrical connection between the gate electrode and the buried gate electrode increases dramatically. With the miniaturization of the gate electrode, it is also required from the viewpoint of reducing the parasitic capacitance that the embedded gate electrode is also miniaturized and aligned in a self-aligned relationship with the same dimensions. In order to form a miniaturized buried gate electrode by high-concentration ion implantation, it is possible to reduce the size of the implantation blocking mask. However, with the miniaturization, the influence of the sidewall of the implantation blocking mask increases, so The relative wraparound amount increases. This relatively corresponds to an increase in the gate length of the buried gate electrode and causes an increase in parasitic capacitance.

  Furthermore, when the buried gate electrode is formed using the ion implantation method, the implanted impurity has a depth direction distribution similar to a Gaussian distribution, so that the impurity concentration in the region adjacent to the buried gate insulating film is sufficiently high. If an attempt is made to suppress depletion of the buried gate electrode, impurities are inevitably distributed at a high concentration in the buried gate insulating film and the single crystal silicon film. In addition, the implanted impurities are inevitably diffused outside the desired region due to the influence of heat treatment in the subsequent manufacturing process, resulting in an increase in parasitic capacitance. Impurity diffusion into the single crystal silicon film acts against the fully depleted operation and causes a fundamental contradiction.

  Furthermore, since the threshold voltage of a fully depleted SOI IIFET is principally determined only by the work function of each of the gate electrode and the buried gate electrode, it can be formed in a semiconductor substrate like an IGFET manufactured on a normal semiconductor substrate. There is a problem that a method for controlling the threshold voltage by an arbitrary amount of ion implantation into the electrode cannot be applied. For example, in order to design each of the threshold voltages of a plurality of fully depleted SOIIGFETs to a desired value, each IGFET must be manufactured using a different gate material, which is impossible in practice. is there.

  The first object of the present invention is to avoid the difficulty caused by the manufacturing method of a double gate SOIIGFET, which is an ideal structure as an ultrafine IGFET, and to improve the yield of good products even in the current semiconductor device manufacturing technology. It is to provide a structure capable of improving the performance.

  The second object of the present invention is to provide a technique for solving various problems related to the electrical connection between the gate electrode and the buried gate electrode 6 in the double gate SOIIGFET.

  The third object of the present invention is to solve in principle the essential problems of the prior art in which the buried gate electrode of the double gate type SOIIIFET is formed by high concentration ion implantation, and to further improve the performance of the fully depleted type SOIIIFET. It is to provide a new structure that can be made possible.

  The fourth object of the present invention is to provide a means for solving the fundamental problem concerning the threshold voltage control in the conventional fully depleted SOIIGFET, and without changing the gate material even in the adjacent IGFET in the same substrate. An object of the present invention is to provide a new structure capable of setting an arbitrary threshold voltage while maintaining a fully depleted type characteristic.

  Another object of the present invention is to provide a double-gate structure in a fully depleted SOI IIFET using a technique for improving mobility by controlling semiconductor physical properties, for example, a technique for imparting strain such as modifying the lattice constant of a silicon single crystal. The concept of further improving the performance by enabling the combination with such a transistor structure corresponds to the fact that has not been proposed previously. That is, it is an object of the present invention to provide a new structure capable of further improving the performance of a fully depleted SOIIGFET having a strained silicon thin film while maintaining a state in which the lattice constant of a silicon single crystal is modified.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The IGFET constituting the semiconductor device of the present invention includes a support substrate, a first insulating film formed on the support substrate, a first semiconductor film formed on the first insulating film, and the first semiconductor film. A source and a drain are formed in the second semiconductor film of a semiconductor substrate including a second insulating film formed thereon and a second semiconductor film formed on the second insulating film, and the source and drain are formed A gate electrode is formed on the second semiconductor film via a third insulating film, and a buried gate electrode by selective introduction of a high concentration impurity is not formed in the first semiconductor film below the gate electrode.

The operation principle of the SOIIGFET according to the present invention will be described with reference to the equivalent circuit diagram of FIG. Although FIG. 1 shows the complementary SOIIGFET, in order to facilitate understanding, only the n-type IGFET on the left side of the figure is focused. That is, attention is focused on the T _1N , T _2N , and C ₁ regions. For the left half p-type IGFET, in principle, exactly the same operation is expected only when the conduction / non-conduction relationship is reversed.

In the figure, T _1N represents a fully depleted SOIIGFET configured as a thin semiconductor thin film, C ₁ represents a capacitive element connected in series to the substrate terminal of T _1N , and the embedded semiconductor film in the multilayer SOI substrate described above It is an insulating film capacitive element based on the thin insulating film comprised above. T _2N represents an auxiliary transistor equivalently configured in a buried semiconductor film separated from the support substrate by an insulating film, but the source terminal electrically connected in series with the insulating film capacitor element C ₁ has a source A high concentration diffusion layer corresponding to the diffusion layer or a PN junction is not intentionally introduced. The introduction of the source diffusion layer is the aforementioned problem itself. The transistor operation in the structure without introducing the source diffusion layer is titled “I-MOS: A Novel Semiconductor Device with a Subthreshold Slope lower than kT / q” by Plimmer et al., 2002 International Electron Devices Meeting, pages 289-292. It has been verified theoretically and experimentally.

In the equivalent circuit of FIG. 1, the gate electrode terminal of T _2N is connected to the drain diffusion layer of T _1N . This is an equivalent configuration in which a high-concentration drain diffusion layer formed in a thin T _1N semiconductor thin film acts as a gate electrode, a thin insulating film existing below the gate insulating film serves as a gate insulating film, and a buried semiconductor film surface region serves as a channel. The operation mechanism of the auxiliary transistor is shown. An input terminal IN is connected to the substrate terminal of the T _1N via a T gate electrode of _1N and T _2N and C _1,. The input IN potential that makes T _1N conductive is defined as “1”, and the input IN potential that makes nonconductive is defined as “0”.

When the input IN potential and the output terminal OUT potential are both “1”, T _2N is also in a conductive state, and the substrate terminal of T _1N is in the “1” state via C ₁ . That is, the threshold voltage of T _1N is lowered and acts to further increase the conduction current. This action is the same as the double gate structure. The fundamental difference from the double gate structure from the viewpoint of the equivalent circuit is that the double gate structure has the input IN potential applied directly to the substrate terminal of T _1N via C ₁ , whereas in the structure of the present invention, It is a point applied via T _2N .

In the present invention structure, OUT potential acts to some extent immediately further increase the conduction current of T _1N substrate terminal of the T _1N at a high state. This means that the inverter operation works more effectively at the initial stage of input switching, and corresponds to the action particularly effectively in the dynamic operation. Note that since it is not necessary to form a barrier component such as a PN junction at the source terminal of T _2N, the “1” potential remains at the T _2N potential until the IN potential switches to “0” potential even when the OUT potential decreases. It is held by a current path through the substrate region. T P-type substrate terminal potential is to switch from "0" to follow to "1" to the IN shown in the right half of Figure 1 of _1N IGFET, is accelerated by T _1P, and T _2P, the T _1N A high-speed transition to a non-conductive state, that is, a steep gate voltage dependency of the source / drain current is realized.

  In the structure of the present invention, it is not necessary to introduce a high-concentration impurity into a region corresponding to the buried gate electrode, so that the first and second problems related to the double gate structure are fundamentally solved. That is, beam line contamination due to high concentration ion implantation, problems related to electrical connection between the upper gate electrode and the buried gate electrode, depletion in the buried gate electrode, high concentration impurities in the lower gate insulating film, and single crystal silicon film This eliminates problems such as contamination and increase in parasitic capacitance.

In the present invention, in order to solve the third problem, the beam line contamination in the ion implantation technique can be ignored in the buried semiconductor film region via C ₁ under the substrate terminal of T _1N , that is, the source terminal region of T _2N. By implanting an amount of impurities, the threshold voltage of T _1N can be finely adjusted to a desired value. Although the threshold voltage is essentially controllable by a work function based on the gate electrode material, in the structure of the present invention, the threshold voltage is also applied to adjacent transistors having the same gate electrode material by introducing impurities into the buried semiconductor film region. The voltage can be changed. In a fully depleted SOIIGFET, the threshold voltage is reduced by using a refractory metal material having a work function corresponding to the vicinity of the center of the forbidden band of a silicon single crystal or a silicide thereof as the upper gate electrode material. Can be set near zero. In the structure of the present invention, the threshold voltage can be easily moved by about 0.2 V by introducing impurities of about 10 ¹⁸ cm ⁻³ .

  In the normal SOI substrate, the threshold voltage can be controlled by applying a voltage to the support substrate. However, since the (embedded) insulating film on the support substrate is usually thicker than 100 nm, a high voltage of several tens of volts can be applied. It is practically impossible to control individual IGFETs independently. Although the present invention is based on the SOI structure, threshold voltage control similar to that of a normal substrate is possible, and the field of application of fully depleted SOIIGFETs for which application fields are limited can be dramatically expanded. In particular, fields that can be applied as ultra-fine semiconductor devices with low power consumption and large driving capability are dramatically expanded.

  In the semiconductor device according to the present invention, a multi-layer SOI substrate is manufactured in a state in which lattice strain is preliminarily applied to an ultrathin single crystal silicon film to be manufactured, and then described in detail in the embodiment of the present invention. It is only necessary to manufacture the semiconductor device according to the method described. The points to be noted in the production of the above-mentioned multilayer structure SOI substrate will be described in detail in the embodiment of the present invention. However, the bonding performed after the bonding process of the substrate to be the support substrate and the ultrathin single crystal silicon film is performed. The heat treatment is performed at a low temperature of about 900 ° C. or less so that the lattice strain is not relaxed. High current operation is further improved by the characteristics of the semiconductor device according to the invention and the effect of increasing mobility by the strained semiconductor thin film.

For the drains of T _2N and T _2P configured in the embedded semiconductor film separated from the support substrate by the insulating film, select the thin semiconductor thin film including T _1N and T _1P and the thin embedded insulating film below it. It can be formed by selectively removing and selectively forming any one of a high-concentration diffusion layer, a Schottky junction, or an ohmic junction in the buried semiconductor film region of the exposed removal region.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  High performance of fully depleted SOIIGFET can be realized.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. The other part or all of the modifications, details, and supplementary explanations are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless explicitly stated or in principle limited to a specific number in principle It is not limited to the specific number, and may be a specific number or more.

  Further, in the following embodiments, it is needless to say that the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Yes.

  Similarly, in the following embodiments, when referring to the shape and positional relationship of components and the like, the shape and the like of the component are substantially changed unless specifically stated or otherwise considered in principle. Approximate or similar. The same applies to the above numerical values and ranges.

  Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. It goes without saying that the material, conductivity type, manufacturing conditions, and the like of each part are not limited to those described in the present embodiment, and many modifications can be made.

(Embodiment 1)
3 to 11 are main part cross-sectional views showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps, and FIGS. 12 and 13 are schematic plan views of the semiconductor device. For convenience of explanation, the description will be made with the conductivity types of the semiconductor substrate and the semiconductor film fixed, but the combination of the conductivity types may be arbitrary, and is not limited to the conductivity types described in this embodiment.

First, as shown in FIG. 3, a silicon oxide film 2a having a thickness of 100 nm is obtained by thermally oxidizing a p-type single crystal silicon substrate having a surface orientation (100), a resistivity of 10 Ω · cm, a diameter of 20 cm, and a main surface mirror-polished. The support substrate 1 was produced by forming. On the other hand, a single crystal silicon substrate 40 having the same specifications as that of the support substrate 1 is separately prepared, and its main surface is thermally oxidized to form a 1.8 nm thick silicon oxide film (not shown). By nitriding the surface of the film with NO gas to form a silicon nitride film (not shown) having a thickness of 0.2 nm, a thin buried gate insulating film 10 having a laminated structure of a silicon oxide film and a silicon nitride film is formed. did. The silicon nitride film has a relative dielectric constant larger than that of the silicon oxide film, and the optical film thickness electrically equivalent to the silicon oxide film corresponds to about twice the thickness. Thereafter, an amorphous silicon film 12a having a thickness of 100 nm was deposited on the surface of the buried gate insulating film 10 by a CVD method using Si ₂ H ₆ gas.

Next, in order to remove the particulate matter that hinders the flatness of the main surface generated by the CVD process, etc., after performing extremely light surface polishing not containing abrasive grains, the known ultra-thin SOI substrate manufacturing method is applied. Based on this, ion implantation of hydrogen was performed. The injection amount was 5 × 10 ¹⁶ / cm ² . As a result of this ion implantation, a crystal defect layer 41 was formed at a depth of about 40 nm from the main surface of the single crystal silicon substrate 40.

  Next, the supporting substrate 1 having the silicon oxide film 2a formed on the main surface and the single crystal silicon substrate 40 having the amorphous silicon film 12a formed on the main surface are subjected to a hydrophilic treatment, and then at room temperature. The main surfaces of each other were brought into close contact with each other. Next, when the two bonded silicon substrates are heated to 500 ° C., formation and increase of microvoids in the crystal defect layer 41 of the single crystal silicon substrate 40 occur, and the crystal defect layer 41 and the single crystal silicon substrate Peeling occurred at the interface with 40. Further, the single crystal silicon thin film 3 having a thickness of about 20 nm was formed in the crystal defect layer 41, and the amorphous silicon film 12a was in close contact with the support substrate 1 through the silicon oxide film 2a (FIG. 4).

  Next, when high temperature heat treatment at 1100 ° C. is performed on the two bonded silicon substrates, the bonding strength between the amorphous silicon film 12a and the silicon oxide film 2a is remarkably improved, and the bonding is similar to that of a normal single crystal silicon substrate. It became strength. From this state, the peeled surface of the single crystal silicon thin film 3 is mirror-polished by a surface polishing method that does not include abrasive grains, so that the thin embedded gate insulating film 10, the embedded silicon film 12, and the thick embedded are formed below the single crystal silicon thin film 3. An SOI substrate having the oxide film 2 laminated on the support substrate 1 was manufactured. Note that the buried silicon film 12 changed from an amorphous silicon film to a polycrystalline silicon film during the high-temperature heat treatment process.

  Next, as shown in FIG. 5, element isolation grooves 11 were formed on the SOI substrate by a known method. The element isolation trench 11 has a depth reaching the buried oxide film 2 from the surface of the single crystal silicon thin film 3, and the buried silicon film 12 is also separated from each other by the element isolation trench 11. A groove 13 having a depth reaching the embedded silicon film 12 from the surface of the single crystal silicon thin film 3 was formed in a region (center portion in the figure) separating the n-type IGFET formation region and the p-type IGFET formation region.

  Next, after cleaning the surface of the single crystal silicon thin film 3 to reduce its thickness to about 10 nm, the surface is thermally oxidized to form a 1.8 nm thick silicon oxide film (not shown), Subsequently, the surface of the silicon oxide film is nitrided with NO gas to form a silicon nitride film (not shown) having a thickness of 0.2 nm, thereby forming a gate insulating film having a laminated structure of the silicon oxide film and the silicon nitride film. 4 was formed.

  Next, as shown in FIG. 6, a gate electrode 5 made of a polycrystalline silicon film was formed on the gate insulating film 4. In order to form the gate electrode 5, a polycrystalline silicon film having a thickness of 60 nm and a silicon nitride film 14 having a thickness of 40 nm are deposited on the gate insulating film 4 by a CVD method, and then the silicon nitride film 14 and the polycrystalline silicon film are formed. And patterning. The silicon nitride film 14 is an insulating film that protects the surface of the gate electrode 5. The gate length of the gate electrode 5 was 50 nm, and the height of the gate electrode 5 was 100 nm including the silicon nitride film 14. In the present embodiment, no impurity for reducing the resistance is introduced into any of the gate electrodes 5 of the n-type IGFET and the p-type IGFET. In the above-described step of patterning the silicon nitride film 14 and the polycrystalline silicon film, the gate insulating film 4 in a region other than the lower portion of the gate electrode 5 is removed, and the surface of the single crystal silicon thin film 3 is exposed.

Next, as shown in FIG. 7, As ions are applied to the single crystal silicon thin film 3 in the n-type IGFET formation region (left side portion of the figure), and the single crystal silicon thin film 3 in the p-type IGFET formation region (right side portion of the figure). Are ion-implanted under the conditions of acceleration energy of 1 keV and 900 eV and a dose of 4 × 10 ¹⁵ / cm ² , respectively, so that the n-type source diffusion layer 6 and n A type drain diffusion layer 7 was formed, and a p type source diffusion layer 8 and a p type drain diffusion layer 9 were formed in the single crystal silicon thin film 3 in the p type IGFET formation region. In addition, an n-type diffusion layer 15 and a p-type diffusion layer 16 are also formed at the bottom of the groove 13 that separates the n-type IGFET formation region and the p-type IGFET formation region by the ion implantation. Note that, by the ion implantation, most of the single crystal silicon thin film 3 was made amorphous, and only the bottom region kept slightly single crystal. Then, the substrate surface temperature was raised to about 1200 ° C. by carbon dioxide laser irradiation with an irradiation time of about 1/1000 seconds, and the thermal activation treatment of the impurities introduced by the ion implantation was performed.

  Next, as shown in FIG. 8, a silicon oxide film 17 having a thickness of 70 nm is deposited on the substrate by CVD, and then anisotropic dry etching is performed on the silicon oxide film to form the sidewall of the gate electrode 5. Sidewall spacers 17s are formed. At this time, the silicon oxide film 17 is buried in the trench 13 to separate the n-type IGFET formation region and the p-type IGFET formation region.

  Next, as shown in FIG. 9, a silicon film is formed on the n-type source diffusion layer 6, the n-type drain diffusion layer 7, the p-type source diffusion layer 8 and the p-type drain diffusion layer 9 by selective epitaxial growth. After selectively depositing, an impurity (As or B) having the same conductivity type as that of the lower diffusion layer was ion-implanted into these silicon films. As a result, an n-type stacked source diffusion layer 26 is formed above the n-type source diffusion layer 6, an n-type stacked drain diffusion layer 27 is formed above the n-type drain diffusion layer 7, and the p-type source diffusion layer 8 A p-type stacked source diffusion layer 28 was formed on the top, and a p-type stacked drain diffusion layer 29 was formed on the p-type drain diffusion layer 9. Thereafter, the silicon nitride film 14 above the gate electrode 5 was removed by etching.

  Next, a Ni (nickel) film is deposited on the substrate by sputtering, followed by heat treatment at 450 ° C., the gate electrode 5, the n-type stacked source diffusion layer 26, the n-type stacked drain diffusion layer 27, and the p-type stacked source diffusion. After reacting each of the layer 28 and the p-type stacked drain diffusion layer 29 with the Ni film, the unreacted Ni film is removed by etching. The Ni film was etched using a mixed aqueous solution of hydrochloric acid and hydrogen peroxide. Thus, each of the gate electrode 5 made of a silicon film, the n-type stacked source diffusion layer 26, the n-type stacked drain diffusion layer 27, the p-type stacked source diffusion layer 28, and the p-type stacked drain diffusion layer 29 becomes a Ni silicide film. Reduced resistance. Through the steps up to here, an n-type IGFET (Tn) and a p-type IGFET (Tp) are formed (FIG. 10).

  Next, as shown in FIG. 11, a silicon oxide film is deposited on the substrate by a CVD method to form an interlayer insulating film 21, and then the surface of the interlayer insulating film 21 is planarized by a chemical mechanical polishing method. N-type stacked source diffusion layer 26, n-type stacked drain diffusion layer 27, p-type stacked source diffusion layer 28, p-type stacked drain diffusion layer 29, n-type diffusion layer 15, and p-type diffusion layer 16. The insulating film 21 (and the silicon oxide film 17) was etched to form the connection hole 22.

  Thereafter, a metal film is deposited on the interlayer insulating film 21 including the inside of the connection hole 22 by a sputtering method, and then the metal film on the interlayer insulating film 21 is removed by a chemical mechanical polishing method. The output terminal electrodes 31 and 32, the power supply terminal electrode 33, and the input terminal electrode 34 were formed. Further, a second interlayer insulating film (not shown) is formed on the interlayer insulating film 21, and then a wiring (not shown) is formed on the second interlayer insulating film, thereby completing the complementary IGFET (n Type semiconductor device having type IGFET (Tn) and p type IGFET (Tp)) was manufactured.

  In the present embodiment, since the gate electrodes 5 of the n-type IGFET (Tn) and the p-type IGFET (Tp) are made of a metal silicide film, the n-type IGFET (Tn) is used despite being a fully depleted SOIIGFET. ) And p-type IGFET (Tp), the threshold voltage could be set to almost 0V. In addition, despite the fact that the single crystal silicon thin film 3 constituting the channel is finally made as thin as 10 nm, the source and drain regions are constituted by a stacked structure, and most of the stacked structure is a metal silicide film. As a result, the problems of increased contact resistance and series resistance between the semiconductor and the metal silicide film could be avoided.

  12 and 13 are schematic plan views of a semiconductor device manufactured based on the present embodiment, that is, a complementary IGFET, and numerals indicating each part are the same as those in FIG. The left half of FIG. 12 shows n-type IGFET (Tn), and the right half shows p-type IGFET (Tp).

  The gate electrode 5 common to the n-type IGFET (Tn) and the p-type IGFET (Tp) is connected to the wiring 36 via the connection electrode 35 in the same layer as the electrodes (30 to 34). The n-type diffusion layer 15 and the p-type diffusion layer 16 are connected to the wiring 36 through the input terminal electrode 34. The output terminal electrodes 31 and 32 are connected to each other via a wiring 37. A wiring 38 is formed on the ground potential electrode 30, and a wiring 39 is formed on the power supply terminal electrode 33.

FIG. 1 is a circuit diagram illustrating a circuit configuration of a semiconductor device manufactured based on the complementary IGFET of this embodiment. In the figure, T _1N and T _1P indicate an n-type IGFET (Tn) and a p-type IGFET (Tp) in a pair of complementary IGFETs, which are formed in the single crystal silicon thin film 3 in this embodiment. T _2N and T _2P are _IGFETs each having an n-type drain diffusion layer 7 and a p-type drain diffusion layer 9 of T _1N and T _1P as gate electrodes, and an n-type diffusion layer 15 and a p-type diffusion layer 16 as drain diffusion layers, respectively. The source regions of T _2N and T _2P are the buried silicon film 12 immediately below the channel at T _1N and T _1P .

The amount of charge in the buried silicon film 12 immediately below the channel controls the T _1N and T _1P channels as in the double gate structure SOIIGFET. R ₁ and R ₂ are resistance components representing leakage current components flowing outside the surface channel between the source and drain at T _2N and T _2P , and diffusion current, punch-through current, and polycrystalline Si film defects in the intrinsic semiconductor substrate region This represents the leakage current component and the like.

In the circuit configuration of FIG. 1, when the input terminal is switched from the ground potential to a positive high potential, T _1N becomes conductive, and the output terminal potential is converted from the high potential to the ground potential. In the initial situation where the output terminal potential is still held at a high potential in this state, the output terminal potential controls the substrate potential of T _1N through T _2N and C _1, to higher current operation of the T _1N That is, the conversion of the output potential from the high potential to the ground potential is performed at a higher speed.

T _1P is cut off when a positive high potential is applied to the input terminal, but the substrate potential of T _1P is held at a high potential via C ₂ as long as the input terminal is at a high potential. It works to strengthen the _1P blocking state, and works to realize faster conversion of the output terminal potential from the high potential to the ground potential. When the input terminal is switched from a positive high potential to the ground potential, an operation opposite to that described above occurs in the complementary IGFET. That is, T _2N and T _2P act so as to further increase the inverter operating speed by T _1N and T _1P .

When focusing on the IGFET alone, T _2N or T _2P reduces the threshold voltage so that the substrate potential of T _1N or T _1P becomes larger in the conductive state and accelerates the cut-off state in the cut-off state. This has the effect of acting so that the threshold voltage increases. In the circuit configuration shown in FIG. 1 the substrate potential of T _1N or T _1P is controlled via the drain region lower portion of the T _1N or T _1P.

In general, in the IGFET, the channel width is designed to be larger than the channel length. In such a layout configuration, the channel resistance due to T _2N or T _2P is reduced, and the inverter operation speed can be increased more effectively. An increase in the inverter operating speed can be expected even in a known double-gate structure SOIIGFET. In this case, as the gate line width is reduced, the buried gate electrode as viewed from the connection with the upper gate electrode extending in the channel length direction is used. As the resistance of the inverter also increases, the effect of increasing the inverter operating speed is hindered with the miniaturization. That is, from the viewpoint of miniaturization of the semiconductor device, the relative speed-up effect of the inverter according to the present embodiment has an effect that it is superior to the double gate structure.

FIG. 14 is a diagram showing waveform transitions at the representative nodes in FIG. 1 for the operation mechanism, and shows the correlation between the input (IN) waveform, the output (OUT) waveform, and T _1N and T _1P substrate terminal potentials. Show. When the IN node switches from the 0 level (Vss) to the 1 level (Vcc), the OUT node transitions from the 1 level to the 0 level when the T _1N switches from the OFF state to the ON state, and the T _1P switches from the ON state to the OFF state. However, when the OUT node is at 1 level and close to 1 level, T _2P is OFF and T _2N is ON, and the capacitive elements C ₁ and C ₂ are raised to 1 level. As a result, T _1N is turned on more quickly with a larger current, and T _1P is turned on faster as the leakage current is further reduced.

In the state where the IN node is maintained at 1 level, 1 level is transmitted to the T _1N and T _1P substrate terminal potentials with the time constant via the resistance components R ₁ and R ₂ , so that 1 level is maintained. When the IN node switches from the 1 level to the 0 level, the OUT node starts to transition from the 0 level to the 1 level by switching the T _1N from the ON state to the OFF state and T _1P from the OFF state to the ON state. When the OUT node is at the 0 level and close to the 0 level, T _2P is ON and T _2N is OFF, causing the capacitive elements C ₁ and C ₂ to approach the 0 level. As a result, T _1N is actuated faster as the leakage current is reduced, and T _1P is actuated as soon as the current is increased and the ON state is activated more quickly. In a state where the IN node is maintained at 0 level, the 0 level is transmitted to the substrate terminal potentials of T _1N and T _1P with the time constant via the resistance components R ₁ and R ₂ , so that the 0 level is maintained.

  In the semiconductor device according to the present embodiment, various problems relating to the introduction of the high-concentration impurity region constituting the buried gate electrode 102 as in the conventionally known double gate structure shown in FIG. . Therefore, the problem of unintentionally introducing a high concentration impurity into the single crystal silicon film 3 where the channel is formed and the problem of deterioration of the buried gate insulating film do not occur. It has been confirmed that the semiconductor device according to the present embodiment exhibits a high-speed operation that is approximately 1.5 times the switching speed of an inverter manufactured using a conventionally known SOI substrate.

(Embodiment 2)
FIG. 15 is a circuit diagram of a semiconductor device according to the second embodiment. In the manufacture of the semiconductor device in the present embodiment, the n-type diffusion layer 15 and the p-type diffusion layer 16 in the first embodiment are not formed in the buried silicon film 12, and the Schottky is formed by the wiring metal and the buried silicon film 12. The input terminal and the buried silicon film 12 were connected through the junction. Other manufacturing steps were performed based on the first embodiment.

In FIG. 15, the drain junctions of the IGFETs indicated as T _2N and T _2P are Schottky junctions. R ₁ and R ₂ correspond to respective resistance components passing through the buried silicon film 12 from the drain junction of T _2N and T _2P to the source region. In the circuit configuration shown in FIG. 15 as well, the substrate potentials of T _1N and T _{1P depend on} the respective embedded capacitors C ₁ , due to the conduction component via T _2N and T _2P and the conduction component via the internal resistances R ₁ and R ₂ . The substrate potential of each IGFET constituting the inverter via C ₂ is controlled by the potential applied to the gate electrode 5, and acts to reduce the leakage current more in the conduction state and to a larger current in the interruption state.

Also, the output potential of the inverter approaches the ground potential by conduction of T _1N, if the state of a high potential so that the gate potential be blocked T _2N keep the T _1N in a conductive state, T _1N and T _1P The substrate potential is maintained at a high potential state via R ₁ and R ₂ so that the output potential is brought closer to the ground potential more quickly.

In this state, T _2P is in a cut-off state and acts to further reduce the leakage current. That is, in the semiconductor device according to the present embodiment, an effect that the inverter operation is performed at a higher speed occurs. A semiconductor device in which a desired amount of impurities is introduced into the buried silicon film 12 so that the Schottky junction in FIG. 15 is an ohmic junction between the metal and the semiconductor was also manufactured. Therefore, there is no problem even if the Schottky junction is replaced with an ohmic junction.

(Embodiment 3)
16 to 19 are cross-sectional views illustrating the process of manufacturing the semiconductor device according to the third embodiment, and FIG. 20 is a cross-sectional view after completion. In the present embodiment, a mixed crystal layer 42 of Si and Ge (germanium) is grown on the main surface of the single crystal silicon substrate 40 in the first embodiment by an epitaxial method. The mixed crystal layer 42 includes, for example, a 3 μm thick region grown by increasing the Ge composition ratio to 0 to 40% and a 2 μm thick region where the Ge composition ratio is 40% (constant). Configured. The mixed crystal layer 42 is also referred to as a strain relaxation layer.

  Following the formation of the strain relaxation layer 42, a silicon strain layer 43 having a thickness of 10 nm was grown. The lattice strain amount in the silicon strained layer 43 was confirmed to be about 1.6% as a deviation from the single crystal silicon lattice spacing by Raman spectroscopy. Prior to the epitaxial growth, a silicon nitride film (not shown) was deposited on the back surface of the single crystal silicon substrate 40 so that the warpage of the substrate after the epitaxial growth was compensated and became flat.

From this state, similarly to the first embodiment, formation of a thin buried gate insulating film 10 having a laminated structure and deposition of an amorphous silicon film 12a having a thickness of 20 nm on the surface thereof by chemical vapor reaction of Si ₂ H ₆ are performed. Then, hydrogen ion implantation based on the surface flattening and the known ultra-thin SOI substrate manufacturing method was performed. As a result of this ion implantation, a crystal defect layer 41 was formed at a depth of about 40 nm from the surface of the silicon strained layer 43. Further, as in the first embodiment, a support substrate 1 on which a silicon oxide film 2a was formed was separately prepared (FIG. 16).

  Next, after the step shown in FIG. 16, as in the first embodiment, the two substrates are bonded together, and in the strain relaxation layer 42 above the silicon strain layer 43 using the peeling at the crystal defect layer 41. It was made to peel. The heat treatment for enhancing the adhesive strength was performed at 900 ° C. for the purpose of minimizing strain relaxation in the silicon strain layer 43. From this state, the peeled surface is mirror-polished by a surface polishing method that does not include abrasive grains, a thin strain relaxation layer 42, a 10 nm thick single crystal silicon strained layer 43, a thin buried gate insulating film 10, a buried silicon film 12, a thick buried layer. An SOI substrate in which the oxide film 2 was sequentially formed on the support substrate 1 was manufactured. Note that the silicon nitride film formed on the back surface of the single crystal silicon substrate 40 before bonding was removed after the heat treatment for enhancing the adhesive strength (FIG. 17).

  Next, after the step shown in FIG. 17, the element isolation with a depth reaching the buried oxide film 2 that defines the active region in the SOI substrate having the multilayered structure having the silicon strained layer 43 in accordance with the manufacturing method of the first embodiment. After forming the groove 11 and forming the groove 13 by selectively removing the single crystal silicon strained layer 43 in the desired region, the gate insulating film 4 was formed. In the state before forming the gate insulating film 4, the film thickness of the strain relaxation layer 42 was completely removed by surface cleaning or the like, and only the 10 nm thick single crystal silicon strained layer 43 remained (FIG. 18).

  Next, after the step shown in FIG. 18, the gate electrode 5 is formed. In the present embodiment, a polycrystalline SiGe film in which Ge is added at a thickness of 20 nm and 30% of Ge is added and B is also added at a high concentration. A polycrystalline silicon film having a thickness of 40 nm was deposited by a CVD method and processed so as to have a gate length of 30 nm together with the silicon nitride film 14 (gate protective film) having a thickness of 40 nm. The reason for using a polycrystalline SiGe film doped with a p-type impurity at a high concentration as the gate electrode material immediately above the gate insulating film 4 is that the threshold voltage in the n-channel fully depleted SOI IIFET is determined by the work function of the gate electrode material. This is because it can be set near 0V.

  Subsequently, after the n-type source diffusion layer 6 and the n-type drain diffusion layer 7 are formed by ion implantation of As using the gate electrode 5 and the silicon nitride film 14 and an activation heat treatment thereof, the above-described embodiment 1, an n-type diffusion layer 15, a silicon oxide film 17, a sidewall spacer 17c, an n-type stacked source diffusion layer 26, and an n-type stacked drain diffusion layer 27 were formed (FIG. 19). The n-type stacked source diffusion layer 26 and the n-type stacked drain diffusion layer 27 are formed by depositing, for example, an amorphous or polycrystalline silicon film doped with P (phosphorus) at a high concentration by the CVD method in addition to the epitaxial growth method. May be.

  Next, after the step shown in FIG. 19, the silicon nitride film 14 is selectively removed according to the manufacturing method of the first embodiment, and the gate electrode 5, the n-type diffusion layer 15, and the n-type stacked source diffusion layer 26. And the silicidation process of the n-type stacked drain diffusion layer 27 was performed. Subsequently, after the interlayer insulating film 21 was deposited, the connection hole 22 was formed, the ground potential electrode 30, the output terminal electrode 31, and the input terminal electrode 34 were formed, a semiconductor device was manufactured through a wiring formation process (FIG. 20).

FIG. 21 is a circuit diagram for explaining the circuit configuration of the semiconductor device of the present embodiment, and FIGS. 22 and 23 are schematic plan views of the semiconductor device. In the comparison between FIG. 21 and FIG. 20, T ₁₁ is an n-channel fully depleted SOI IIFET formed in the single crystal silicon strained layer 43 in FIG. 20, and T ₂₁ and T ₂₂ are the n-type source diffusion layer 7, n This is an auxiliary transistor using the type drain diffusion layer 8 as a gate electrode and the respective n type diffusion layer 15 as a drain. The source corresponds to the buried silicon film 12 via the buried gate insulating film 10 immediately below the substrate terminal of T ₁₁ . C ₁ is a capacitance component due to the buried gate insulating film 10. The input terminal electrode 34 in FIG. 20 is connected to the gate electrode 5 by wirings 45 and 46.

  The circuit shown in FIG. 21 is generally called a transfer gate, and is a logic circuit that controls transfer of a signal from either the source or drain to the drain or source side in accordance with a control signal to the IN terminal. That is, the circuit of FIG. 21 is required to operate in both directions between the electrodes (30, 31), and the roles of the source and drain are required to be switched according to the transfer signal. It is also required that the input / output height of the transfer signal is not attenuated. For this reason, in the conventional transfer gate, an n-type IGFET and a p-type IGFET are connected in parallel, and signals that are opposite to each other are input to the respective IN terminals. That is, the transfer gate is composed of two IGFETs.

  In the semiconductor device according to the present embodiment, the threshold voltage is set to approximately 0 V by the 30 nm-long gate electrode 5 made of the polycrystalline SiGe film to which B is added at a high concentration, and the driving current is driven by the auxiliary transistor. Due to the increase and the leakage current reduction effect, it was possible to confirm a high-speed operation almost twice as high as that of the conventional complementary IGFET configuration without causing a decrease in output despite being constituted by one transistor.

The semiconductor device according to this embodiment, since the unit logic circuit is composed one of the main transistor T ₁₁ and the two connection holes, also a significant reduction in the area occupied compared with the case based on the conventional auxiliary transistor Also realized.

The first reason for achieving the high-speed operation of the semiconductor device according to the present embodiment is the substrate potential control based on the auxiliary transistor, and the second reason is that the main transistor T ₁₁ is approximately in the direction parallel to the (100) plane. This is based on the fact that the single crystal silicon thin film 3 having a lattice strain of 1.6% is formed. The introduction of crystal lattice strain can solve the degeneration of the conduction band, valence band and conduction band of Si single crystal, light hole effective mass component becomes the main subject of conduction, and the scattering of energy valleys can be suppressed. It seems that both of the electrons and holes appear as improved mobility due to the above effects.

Although the amount of lattice strain introduced in the Si single crystal constituting the main transistor T ₁₁ is controlled by the Ge content in the mixed crystal layer 42 made of SiGe, in the manufacture of the semiconductor device according to the present embodiment, the mixed crystal by changing the Ge content of layer 42, the single-crystal silicon thin film 3 is lattice strain amount separately prepared by using a substrate which was controlled to 0.01% or less of 2% or more, of the T ₁₁ with increasing lattice strain amount The current driving ability tends to increase from about 0.01% of the lattice strain, but the lattice strain is about 2%, and the tendency is completely saturated. On the other hand, the amount of crystal defects generated in the single crystal silicon thin film 3 also increases rapidly as the lattice strain increases.

  From the above results, it is desirable that the lattice strain amount of the single crystal silicon thin film 3 is 0.01% or more and 2% or less. In the present embodiment, in the structure for introducing lattice strain into the single crystal silicon thin film 3, the stress mismatch between the buried oxide film 2 and the support substrate 1 is relaxed, and the single crystal silicon thin film 3 into which lattice strain is introduced is introduced. In order to prevent the generation of crystal defects, a prototype of a structure in which Ge is mixed in the embedded silicon film 12 was examined, and it was confirmed that a completely crystalline single crystal silicon thin film 3 in which no crystal defects were observed was obtained. It was confirmed that the SiGe mixed crystal layer was effective for the film 12.

  Here, in the region where the buried silicon film 12 is in contact with the buried gate insulating film 10, a stacked structure in which a Si layer is used may be adopted, and a method of ensuring the stability of the interface with the buried gate insulating film 10 may be used. In this embodiment, an example in which two auxiliary transistors are formed is shown. However, when the application circuit is not a transfer gate, one auxiliary transistor may be used. Further reduction is possible.

(Embodiment 4)
FIG. 24 is a completed sectional view of the semiconductor device according to the fourth embodiment of the present invention. In the present embodiment, only the p-type IGFET (Tp) of the first embodiment is manufactured. That is, the introduction of impurities into the source and drain diffusion layers depended on the high concentration B. The main difference from the first embodiment is that the direction of the source and drain diffusion layers of the p-type IGFET formed in the single crystal silicon thin film 3 is not the normal <110> direction but the <100> direction. And that the impurity region 44 for adjusting the threshold voltage is introduced into the buried silicon layer 12 via the buried gate insulating film 10 below the channel region of the p-type IGFET (Tp) as the main transistor. .

Impurities were introduced through the single crystal silicon thin film 3 and the buried gate insulating film 10 by ion implantation. In order to increase the drive current and leakage current by changing the threshold voltage in the p-type IGFET (Tp) in the positive direction, the implantation type is changed to B or In (indium), and the threshold voltage is changed to the negative direction. In order to reduce the drive current and leakage current, As, P or Sb (antimony) may be used. The implantation amount may be 1 × 10 ¹⁴ / cm ² or less, so that the implantation damage in the single crystal silicon thin film 3 and the buried gate insulating film 10 in the penetrating region can be suppressed to an extent that can be effectively ignored.

  The implantation region was controlled by determining an implantation blocking mask before forming the gate insulating film 4. This is because the entire surface is implanted without using an implantation blocking mask at this stage, and after forming the gate electrode, implantation impurities of the opposite conductivity type using the gate electrode 5 as an implantation blocking mask are compensated for implanted impurities other than the desired region. Alternatively, the impurity region 44 may be left in the buried silicon film 12 in a self-aligning relationship with the gate electrode 5. The threshold voltage is determined by the amount of impurities in the single crystal silicon thin film 3, the work function of the gate electrode 5, the amount of impurities in the impurity region 44, and the thicknesses of the gate insulating film 4 and the buried gate insulating film 10. .

  In the IGFET according to the present embodiment, the single crystal silicon thin film 3 is as extremely thin as 10 nm, and the amount of impurities inside is in a completely depleted state with negligible concentration, and the gate insulating film 4 and the embedded gate insulating film 10 Since each film thickness is as thin as about 2 nm in terms of a silicon oxide film, it is almost determined by the work function of the gate electrode 5, the total amount of impurities in the impurity region 44, and the distribution state thereof.

  In the IGFET according to the present embodiment, by using a metal silicide film as the material of the gate electrode 5, the threshold voltage is set to be substantially 0 V, and for each constituent IGFET on the same semiconductor substrate according to a desired circuit configuration. Impurity regions 44 into which a desired amount of a desired impurity was selectively introduced were formed. In the present embodiment, the p-type diffusion layer 16 connected to the gate electrode 5 and connected to the buried silicon film 12 is provided in one place from the viewpoint of reducing the occupied area. In the p-type IGFET (Tp) manufactured based on this embodiment, although it is a fully depleted SOIIGFET, an adjacent IGFET having a threshold voltage made of the same gate material according to a desired circuit configuration In the meantime, the gate input potential can be effectively set by the function of the auxiliary transistor having the p-type drain diffusion layer 9 as the gate and the p-type diffusion layer 16 as the drain. It was confirmed that this is the first IGFET that can act on substrate potential control to achieve a large drive current and a low leakage current.

  Further, in the p-type IGFET based on the present embodiment, the effect of improving the hole mobility is also exhibited due to the effect that the source / drain directions are arranged in the <100> direction, which is based on the first embodiment. Compared with the p-type IGFET in which the source / drain directions are arranged in the <110> direction, an improvement in driving current of about 10% was achieved without fluctuations in threshold voltage and increase in leakage current.

  The IGFET according to the present embodiment is based on a fully depleted operation mechanism, and does not require introduction of impurities for punch-through suppression into the single crystal silicon thin film 3 constituting the channel region. For this reason, the problem increases in the leakage current due to the direct tunneling current between the drain and the substrate due to the increase in the amount of punch-through suppression impurities, which is a problem in the ultrafine IGFET manufactured on the normal substrate, and increases with the increase in the amount of introduced impurities. Basic fatal defects such as an increase in variation in threshold voltage due to an increase in the relative fluctuation amount of the introduced impurities are eliminated. Therefore, a dramatic improvement in the yield of good products can be achieved. In order to maintain the above fully depleted operation mechanism, it is necessary to manufacture an ultrafine IGFET in the single crystal silicon thin film 3 that is sufficiently thin compared to the gate length and close to an intrinsic semiconductor in the SOI structure. When the power supply voltage is 1 V or less, the film thickness of the single crystal silicon thin film 3 is preferably 1/3 or less of the gate length, and preferably 1/5 or less for complete depletion.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is a technique suitable for application to a semiconductor device having a highly integrated, high-performance fully-depleted SOI IIFET.

1 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention. It is principal part sectional drawing of the semiconductor substrate which shows the structure of the conventional SOIIGFET. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor device which is one embodiment of this invention. FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 5; FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 7; FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 8; FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 9; It is principal part sectional drawing of the semiconductor substrate which shows the semiconductor device which is one embodiment of this invention. It is a schematic plan view of the semiconductor substrate which shows the semiconductor device which is one embodiment of this invention. It is a schematic plan view of the semiconductor substrate which shows the semiconductor device which is one embodiment of this invention. It is a wave form diagram which shows the operation mechanism of the semiconductor device which is one embodiment of this invention compared with a prior art. It is a circuit diagram of the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. FIG. 17 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 17; FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 18; It is principal part sectional drawing of the semiconductor substrate which shows the semiconductor device which is other embodiment of this invention. It is a circuit diagram of the semiconductor device which is other embodiment of this invention. It is a schematic plan view of the semiconductor substrate which shows the semiconductor device which is other embodiment of this invention. It is a schematic plan view of the semiconductor substrate which shows the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the semiconductor device which is other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Support substrate 2a Silicon oxide film 2 Embedded oxide film 3 Single crystal silicon thin film 4 Gate insulating film 5 Gate electrode 6 n-type source diffusion layer 7 n-type drain diffusion layer 8 p-type source diffusion layer 9 p-type drain diffusion layer 10 embedded gate Insulating film 11 Element isolation trench 12a Amorphous silicon film 12 Embedded silicon film 13 Groove 14 Silicon nitride film 15 N-type diffusion layer 16 P-type diffusion layer 17 Silicon oxide film 17c Side wall spacer 21 Interlayer insulation film 22 Connection hole 26 N-type Stacked source diffusion layer 27 n-type stacked drain diffusion layer 28 p-type stacked source diffusion layer 29 p-type stacked drain diffusion layer 30 Ground potential electrodes 31, 32 Output terminal electrode 33 Power supply terminal electrode 34 Input terminal electrode 35 Connection electrodes 36-39 Wiring 40 Single crystal silicon substrate 41 Crystal defect layer 42 Mixed crystal layer (strain relaxation layer)
43 Silicon strained layer 44 Impurity regions 45 and 46 Wiring 100 Support substrate 101 Embedded oxide film 102 Embedded gate electrode 103 Embedded gate insulating film 104 Gate insulating film 105 Gate electrode 106 Source diffusion layer 107 Drain diffusion layer 108 Element isolation trench 110 Single crystal silicon Film Tn n-type IGFET
Tp p-type IGFET

Claims (19)

A first insulated gate field effect transistor on a semiconductor substrate; and a second insulated gate field effect transistor having the same conductivity type as the first insulated gate field effect transistor;
A gate electrode of the first insulated gate field effect transistor is electrically connected to a drain of the second insulated gate field effect transistor;
A source of the second insulated gate field effect transistor is electrically connected to a substrate terminal of the first insulated gate field effect transistor through a capacitive element;
The drain of the first insulated gate field effect transistor is electrically connected to the gate electrode of the second insulated gate field effect transistor.   2. The semiconductor device according to claim 1, wherein a drain of the second insulated gate field effect transistor is formed by a pn junction.   2. The semiconductor device according to claim 1, wherein a drain of the second insulated gate field effect transistor is formed by a junction of metal or metal silicide and a semiconductor. A supporting substrate; a first insulating film formed on the supporting substrate; a first semiconductor film formed on the first insulating film; a second insulating film formed on the first semiconductor film; A source and a drain of an insulated gate field effect transistor are formed in the second semiconductor film of the semiconductor substrate including the second semiconductor film formed on the second insulating film;
A gate electrode of the insulated gate field effect transistor is formed on the second semiconductor film between the source and drain via a third insulating film, and the gate electrode is connected to the first semiconductor film. A semiconductor device.   5. The semiconductor device according to claim 4, wherein the gate electrode and the first semiconductor film are connected through a pn junction.   5. The semiconductor device according to claim 4, wherein the connection between the gate electrode and the first semiconductor film is made through a junction of a metal or metal silicide and a semiconductor.   5. The semiconductor device according to claim 4, wherein the second semiconductor film is made of single crystal silicon.   5. The semiconductor device according to claim 4, wherein at least one of the first and second semiconductor films has a silicon-germanium mixed crystal or a stacked structure of the silicon-germanium mixed crystal and silicon. .   5. The semiconductor device according to claim 4, wherein a stacked diffusion layer having the same conductivity type as the source and drain is formed on each of the source and drain.   5. The semiconductor device according to claim 4, wherein the gate electrode is made of metal, metal silicide, or a stacked structure thereof.   5. The semiconductor device according to claim 4, wherein the thickness of the second semiconductor film is smaller than the gate length of the gate electrode.   12. The semiconductor device according to claim 11, wherein an impurity for adjusting a threshold voltage is added to the first semiconductor film immediately below the gate electrode.   13. The semiconductor device according to claim 12, wherein the threshold voltage has a plurality of values.   8. The semiconductor device according to claim 7, wherein the second semiconductor film made of single crystal silicon is configured with a (100) plane, and the source and drain of the insulated gate field effect transistor are <100 through the gate electrode. > A semiconductor device characterized by being arranged perpendicularly or parallel to a direction.   8. The semiconductor device according to claim 7, wherein a tensile strain of 0.01% or more and 2% or less is applied to the second semiconductor film made of single crystal silicon in at least one direction in the plane of the film. A featured semiconductor device. First and second insulated gate field effect transistors of the first conductivity type; and third and fourth insulated gate field effect transistors of the second conductivity type opposite to the first conductivity type. ,
The drain and gate electrode of the first insulated gate field effect transistor are connected to the drain and gate electrode of the third insulated gate field effect transistor, respectively.
A gate electrode of the first insulated gate field effect transistor is connected to a drain of the second insulated gate field effect transistor;
A source of the second insulated gate field effect transistor is connected to a substrate terminal of the first insulated gate field effect transistor through a capacitive element;
A drain of the first insulated gate field effect transistor is connected to a gate electrode of the second insulated gate field effect transistor;
A gate electrode of the third insulated gate field effect transistor is connected to a drain of the fourth insulated gate field effect transistor;
A source of the fourth insulated gate field effect transistor is connected to a substrate terminal of the third insulated gate field effect transistor through a capacitive element;
The drain of the third insulated gate field effect transistor is connected to the gate electrode of the fourth insulated gate field effect transistor.   17. The semiconductor device according to claim 16, wherein the third and fourth insulated gate field effect transistors are arranged in the same semiconductor film and insulated from other semiconductor devices configured in the semiconductor film. A semiconductor device characterized by the above.   17. The semiconductor device according to claim 16, wherein each of the second and fourth insulated gate field effect transistors is replaced with a resistance element. 5. The semiconductor device according to claim 4, further comprising: a semiconductor device in which a plurality of transistors arranged adjacent to each other on the same supporting substrate as the semiconductor device are connected in series, and the substrate immediately below the serially connected semiconductor device. A semiconductor device, wherein the terminal is connected to a ground potential or a power supply potential through a capacitor.

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