JP2005122329A - Software real-time analysis method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To additionally insert a debug-dedicated instruction that generates a debug event without causing a change in ROM size, a decrease in optimality, and a performance deterioration caused by inserting the debug-dedicated instruction into software to be analyzed. The software development efficiency is improved and improved by providing a software real-time analysis method that can be arbitrarily deleted or deleted.
A processor for executing parallel instructions including the debug-dedicated instructions, program conversion means for preliminarily securing a ROM area for inserting the debug-dedicated instructions in the analysis target software, and the ROM Analyzing the program by means of program conversion means and a debugger capable of executing instruction replacement with the debug-dedicated instruction for a region, and a debug device capable of arbitrarily controlling the timing of occurrence of a debug event by an argument of the debug-dedicated instruction Provided is a software real-time analysis method capable of arbitrarily specifying a debug event without affecting the ROM size, optimality, and performance of the target software.
[Selection] Figure 1

Description

  The present invention relates to an analysis method for use in real-time analysis of the operation of software running on a processor.

  As a method for real-time analysis of software operations, debug events can be set for any point of interest existing in the analysis target software, and the logical operation of the software can be determined by referring to the history of occurrence of the debug events. A method of performing processing performance analysis is widely used.

In this real-time analysis method using a debug event, a dedicated instruction or a group of information output instructions for a specific resource is inserted at a corresponding position, and a means for detecting the execution of the instruction inserted for the debug event and its history are collected. Provision of information necessary for real-time analysis is realized by the means to perform (for example, Patent Document 1).
JP-A-6-89200

  However, in the real-time analysis method using the conventional debug event, every time the specified position of the debug event is changed or deleted, the compiling or assembling work is required and the software is reconstructed. Even if there is no change at the source program level, the ROM size and the program counter allocation will change at the machine language level, resulting in a loss of the essence of the analysis work that changes the analysis target for the analysis work. There was a problem.

  In addition, there is a problem in that the optimality of the software part to be analyzed is lowered due to a change in the structure of the instruction group existing before and after the insertion place by inserting the instruction for debugging. It was.

In addition, when an information output instruction group for a specific resource is inserted without using a dedicated instruction, there is a serious problem that the performance is deteriorated in proportion to the set number of debug events.
In the present invention, in order to solve the above-described problems in the conventional technology, additional setting or deletion of debug events is arbitrarily performed without changing the ROM size of the analysis target software, decreasing the optimality, or degrading the performance. It is an object of the present invention to provide a real-time analysis method capable of performing the above.

  In order to achieve this object, the software real-time analysis method according to claim 1 of the present invention inserts a dedicated debug instruction for generating a debug event in the software to be analyzed, and refers to the execution history of the software. A real-time analysis method that executes a parallel instruction execution having a notification function of the debug instruction and instruction execution state, and controls the timing of occurrence of a debug event based on the execution notification information of the debug instruction and debugs A debug device that outputs debug information necessary for analysis when an event occurs, and a ROM area for inserting the debug-dedicated instruction at a location where the instruction parallelism is free, and the ROM area position information is read as ROM information Program conversion means to output as and debug event instructed A ROM size change due to the insertion of the debug-dedicated instruction, a decrease in the optimality, and performance are configured from a debugger that performs instruction replacement processing to the debug-dedicated instruction for the ROM area based on the setting information and the ROM information. It is characterized by no deterioration.

  The software real-time analysis method according to claim 2 is the software real-time analysis method according to claim 1, wherein the debug-dedicated instruction has invalidation information, event ID information, and event detection timing designation information as arguments. When invalidation is not specified in the invalidation information, the contents of the argument and the occurrence of execution are notified to the debug device.

  The software real-time analysis method according to claim 3 is the software real-time analysis method according to claim 1 or 2, wherein the debug-dedicated instruction does not affect all processor resources. Execution is completed in a machine cycle.

  The software real-time analysis method according to claim 4 is the software real-time analysis method according to claim 1, 2 or 3, wherein the debug device receives the event ID information and the event detection timing designation information. At the same time as storing, debug information is generated and output based on time information independently generated from the information.

  The software real-time analysis method according to claim 5 is the software real-time analysis method according to claim 1, claim 2, claim 3, or claim 4, wherein the debug device notifies the instruction execution completion from the processor. FIFO type buffer that stores time information at any time whenever it is received, and corresponds to any instruction executed in the past based on the debug event detection timing designation information notified at the time of execution of the debug dedicated instruction The time information to be extracted is extracted from the FIFO type buffer, and at the same time, the occurrence of a debug event is detected, thereby making it possible to set and detect the occurrence of a debug event for an instruction executed in the past rather than the debug dedicated instruction. And

  The software real-time analysis method according to claim 6 is the software real-time analysis method according to claim 1, claim 2, claim 3, claim 4 or claim 5, wherein the debug device A first counter that operates every time an instruction execution completion notification is received, and instruction execution after an arbitrary specified number of times from execution of the debug-dedicated instruction based on the debug event detection timing information notified when the debug-dedicated instruction is executed Debug event occurrence detection is performed when a debug event is performed, and a debug event can be set and detected for any subsequent instruction to be executed in the future rather than the debug dedicated instruction.

  The software real-time analysis method according to claim 7 is the software real-time analysis method according to claim 5 or 6, wherein when all branch instructions including conditional branches are executed on the processor, the FIFO is executed. By disabling the contents of the type buffer and the first counter so that an erroneous debug event occurrence detection due to an unintended branch operation caused by a software failure or the like is not performed, the software is not affected by a software failure and under any circumstances However, it is characterized by enabling accurate detection of debug events.

  The software real-time analysis method according to claim 8 is the software real-time analysis method according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, or claim 7, The debug device includes a second counter and an event ID comparison mechanism that are operated every time the debug dedicated instruction is notified of execution, and a debug dedicated instruction having an arbitrary event ID specified by event detection timing information is arbitrarily specified It is characterized in that it is possible to set and detect the occurrence of a debug event for the case where it is continuously executed a number of times.

  The software real-time analysis method according to claim 9 is the software real-time analysis method according to claim 8, wherein the debug device includes the FIFO buffer, the first counter, and the second counter. A situation in which an interrupt or an exception is generated asynchronously by switching control of these banks even when an interrupt or exception occurs on the processor and when the interrupt or exception is returned from the processing routine. The feature is that real-time analysis can be continued even under.

  The software real-time analysis method according to claim 10 is the method according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, claim 8, or claim 9. In the software real-time analysis method, when the interrupt or exception occurs in the processor, the storage device indicated by a pointer capable of arbitrarily designating the contents of the FIFO buffer, the first counter, and the second counter The FIFO buffer, the first counter, and the second buffer saved from the address area of the storage device indicated by the pointer when returning from the interrupt or exception processing routine in the previous processor. A stack control mechanism that restores the contents of the counter And by, characterized in that to allow continued real-time analysis even in a situation where asynchronously interrupt or exception occurs.

  The real-time analysis method for software according to claim 11 is the method of claim 1 or claim 2 or claim 3 or claim 4 or claim 5 or claim 6 or claim 7 or claim 8 or claim 9 or claim. 10. The software real-time analysis method according to 10, wherein the basic block unit is between the first instruction of software or an arbitrary branch instruction and the next branch instruction, so that all parts of the software to be analyzed can be analyzed. The real-time analysis can always be performed.

  The software real-time analysis method according to claim 12 is the method of claim 1 or claim 2 or claim 3 or claim 4 or claim 5 or claim 6 or claim 7 or claim 8 or claim 9 or claim. 10. The software analysis method according to claim 10 or claim 11, wherein the program conversion means analyzes the contents of the software to be analyzed last time when converting the software, and includes the first instruction, last instruction of the function and subroutine, and the description of the software. The debug-dedicated instruction is automatically inserted into a place where the insertion of the debug-dedicated instruction is explicitly instructed in step (b).

  The software real-time analysis method according to claim 13 is the method of claim 1 or claim 2 or claim 3 or claim 4 or claim 5 or claim 6 or claim 7 or claim 8 or claim 9 or claim. 13. The software real-time analysis method according to claim 10, wherein the program conversion means outputs ROM information including insertion position information of the debug dedicated instruction and the NOP instruction to the debugger. Features.

  The software real-time analysis method according to claim 14 is the method according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, claim 8, claim 9, or claim 10. 14. The software real-time analysis method according to claim 10 or claim 11 or claim 12 or claim 13, wherein the ROM information is read, the event ID information and the event information based on the setting information of the instructed debug event and the ROM information, Generates event detection timing specification information and performs instruction replacement processing with dedicated instructions for debugging on the ROM area, enabling real-time analysis that does not require reconfiguration of analysis target software by changing debug event settings It is characterized by that.

  As described above, additional insertion of the previous debugging instruction that generates a debugging event without changing the ROM size, reducing the optimality, and degrading the performance caused by inserting the debugging instruction into the software to be analyzed It is possible to provide a real-time analysis method that can be arbitrarily deleted or deleted.

  As described above, the debug-dedicated instruction that generates a debug event without causing a change in ROM size, a decrease in optimality, and a performance deterioration caused by inserting the debug-dedicated instruction into software to be analyzed The software development efficiency can be improved and improved by providing a software real-time analysis method capable of arbitrarily inserting and deleting the software.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1, 2, 3, 4, 5 and 6.
FIG. 1 is a block diagram for explaining the configuration of the real-time analysis method of the present invention, FIG. 2 is a diagram showing an example of the specification of a debug dedicated instruction provided in the processor, and FIG. 3 is a program for securing a ROM area for inserting the debug dedicated instruction FIG. 4 is a diagram illustrating the operation of the changing means, FIG. 4 is a diagram illustrating an operation when a debug event is specified for a subsequent instruction of the debug dedicated instruction, and FIG. 5 is a debug event for an instruction existing before the debug dedicated instruction. FIG. 6 is a diagram illustrating an operation when designation is performed, and FIG. 6 is a diagram illustrating an operation when a branch occurs due to an interrupt or exception that occurs asynchronously.

  In FIG. 1, reference numeral 100 denotes a processor (hereinafter referred to as a processor) that executes parallel instructions, 200 denotes a debugging device, 300 denotes program conversion means such as a compiler and assembler, 400 denotes a debugger, and 500 denotes a storage device.

  The processor 100 detects the execution of the debug-dedicated instruction by the instruction fetch control unit 106 that reads an instruction from the storage device 500, the execution instruction analysis unit 101 that decodes the instruction fetched by the instruction fetch control unit 106, and the execution instruction decoding unit 101. A debug dedicated instruction execution notifying unit 102 for notifying the debugging device 200, an interrupt occurrence notifying unit 103 for detecting that an interrupt or exception has occurred and notifying the debugging device 200, and an execution instruction decoding unit 101 during an interrupt or exception processing program. Consists of a return instruction execution notifying unit 104 that detects that execution of a return instruction is detected and notifies the debug device 200, and an instruction execution completion notification unit 105 that detects execution completion and notifies the debug device 200 for each instruction execution unit. Architecture capable of parallel instruction execution Is a processor that Tsu.

  The debugging device 200 decodes the event ID information and the event detection timing designation information notified from the debug dedicated instruction execution notifying unit 102, and performs a FIFO type buffer 204, an instruction execution count counter 205, and a debug dedicated instruction execution count counter 206 described later. The event information analysis unit 201 that performs control through the bank control unit 207 and the time information independent of the operation of the processor 100 are generated and the time information is notified to the FIFO buffer 204 and the event detection unit 209 described later. A time information generation unit 202; an interrupt detection control unit 203 that receives a notification from the interrupt generation notification unit 103 and the return instruction execution notification unit 104; detects an interrupt or exception occurrence and a return from interrupt or exception processing; and a time information generation Generated by the unit 202 The FIFO buffer 204 having a function of sequentially storing time information and simultaneously outputting information corresponding to a debug event to an event detection unit 209 described later, and the number of instruction executions in response to a notification from the instruction execution completion notification unit 105 An instruction execution counter 205 for counting, a debug dedicated instruction execution counter 206 for counting the number of executions of a debug dedicated instruction having the same ID based on the result decoded by the event information analysis unit 201, a FIFO buffer 204, The instruction execution number counter 205 and the debug dedicated instruction execution number counter 206 are handled as one bank, and the interrupt detection and the return from the interrupt processing detected by the interrupt detection control unit 203 in the debug device 200 in which a plurality of banks are mounted. Bank switching control starting from The bank control unit 207 and a pointer register that can be set to an arbitrary value are provided. When an interrupt is detected by the interrupt detection control unit 203, the FIFO type is used for the address area on the storage device 500 indicated by the pointer register. The contents of the buffer 204, the instruction execution count counter 205, and the debug dedicated instruction execution count counter 206 are written out (push operation), and at the same time, the contents of the pointer register are automatically increased, and from the interrupt processing detected by the interrupt detection control unit 203 In response to the return, the contents of the FIFO buffer 204, instruction execution counter 205, and debug dedicated instruction execution counter 206 saved in the storage device 500 based on the value indicated by the pointer register are read and returned (pop operation). Stack control unit 208 and event information analysis unit 201 Event detection unit 209 that detects an event based on the result of decoding and extracts the corresponding event ID information and time information, and debug information for notifying debugger 400 of information on the debug event detected by event detection unit 209 And a debug information output unit 210 for converting and outputting the data.

  The program conversion means 300 includes a source program 301 to be analyzed, and a machine with optimization that reads the source program 301 and performs conversion to machine language while performing optimization so that the performance and code size are the best. A word block 302 and a basic block extractor 303 for extracting a section from the first instruction of the program or a branch instruction to the next branch instruction as one basic block for inserting a debug-dedicated instruction from the result of the machine language converter 302. As an inspection result of the instruction parallelism checking means 304 and the instruction parallelism checking means 304, the contents of each basic block extracted by the basic block extraction means 303 are read to check whether there is a vacancy in the instruction parallelism. If there is no vacancy in the instruction parallelism, only one or more basic blocks are included. If there is a vacancy in the instruction parallelism as a result of the inspection by the machine language reconversion means 305 that performs the optimization again so that the instruction parallelism exists in the instruction parallelism, and the instruction parallelism inspection means 304, the basic block extraction means 303 Instruction insertion means for inserting a debug-dedicated instruction or NOP instruction into a place where there is a vacancy in the instruction parallelism for the extracted basic block, otherwise, for the basic block obtained from the machine language reconversion means 305 306, an execution object 307 that is a result of processing of the instruction insertion unit 306 on the entire source program 301, and a ROM including position information of a debug-dedicated instruction or NOP instruction inserted by the instruction insertion unit 306 Information 308.

  The debugger 400 includes a debug information receiving unit 401 that receives debug information output from the debug information output unit 210 in the debug device 200, and a debug information display that decodes and displays the debug information received by the debug information receiving unit 401. Instruction replacement processing of the dedicated debug instruction and the NOP instruction on the storage device 500 based on the debug dedicated instruction and the insertion position information of the NOP instruction obtained from the instruction insertion information analyzing unit 404 described later in accordance with the instruction from the unit 402 and the operation unit 405 A debug event setting change control unit 403 that performs the above, an instruction insertion information analysis unit 404 that reads ROM information 308 obtained by the program conversion apparatus 300 and obtains insertion position information of a dedicated debug instruction and a NOP instruction, and a debugger 400. Acting as a user interface with workers Consisting of work unit 405.

Next, the operation of the present invention will be described.
In FIG. 2, the debug dedicated instruction code 600 is a machine language mnemonic, and there are event ID information 601 and event detection timing designation information 602 as arguments. Event detection timing designation information 602 includes direction designation information 603 indicating whether the event setting target instruction is in front of or behind the debug dedicated instruction 600, and an offset from the debug dedicated instruction 600 indicating the position of the event setting target instruction. Offset instruction number designation information 604 that is the number of instructions, debug dedicated instruction execution count designation information 605 that is a debug event generation condition, and debug that designates event ID information 601 and event detection timing designation information 602 to be treated as invalid at the time of execution It consists of dedicated instruction invalidation designation information 606.

  In FIG. 3, a machine language conversion result example 611 is a result obtained by performing optimization by converting the source program example 610 by the machine language conversion unit 302. A basic block example extracted by applying the machine language conversion result example 611 to the basic block extracting unit 303 becomes a basic block example 612. When the basic block example 612 is inspected by the instruction parallelism checking unit 304, the basic parallel block example 612 has no space in the instruction parallelism. Re-convert so that The result examples are a machine language reconversion result example 613 and a reconverted basic block example 614. Since the example 615 where the debug dedicated instruction can be inserted exists in the basic block example 614 after the reconversion, the instruction inserting unit 306 inserts the debug dedicated instruction or the NOP instruction into this place, and the execution object 307 is generated. This is stored in the storage device 500.

  The processor 100 fetches an instruction to be executed from the storage device 500 through the instruction fetch control unit 107, and performs an operation while determining an instruction in the execution instruction analysis unit 101. When the instruction fetched from the instruction fetch control unit 107 by the execution instruction analysis unit 101 indicates the debug dedicated instruction code 600, if the content of the debug dedicated instruction invalidation designation information 606 is false, the debug dedicated instruction execution notification unit 102 Through the debug device 200, the event ID information 601 and the event detection timing designation information 602 as arguments are notified to the debug device 200, and the instruction fetched from the instruction fetch control unit 107 returns from interrupt or exception processing. If an instruction is indicated, the debug apparatus 200 is notified through the return instruction execution notification unit 104.

  In the example of the instruction shown in FIG. 4, the event ID information is 0x55, and an event is set for an instruction (Inst C0, Inst C1, Inst C2) that is executed two times after the debug-dedicated instruction.

  When the instruction example shown in FIG. 4 is executed, 0x2 which is an offset value is set in the instruction execution number counter 205 in response to execution of the debug dedicated instruction, and thereafter the counter value decreases by 0x1 every time the instruction is executed. I will do it. Then, the occurrence of a debug event is detected when the value of the instruction execution count counter 205 becomes 0x0, that is, when an instruction two steps after the debug-dedicated instruction is executed. As described above, when the direction designation information 603 notified when the debug dedicated instruction is executed indicates the rear side of the debug dedicated instruction, the contents of the offset instruction count designation information 604 are set in the instruction execution count counter 205 and at the same time the counter operation. Is activated. By detecting a debug event when the operation of the instruction execution counter 205 is valid and its value reaches 0x0, it is possible to set an event and detect a debug event for an instruction executed after a debug-dedicated instruction. It becomes.

  In the example of the instruction in FIG. 5, event ID information is 0xAA, and an event is set for an instruction (Inst B0, Inst B1, Inst B2) that is executed two times before the debug-dedicated instruction. Here, the FIFO type buffer 204 always stores time information created by the time information generating unit 202 every time an instruction is executed.

  When the instruction example shown in FIG. 5 is executed, the event information analysis unit 201 exists in the FIFO buffer −2 based on the direction designation information 603 and the offset instruction number designation information 604 when the execution of the debug-dedicated instruction is received. The time information corresponding to the instruction executed two times before the debug dedicated instruction is selected and extracted as the time information of the debug event.

  That is, the state when the instruction two before the debug-dedicated instruction is executed is detected as the debug event content when the debug-dedicated instruction is executed. As described above, when the direction designation information 603 notified when the debug dedicated instruction is executed indicates the front side of the debug dedicated instruction, the time information is extracted from the FIFO buffer 204 based on the contents of the offset instruction number designation information 604. Thus, it is possible to set an event and detect a debug event for an instruction executed before a debug-dedicated instruction.

  As an assumption condition of FIG. 6, the bank control unit 207 including the FIFO buffer 204, the instruction execution count counter 205, and the debug dedicated instruction execution count counter 206 as one bank, and these banks are filled together. Assume that there is a debugging device 200 including a stack control unit 208 for saving / returning the contents of a bank to / from the storage device 500.

  FIG. 6 shows that an instruction is executed from the head instruction 620 in a certain basic block in the program, an interrupt is generated for the instruction 621 in the basic block, and branches to the interrupt processing head instruction 623. Multiple exceptions occur at the instruction 624 and branch back to the exception processing head instruction 626. After returning to the instruction 624 in the interrupt process in which an exception occurs at the return instruction 627 from exception processing, This is a case where execution returns to the basic block final instruction 622 after returning to the instruction 621 where the interrupt occurred.

  First, in the first interrupt, the bank control unit 207 switches the bank to be used from bank 0 to bank 1. Then, when the next exception occurs, the bank control unit 207 switches the bank to be used to bank 0 at the same time that the stack control unit 208 saves the contents of bank 0 to the storage device 500 in order to prevent destruction of the contents of bank 0. Next, at the time of return from exception processing, the stack control unit 208 restores the contents of the bank 0 saved in the storage device 500, and at the same time, the bank control unit 207 returns the used bank to the bank 1. Then, when returning from the last interrupt processing, the bank control unit 207 returns the bank to be used to bank 0, so that the FIFO buffer 204, the instruction execution counter 205, Since the contents of the debug dedicated instruction execution counter 206 are prevented from being destroyed, it is possible to continue to maintain the debug event detectable state even in a situation where a branch due to an interrupt or exception that occurs asynchronously occurs.

  Note that even if only one of the bank control unit 207 and the stack control unit 208 is present, it is possible to obtain the same effect as the example of FIG. 6, such as actual hardware cost and processing performance. It is possible to select the usage form.

  As described above, the addition of the debug-dedicated instruction that generates a debug event without causing a change in ROM size, a decrease in the optimum degree, and a performance deterioration caused by inserting the debug-dedicated instruction into the analysis target software. Software development efficiency can be improved and improved by providing a software real-time analysis method that can be arbitrarily inserted and deleted.

  Since the software real-time analysis method according to the present invention can arbitrarily set and delete debug events without causing a change in the ROM size of the analysis target software, a decrease in optimality, or performance degradation, It is useful as an analysis method used for real-time analysis of software.

The block diagram explaining the structure of the real-time analysis method of this invention The figure which shows the example of the specification of the debug exclusive instruction which the processor has Program conversion diagram explaining insertion of debug-specific instructions or debug-specific instruction replacement NOP instructions The figure which illustrated the operation when the event setting is done for the succeeding instruction after the debug dedicated instruction The figure which illustrated the operation when the event setting is done for the subsequent instruction before the debug-dedicated instruction Diagram illustrating the operation when a branch occurs due to an unexpected interrupt or exception that occurs asynchronously

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Processor 101 ... Execution instruction decoding part 102 ... Debug exclusive instruction execution notification part 103 ... Interrupt generation notification part 104 ... Return instruction execution notification part 105 ... Instruction execution completion notification part 106 ... Instruction fetch control unit 200 ... Debug device 201 ... Event information analysis unit 202 ... Time information generation unit 203 ... Interrupt detection control unit 204 ... FIFO type buffer 205 ... Instruction execution Number-of-times counter 206 ... Dedicated instruction execution number counter for debugging 207 ... Bank control unit 208 ... Stack control unit 209 ... Event detection unit 210 ... Debug information output unit 300 ... Program conversion means 301 ..Source program 302 ... Machine language conversion means 303 ... Basic block extraction means 304 ... Instruction parallelism checking means 305... Machine language reconversion means 306... Instruction insertion means 307... Execution object 308... ROM information 400 ... debugger 401 ... debug information receiving unit 402. Debug information display unit 403 ... Debug event setting change control unit 404 ... Instruction insertion information analysis unit 405 ... Operation unit 500 ... Storage device 600 ... Debug dedicated instruction code 601 ... Event ID information 602 ... Event detection timing designation information 603 ... Direction designation information 604 ... Offset instruction number designation information 605 ... Debug dedicated instruction execution count designation information 606 ... Debug dedicated instruction invalidation designation information 610 Source program example 611 Machine language conversion result example 612 Basic block example 613 ..Example of machine language re-conversion result 614: Example of basic block after re-conversion 615 ... Example of location where debug dedicated instruction can be inserted 620 ... Basic block head instruction 621 ... Instruction in basic block where interrupt is entered 622... Basic block final instruction 623... Interrupt processing head instruction 624... Interrupt instruction in which exception occurs 626... Exception processing head instruction 627.

Claims (13)

  In a software real-time analysis method for inserting a debug-dedicated instruction for generating a debug event in software to be analyzed and referring to its execution history, the parallel instruction execution having the debug-dedicated instruction and instruction execution state notification function is performed. The processor to be executed, the debug device for controlling the timing of occurrence of the debug event based on the execution notification information of the debug dedicated instruction, and outputting the debug information necessary for the analysis when the debug event occurs, and the portion where the instruction parallelism is free Secures a ROM area for inserting the debug-dedicated instructions, and outputs program location means for outputting the ROM area position information as ROM information; the ROM based on the setting information of the instructed debug event and the ROM information; Replace instruction with dedicated debug instruction for area It consists debugger performs management, the debugging dedicated instruction insertion changes in ROM size by real-time analysis method software, wherein the reduction and performance deterioration of the optimum degree does not occur.   Has invalidation information, event ID information, and event detection timing designation information as arguments, and notifies the debug device of the contents of the argument and execution occurrence when invalidation is not specified in the invalidation information at the time of execution The software real-time analysis method according to claim 1, further comprising the debug-dedicated instruction.   3. The software real-time analysis method according to claim 1, wherein execution of the debug-dedicated instruction is completed in one machine cycle without affecting all processor resources.   The debug device stores the event ID information and the event detection timing designation information, and at the same time generates and outputs debug information based on time information independently generated from the information. The real-time analysis method for software according to claim 1, claim 2, or claim 3.   Each time the debug device receives an instruction execution completion notification from the processor, it includes a FIFO buffer for storing time information at that time, and based on the debug event detection timing designation information notified when the debug dedicated instruction is executed. In addition, by extracting time information corresponding to an arbitrary instruction executed in the past from the FIFO type buffer and simultaneously detecting occurrence of a debug event, a debug event for an instruction executed in the past rather than the debug dedicated instruction is detected. The real-time analysis method for software according to claim 1, wherein the setting and occurrence detection are enabled.   The debug device includes a first counter that operates every time an instruction execution completion notification is received from the processor, and based on the debug event detection timing information notified when the debug dedicated instruction is executed, By detecting the occurrence of a debug event when an instruction is executed an arbitrary number of times after execution, it is possible to set and detect the occurrence of a debug event for any subsequent instruction executed in the future rather than the dedicated instruction for debugging. The software real-time analysis method according to claim 1, claim 2, claim 3, claim 4, or claim 5.   When all branch instructions including conditional branches are executed on the processor, the contents of the FIFO buffer and the first counter are invalidated, and an erroneous debug event due to an unintended branch operation due to a software malfunction or the like 7. The software real-time according to claim 5 or 6, wherein the occurrence of the debug event can be accurately detected under any circumstances by not performing the occurrence detection. analysis method.   The debug device includes a second counter and an event ID comparison mechanism that are operated each time receiving an execution notification of the debug-dedicated instruction, and a debug-dedicated instruction having an arbitrary event ID specified by event detection timing information is arbitrary The debug event can be set and detected when the specified number of times of continuous execution is performed. The claim 1, the claim 2, the claim 3, the claim 4, the claim 5, the claim 6, or the claim 8. The software real-time analysis method according to 7.   The debug device includes a plurality of banks including the FIFO type buffer, the first counter, and the second counter, and generates an interrupt or exception on the processor and an interrupt or exception processing routine. 9. The software real-time analysis method according to claim 8, wherein, at the time of recovery, real-time analysis can be continued even under a situation in which interrupts and exceptions occur asynchronously by switching control of these banks.   When the debug device generates an interrupt or exception in the processor, the contents of the FIFO buffer, the first counter, and the second counter are saved in an address area of a storage device indicated by a pointer that can be arbitrarily designated. At the time of return from the interrupt or exception processing routine in the processor, the contents of the FIFO buffer, the first counter, and the second counter saved from the address area of the storage device indicated by the pointer are restored. 3. The real-time analysis can be continued even in a situation where an interrupt or an exception occurs asynchronously by providing a stack control mechanism, or claim 3 or claim 4, or claim 4 or claim 5 or claim 6 or claim 7 or claim 8 or claim 9 Real-time analysis method of the mounting of the software.   The program conversion means that handles the instruction section from the first instruction of the software or an arbitrary branch instruction to the next branch instruction as one basic block optimizes the analysis target software in a state excluding the insertion of the debug dedicated instruction. As a result of the conversion, by inserting a NOP instruction to secure a ROM area for inserting the debug-dedicated instruction at a place where the instruction parallelism is vacant for each basic block, 6. A state in which a debug event can be arbitrarily set is always maintained for all portions of software to be analyzed. 6. The claim 3, the claim 4, or the claim 5 Or real-time solution of software according to claim 6 or claim 7 or claim 8 or claim 9 or claim 10 Method.   The program conversion means analyzes the content of the software to be analyzed last time, and explicitly inserts the debug-dedicated instruction on the first instruction, last instruction of the function or subroutine and the description of the software. 5. The debug-specific instruction is automatically inserted into a designated location, or claim 2, or claim 3, or claim 4, or claim 5 or claim 6 or claim 7 or The software real-time analysis method according to claim 8, claim 9, claim 10, or claim 11.   4. The program conversion unit outputs ROM information including insertion position information of the debug dedicated instruction and the NOP instruction to the debugger. The software real-time analysis method according to claim 4 or claim 5 or claim 6 or claim 7 or claim 8 or claim 9 or claim 10 or claim 11 or claim 12.

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