JP2005128773A - Microprocessor and compiling method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a transition to a debug program execution mode during execution of a predetermined section in a user program regardless of input of a debug interrupt signal.
A processor according to the present invention detects a CPU core that executes a user program and a debug program, and whether or not the CPU core is executing an interrupt-prohibited section that prohibits interruption of execution in the user program. When a detection interrupt and a debug interrupt signal requesting execution of the debug program are input during execution of a section other than the interrupt-prohibited section, the CPU core causes the CPU core to interrupt the user program. A determination block for causing the CPU core to continuously execute the user program as it is when the debug interrupt signal is input while the CPU core is executing the interrupt prohibited section while the debug program is executed. And comprising.
[Selection] Figure 1

Description

  The present invention relates to a microprocessor and a compiling method for verifying a user program using a debug program.

  A debugging function of a conventional microprocessor or the like (implemented by a DSU (Debug Support Unit) connected to the CPU core, for example) realizes transition of the microprocessor operation mode from the user program execution mode to the debug program execution mode. .

  Specifically, when a specific signal (debug interrupt signal) is input to the DSU from an external device such as a user terminal, the DSU causes the CPU core to interrupt the user program and execute the debug program. Alternatively, the transition to the debug program execution mode is also realized by the CPU core executing a specific instruction during execution of the user program.

  The microprocessor that has executed the debug program by mode transition returns to the user program execution mode by executing a return instruction (for example, a DRET instruction). That is, the microprocessor executes the instruction stored in the program counter (PC) +1 when transitioning to the debug program execution mode. Therefore, when viewed from the user, the user program is interrupted while the debug program is being executed.

As described above, by controlling execution / interruption of the user program using the mode transition function of the microprocessor, it is possible to perform debug processing without affecting the system status during execution of the user program.
JP 2002-55847 A Japanese Patent Laid-Open No. 2002-202900

  However, conventionally, when a debug interrupt signal is input to the DSU from an external device such as a user terminal, there is a problem that a transition to the debug program execution mode is forced even if any section of the user program is executed. It was.

  In general, a user program is linked with a routine program created by a user other than the user, such as an OS (Operating System) kernel or a library. In many cases, the routine program linked to the user program does not disclose information (for example, source code), and in such a case, it may be difficult to debug the user program.

  For example, when such a routine program is being executed, if the microprocessor is shifted to the debug program execution mode, a situation may occur in which it is impossible to specify where the interrupted location is in the routine program.

  Also, in a user program that implements I / O processing, for example, a program for an Ethernet (registered trademark) controller, if the program is interrupted during data input / output, data acquisition may be incomplete. That is, even if the continuation of the program is executed, there is no guarantee that the continuation data can be completely acquired, and therefore, the subsequent program execution may be hindered.

  The present invention has been made in view of the above problems, and its purpose is to prevent transition to the debug program execution mode during execution of a specific section in the user program regardless of the input of the debug interrupt signal. It is an object of the present invention to provide a microprocessor and a compiling method that are made possible.

  A microprocessor according to the present invention includes a CPU core that executes a user program and a debug program, and a detection block that detects whether or not the CPU core is executing an interrupt-prohibited section that prohibits interruption of execution in the user program. When a debug interrupt signal for requesting execution of the debug program is input while the CPU core is executing an interval other than the interrupt-prohibited interval, the CPU core interrupts the user program and the debug program On the other hand, if the debug interrupt signal is input while the CPU core is executing the interrupt-prohibited section, a determination block that causes the CPU core to continuously execute the user program It is configured as a provision.

  The microprocessor according to the present invention executes a user program to control a connected control target device, and when a debug interrupt signal for requesting execution of a debug program is input to the CPU core. A debug request block for interrupting the user program and executing the debug program. The debug request block is related to the input of the debug interrupt signal when the specific process is performed by the control target device. The user program is not interrupted.

  The compiling method of the present invention is a method in which a compiler compiles a source program into assembly code, the step of detecting an interrupt-prohibited section in which interruption of execution is prohibited in the source program, and the source program And compiling into assembly code and inserting an instruction code representing an interrupt-prohibited section before and after the detected interrupt-prohibited section.

  According to the present invention, since the determination block for determining whether or not the CPU core is executing the section for prohibiting the interruption of the user program is provided during execution of the section, regardless of the input of the debug interrupt signal, It is possible to prevent the transition to the debug program execution mode.

(First embodiment)
First, features of this embodiment will be briefly described.

  In the present embodiment, it is determined whether or not the CPU core is executing a section (critical section) in which execution interruption is prohibited in the user program. When the critical section is being executed, a debug interrupt signal is input. Regardless, the CPU core is not changed to the debug program execution mode.

  Hereinafter, the present embodiment will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a microprocessor 1 as a first embodiment of the present invention.

  The microprocessor 1 is connected to a memory 2 that stores a user program. The microprocessor 1 and the memory 2 are configured by one chip, for example.

  The user program in the memory 2 is inserted with a critical section entry instruction and a critical section end instruction for specifying a section for which interruption during execution is prohibited.

  FIG. 3 is a diagram illustrating an example of a user program (assembly code).

  This user program realizes that data sent from a LAN cable or the like is captured and stored in the memory 2. The user program includes a first instruction group that performs initial processing, an I / O processing instruction group that performs I / O processing, a second instruction group that performs termination processing, and the like. A critical section entry instruction (dentcli) and a critical section end instruction (dextcli) are inserted before and after the I / O processing instruction group.

  The microprocessor 1 is connected to the user terminal 3 and receives a debug interrupt signal for requesting execution of the debug program from the user terminal 3.

  As described above, the microprocessor 1 connected to the memory 2 and the user terminal 3 includes the CPU core 4, the flag setting unit 5, the condition determination block 6, and the DSU (Debug Support Unit) 8.

  The CPU core 4 executes the above-described user program. The CPU core 4 generates a flag setting instruction as a result of execution of the critical section entry instruction (dentcli instruction) and outputs the flag setting instruction to the flag setting unit 5. Further, the CPU core 4 generates a flag release instruction as a result of execution of the critical section end instruction (dextcli instruction), and outputs it to the flag setting unit 5.

  When the flag setting unit 5 receives a flag setting command from the CPU core 4, the flag setting unit 5 sets true (“1”) to the critical section flag. On the other hand, when the flag setting unit 5 receives a flag release command from the CPU core 4, the flag setting unit 5 sets false (“0”) to the critical section flag. This critical section flag is set to false (“0”) as an initial value.

  The condition determination block 6 allows the DSU 8 to pass the debug interrupt signal from the user terminal 3 (a signal requesting transition to the debug program execution mode) or not depending on the contents of the critical section flag. .

  More specifically, when the critical section flag is true (“1”), the condition determination block 6 does not pass the debug interrupt signal from the user terminal 3 to the DSU 8. On the other hand, when the critical section flag is false (“0”), the condition determination block 6 passes the debug interrupt signal from the user terminal 3 to the DSU 8 as it is.

  The DSU 8 includes a debug program that realizes referring to internal resources in the CPU core 4 and the memory 2 (debug processing).

  When the DSU 8 receives a debug interrupt signal from the user terminal 3, the DSU 8 changes the CPU core 4 from the user program execution mode to the debug program execution mode. More specifically, when receiving a debug interrupt signal, the DSU 8 sends a debug start signal to the CPU core 4. The CPU core 4 that has received the debug start signal interrupts the user program being executed (stores the program counter value storing the instruction to be executed next), and executes the debug program 8 in the DSU 8.

  When the DSU 8 receives an instruction (not shown) to stop debugging from the user terminal 3 during execution of the debug program by the CPU core 4, the DSU 8 sends a debug end signal to the CPU core 4. The CPU core 4 that has received the debug end signal executes an instruction (for example, DRET) for ending the execution of the debug program (previously stored in the CPU core 4) to end the debug program, and informs the DSU 8 of that. Notify Thereafter, the CPU core 4 continues to execute the user program from the interrupted location.

  Next, processing steps performed by the microprocessor 1 will be described with reference to the user program shown in FIG.

  FIG. 2 is a flowchart for explaining processing steps performed by the microprocessor 1.

  The CPU core 4 reads the user program (see FIG. 3) in the memory 2, and first executes the first instruction group (step S1). As a result, the CPU core 4 sets initial data necessary for the subsequent I / O processing in the internal register (step S1).

  Next, the CPU core 4 executes a critical section entry instruction (dentcli) arranged next to the first instruction group (step S2). That is, the CPU core 4 sends a flag setting command to the flag setting unit 5, and the flag setting unit 5 that has received the flag setting command sets the critical section flag to “1”.

  Next, the CPU core 4 executes an I / O processing instruction group arranged next to the critical section entry instruction (dentcli) (step S3). That is, the CPU core 4 sequentially fetches data sent from a LAN cable or the like and stores it in the memory 2 (steps S3-1 and S3-2). As shown in FIG. 2, when a debug interrupt signal is input from the user terminal 3 to the condition determination block 6 during data capture, the condition determination block 6 indicates that the critical section flag is true (“1”). The debug interrupt signal is not passed through DSU8. Therefore, the CPU core 4 does not interrupt the I / O processing instruction group being executed.

  When the CPU core 4 receives all the data (YES in step S3-2), the CPU core 4 ends the execution of the I / O processing instruction group, and the critical section end instruction (next to the I / O processing instruction group ( dextcli) is executed (step S4). That is, the CPU core 4 sends a flag release command to the flag setting unit 5, and the flag setting unit 5 that has received the flag release command sets the critical section flag to “0”.

  If the critical section flag is set to “0”, the condition determination block 6 passes the debug interrupt signal from the user terminal 3 to the DSU 8 (step S5). The DSU 8 that has received the debug interrupt signal sends a debug start signal to the CPU core 4. Receiving the debug start signal, the CPU core 4 interrupts the user program being executed and starts execution of the debug program (step S5).

  When the DSU 8 receives a debug stop instruction (not shown) from the user terminal 3 during execution of the debug program by the CPU core 4, a debug end instruction is sent to the CPU core 4 (step S6). The CPU core 4 that has received the debug end instruction executes the above-described DRET instruction, for example, and ends the debug program. The CPU core 4 that has finished the debug program continues to execute the user program from the location interrupted above (step S6).

  Here, in order to better understand this embodiment, the processing steps by a conventional microprocessor will be examined.

  FIG. 4 is a flowchart for explaining processing steps by a conventional microprocessor.

  As shown in FIG. 4, conventionally, when a debug interrupt signal is input during the I / O process (step S22), the mode is forcibly shifted to the debug program execution mode (step S23). For this reason, even if it returns to user program execution mode after completion | finish of debug program execution mode (step S24), the integrity of data is not guaranteed (step S22-2).

  On the other hand, in this embodiment, the I / O processing instruction group is prevented from being interrupted by the critical section entry instruction (dentcli) and the critical section end instruction (dextcli), so the transmitted data is reliably acquired. it can.

  In the above-described example, the interruption in the section specified by the critical section entry instruction and the critical section end instruction is prevented. However, it is also possible to prevent the interruption from the device (control target device) controlled by the CPU core 4. .

  For example, it is assumed that the content of the user program is to heat the liquid filled in the container held by the device to be controlled and to stop heating when it is detected that the liquid has reached a predetermined temperature. The control target device heats the liquid in the container or stops the heating under the control of the CPU core 4. In this case, it is not preferable from the viewpoint of safety to interrupt the running user program during heating. This is because the liquid in the container may be heated beyond an allowable temperature.

  Therefore, as shown in FIG. 5, the control target device 10 is made to have a critical section flag. The control target device 10 sets the critical section flag to “1” when performing specific processing such as heating, and sets the critical section flag to “0” when processing other than the specific processing is performed. To do. The condition determination block 6 determines whether or not to pass the debug interrupt signal based on the critical interval flag.

  As described above, when a critical section entry instruction and a critical section end instruction are inserted into the user program, for example, there is a risk of forgetting to insert by a human being, but in this way, the control target device 10 side is permitted to be interrupted. It is possible to reliably prevent an unexpected situation by determining whether or not.

  Here, in the above example, the critical section is specified by the assembly code. However, a grammar corresponding to the critical section entry and termination instructions is also prepared in a high-level language such as C language, and a compiler corresponding to this is prepared. As a result, a program for specifying a critical section can be created even in a high-level language such as C language.

  In this case, as a compilation processing step, first, a critical section is detected from within a source program described in C language or the like. When the critical section is detected, the source program is compiled to generate assembly code in which a critical section entry and end instruction is inserted before and after the detected critical section.

  As described above, according to the present embodiment, the critical section is specified by the critical section entry instruction and the critical section end instruction, and the debug interrupt signal is not passed during the execution of the critical section. It is possible to prevent the user program from being interrupted and transiting to the debug program execution mode. In other words, according to the present embodiment, it is possible to provide a debugging method that reliably prevents a transition to the debug program execution mode within a critical section and reliably executes a mode transition request in a section other than the critical section. As described above, according to the present embodiment, execution permission / non-permission of the debug program can be controlled by the user program.

  In addition, according to the present embodiment, the conventional user program (source program) written in a high-level language or the like is slightly changed, the setting of the conventional compiler is slightly changed, and the source program is simply recompiled. The assembly code specifying the critical section can be easily generated. Accordingly, it becomes easy to reuse the source program.

(Second Embodiment)
In the present embodiment, it is determined whether or not the CPU core is executing an instruction having a specific address bit pattern. When an instruction having a specific address bit pattern is being executed, The debug interrupt signal is not passed through the DSU 8.

  Hereinafter, this embodiment will be described in detail.

  FIG. 6 is a block diagram showing a configuration of the microprocessor 11 as the second embodiment of the present invention.

  As shown in FIG. 6, the address mask register 12 stores an address bit pattern (address mask) having a predetermined length. When the address length is 32 bits, the address mask is, for example, “1111XXX.X” (X can be “1” or “0”) (X is 28 bits). The address mask in this case represents a pattern in which the upper 4 bits [31:29] are all 1. The address mask in the address mask register 12 can be changed from the CPU core 4 at any time.

  The address mask comparison block 13 receives a program counter (PC) value from the CPU core 4 and compares the program counter value with an address mask. If the program counter value has a bit pattern indicated by the address mask, the address mask comparison block 13 sets the critical interval flag held therein to “1”. On the other hand, when the program counter value does not have the bit pattern indicated by the address mask, the address mask comparison block 13 sets the critical section flag to “0”.

  The condition determination block 6 does not pass the debug interrupt signal from the user terminal 3 to the DSU 8 if the critical section flag in the address mask comparison block 13 is “1”. To pass through.

  As described above, according to the present embodiment, the program counter value is compared with the address mask, and when the program counter value has the bit pattern indicated by the address mask, the debug interrupt signal is not allowed to pass. While the address group having the same bit pattern (for example, a specific segment in the memory 2) is being executed, interruption of the user program can be prevented. That is, the transition from the user program execution mode to the debug program execution mode can be prevented. The above effects will be described below using specific examples.

  For example, in an OS (Operating System) such as Linux (registered trademark) for TX49 core (registered trademark), a 32-bit address space is divided into a plurality of segments and managed by upper 4 bits [31:29]. For example, an OS such as Linux stores a kernel program and an application program in separate segments.

  In such a case, the transition to the debug program execution mode can be prevented during execution of the kernel program by using the bit pattern of the segment storing the kernel program as an address mask.

  Moreover, according to this Embodiment, since it comprised as mentioned above, it is not necessary to add a change to a user program. Therefore, the existing user program can be used as a debugging target in the state as it is.

(Third embodiment)
In the present embodiment, the CPU core determines whether or not an instruction in a designated address range is being executed. If the designated address range is being executed, a debug interrupt signal from the user terminal 3 is output. The DSU 8 is not allowed to pass through.

  Hereinafter, embodiments of the present invention will be described in detail.

  FIG. 7 is a block diagram showing a configuration of the microprocessor 14 according to the third embodiment of the present invention.

  As shown in FIG. 7, the start address register 15 and the end address register 16 hold a start address and an end address, respectively. These start address and end address define a critical section in which interruption is prohibited in the user program. The start address and the end address can be changed by the CPU core 4 at any time.

  The start / end address comparison block 18 receives the program counter value from the CPU core 4, and when this program counter value is included in the address range of the start address and the end address, the critical interval flag held therein is set to “1”. Set to. For example, the critical interval flag is set to “1” when the received program counter value matches the start address, and the critical interval flag is set to “0” when the received program counter value exceeds the end address. .

  The condition judgment block 6 does not pass the debug interrupt signal from the user terminal 3 to the DSU 8 if the critical section flag in the start / end address comparison block 18 is “1”, and if it is “0”, the debug interrupt signal Is passed to DSU8.

  As described above, according to the present embodiment, the debug interrupt signal from the user terminal 3 is not passed to the DSU 8 during the execution of the instruction in the address range specified by the start address and the end address. It is possible to prevent the user program from being interrupted during the execution of a specific address range and entering the debug program execution mode. As a result, it is possible to construct a program debug system in accordance with the hardware architecture unique to the microprocessor.

  Moreover, according to this Embodiment, since it comprised as mentioned above, it is not necessary to add a change to a user program. Therefore, an existing user program can be used as a debugging target as it is.

  Here, in the above description, the start address and the end address can be changed at any time. However, it is preferable that the start address and the end address can be changed without changing the contents of the user program. For this purpose, for example, a ROM monitor program in which a start address and an end address can be set is prepared separately, and this ROM monitor program is operated in the debug program execution mode. As a result, the debug operator can specify the critical section while confirming the system status and the like at any time during the debug operation without changing the contents of the user program.

  In the above description, the first to third embodiments have been described as being separate from each other, but these may be combined.

  For example, priorities that can be appropriately changed are set for the critical section flags in the first to third embodiments, and the critical section flag having the highest priority is applied. This enables more flexible debugging work.

It is a block diagram which shows the structure of the microprocessor as the 1st Embodiment of this invention. It is a flowchart for demonstrating the processing step by a microprocessor. It is a figure which shows the example of a user program containing a critical area approach command and a critical area end command. It is a flowchart explaining the processing step by the conventional microprocessor. It is a figure which shows the structure of the microprocessor which enabled control of whether the interruption of a user program from the control object apparatus side by CPU core 4 was possible. It is a block diagram which shows the structure of the microprocessor as the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the microprocessor as the 3rd Embodiment of this invention.

Explanation of symbols

1, 11, 14 Microprocessor 2 Memory 3 User terminal 4 CPU core 5 Flag setting unit 6 Condition determination block 8 DSU
10 control target device 12 address mask register 13 address mask comparison block 15 start address register 16 end address register 18 start / end address comparison block

Claims (6)

A CPU core for executing a user program and a debug program;
A detection block for detecting whether or not the CPU core is executing in the user program an interrupt prohibition section that prohibits interruption of execution;
When a debug interrupt signal for requesting execution of the debug program is input while the CPU core is executing an interval other than the interrupt-prohibited interval, the user program is interrupted by the CPU core and the debug program is executed. On the other hand, when the debug interrupt signal is input while the CPU core is executing the interrupt prohibited section, a determination block that causes the CPU core to continuously execute the user program;
A microprocessor comprising: The user program has an interrupt prohibition instruction that prohibits interruption of execution in a specified section,
The detection block detects whether or not the CPU core is executing the interrupt prohibited section based on whether or not the CPU core is executing the specified section by the interrupt prohibition instruction. The microprocessor of claim 1, comprising:   The detection block holds a predetermined memory address pattern, and the CPU core 2. The microprocessor according to claim 1, further comprising detection means for detecting whether or not the interrupt prohibited section is being executed.   The detection block has a predetermined start memory address and a predetermined end memory address, and based on whether or not the CPU core is executing an instruction in a memory address section by the start memory address and the end memory address, 2. The microprocessor according to claim 1, further comprising detection means for detecting whether or not the CPU core is executing the interrupt prohibited section. A CPU core that executes a user program to control a connected control target device; and
A debug request block for interrupting the user program to cause the CPU core to execute the debug program when a debug interrupt signal requesting execution of the debug program is input;
The microprocessor characterized in that the debug request block does not interrupt the user program regardless of the input of the debug interrupt signal when a specific process is performed by the control target device. A method by which a compiler compiles a source program into assembly code,
Detecting in the source program an interrupt prohibited section in which execution interruption is prohibited;
Compiling the source program into assembly code and inserting an instruction code representing an interrupt-prohibited section before and after the detected interrupt-prohibited section;
Compile method with

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