JP2005135480A - Semiconductor storage - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage having a prevention means for preventing a user from using a test function except functions to be used by the user among the incorporated test functions. <P>SOLUTION: When no test functions are utilized, a bonding pad section 9 is set to be non-connected state with a terminal. When address signals A6, A7 are at an H level and the potential level of an address signal BA0 is at power supply potential or higher, a signal TMODE is activated and the semiconductor storage 1 is set to a test mode. This sort of setting cannot be conducted from a microcomputer, or the like. Even if a test mode is set erroneously, signals TF1-TF3 can be deactivated if a command AREF is instructed from the microcomputer, or the like. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device, and more particularly to a test mode determination circuit provided in the semiconductor memory device.

  A semiconductor memory device generally has a plurality of test modes in which special functions are activated. Specific examples of special functions include an address degeneration function to shorten the memory cell test in a short time, a margin test function to impose a test under severe conditions by reducing the operation margin of the memory cell, or an initial defective product. There is a voltage control function for reducing burn-in.

There is a prior art for preventing a semiconductor memory device from erroneously entering a test mode when a general user uses the semiconductor memory device as usual. For example, Japanese Patent Application Laid-Open No. 11-304982 (Patent Document 1) sets a test mode when both a command signal and a test signal having a voltage higher than the operating voltage are input, thereby causing erroneous signal input and noise. Disclosed is a semiconductor memory device that prevents a test mode from being input.
Japanese Patent Application Laid-Open No. 11-304982

  Conventional semiconductor memory device test mode setting methods include a method of applying a high voltage to a specific input terminal, as shown in the prior art, because the test mode is not accidentally set during normal use. It was.

  In recent years, semiconductor memory devices shipped in a wafer state are sometimes processed into chips on the user side and sealed in the same package in combination with a microcomputer chip or the like. In order for the user to perform burn-in and various tests on the semiconductor memory device, a microcomputer or the like must send a signal to set the semiconductor memory device to the test mode.

  However, since a high voltage cannot be supplied from the output terminal of the microcomputer, the user cannot use the test function built in the semiconductor memory device with the conventional test mode setting method.

  Therefore, there is a need for a semiconductor memory device that is not erroneously set to the test mode during normal operation and that can be easily set to the test mode by an instruction from a microcomputer or the like.

  In addition, since there are restrictions on input signal combinations and supply potentials in the instructions from the microcomputer or the like, it is impossible to use all the test functions using the microcomputer or the like. If the test function designed on the assumption that it is used by a dedicated test device is released to the user who uses the microcomputer, the semiconductor memory device can be moved from the test mode even if a command to exit the test mode is sent from the microcomputer. There is a problem that it cannot be removed, and further, there is a problem that the semiconductor memory device itself and the microcomputer as a controller are damaged.

  Therefore, there is a need for a semiconductor memory device provided with prevention means that cannot use a test function other than the test mode that should be used by the user among the test functions built in the semiconductor memory device.

  In summary, the present invention is a semiconductor memory device having a test mode and a normal mode as operation modes, and includes a memory circuit and a first operation control unit that performs a read operation and a write operation on the memory circuit in the normal mode. And a second operation control unit that performs a plurality of test operations on the memory circuit in the test mode, wherein the second operation control unit enables or disables at least one of the plurality of test operations. A test operation instruction for instructing each of a plurality of test operations to be valid or invalid in response to a designation unit for holding designation information to be designated in a non-volatile manner, an address signal and a command setting signal given from the outside, and the designation information And a test operation unit that performs a plurality of test operations on the memory circuit in response to an instruction from the test operation instruction unit.

  Since the semiconductor memory device of the present invention includes the option pad, it is possible to respond to each user specifying whether the test mode setting is valid or invalid.

  Further, the semiconductor memory device of the present invention is not set to the test mode if the option pad is not connected to the power supply terminal, and can be easily removed even if the test mode is entered.

  The semiconductor memory device of the present invention is set to the test mode in response to an instruction from a microcomputer or the like when the option pad is connected to the power supply terminal, and once set to the test mode, the test mode is not accidentally exited. .

  Also, when the semiconductor memory device of the present invention is used from a microcomputer or the like, a special test function used in a memory tester or the like is not activated, even if the special test function is activated by mistake, Inactivated by a signal from a microcomputer or the like.

[Embodiment 1]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

  FIG. 1 is a block diagram of the semiconductor memory device of the first embodiment. In FIG. 1, a block diagram of a synchronous DRAM (synchronous dynamic random access memory: SDRAM) is shown as an example of a semiconductor memory device.

  Referring to FIG. 1, a semiconductor memory device 1 includes a memory circuit 2 having a plurality of memory cells arranged in a matrix, and a normal operation control unit 3 that performs a read operation and a write operation on the memory circuit 2 in a normal mode. And a test operation control unit 4 for performing a test operation on the memory circuit 2 in the test mode.

  The test operation control unit 4 includes test function units 5 to 7 for performing various test functions in the test mode, and a test operation instruction unit for generating signals TF1 to TF3 for instructing the test function units 5 to 7 to be activated or deactivated. 8 and a bonding pad unit 9 that generates a signal SIPON for designating activation or deactivation of at least one of the signals TF1 to TF3 as valid or invalid for the test operation instruction unit 8.

  The bonding pad portion 9 is selected to be connected to a terminal by wire bonding or not connected when the semiconductor memory device 1 is sealed in a package. When the bonding pad portion 9 is connected to the terminal and the potential of the bonding pad portion becomes the power supply potential VDD, the signal SIPON is generated.

  Test function units 5 to 7 constitute test operation units for performing various test operations on memory circuit 2. The test function unit 5 provides a test function that can be used by the microcomputer, and is activated in response to the signal TF1. The test function unit 6 cannot be used in response to an instruction from a microcomputer or the like, and can be used when an address signal having a potential level equal to or higher than the power supply potential is input to a predetermined terminal by a dedicated memory tester, and is activated by receiving the signal TF2. It becomes. The test function unit 7 cannot be used in response to an instruction from a microcomputer or the like, but provides a test function that can be used by generating a combination of necessary input signals using a dedicated memory tester, and is activated in response to the signal TF3. .

  Specific examples of the test functions to be provided for the test function units 5 to 7 will be described. For example, the test function unit 5 performs an acceleration test by increasing the internal voltage, and provides a burn-in function for preventing the occurrence of an initial failure by an end user. The test function unit 6 provides, for example, a voltage application mode test function that changes the potential applied to a specific terminal to the potential of the internal voltage. The test function unit 7 provides a degeneration test function that shortens the test time by degenerating the memory address and the output terminal, for example.

  The test operation instruction unit 8 includes an MRS / AREF determination unit 10 that detects that an external command is MRS (mode register set) or AREF (auto refresh) in synchronization with a clock signal CLK input from the outside. The command is given by a combination of signals / CS (chip select signal), / RAS (row address strobe signal), / CAS (column address strobe signal), and / WE (write enable signal).

  If the detected command is MRS, the MRS / AREF determination unit 10 receives the signal TMODE and the address signals A6 and A7, determines the operation mode, and determines whether it is the signal NMRS indicating the normal mode setting or the signal TMRS indicating the test mode setting. One of the signals is generated. Further, if the detected command is AREF, the MRS / AREF determination unit 10 generates a signal AREF indicating that auto refresh is instructed.

  Further, when a test signal having a voltage level (super VIH level) sufficiently higher than the power supply potential is applied to the input terminal of the address signal BA0, the test operation instruction unit 8 is a signal SVIHON indicating that the special test function is effective. SVIH detection unit 11 for generating

  In response to signal TMRS and signal SVIHON, test operation instruction unit 8 activates signal TMODE indicating that semiconductor memory device 1 has been set to the test mode, and signal SVIHFLAG for using the special test function. A test mode determination unit 12 is included. When either the signal NMRS or the signal AREF is input, the test mode determination unit 12 inactivates the signal TMODE and the signal SVIHFLAG.

  Test operation instructing unit 8 further receives signals A0-A6, signal TMODE, signal SVIHFLAG, and signal TMRS to generate signals TF1-TF3 for activating test function units 5-7. And a function decoding unit 13.

  When the test function is not used, the bonding pad unit 9 is set in a non-connected state with the power supply terminal. Such a setting is performed, for example, by not wire bonding the leads of the lead frame and the pads on the chip. If address signals A6 and A7 are at the H level and the potential level of address signal BA0 is equal to or higher than the power supply potential, signal TMODE is activated and semiconductor memory device 1 is set to the test mode. Such setting cannot be made from a microcomputer or the like, and even if the test mode is set by mistake, the signals TF1 to TF3 are inactivated if a command indicating AREF is given from the microcomputer or the like. Therefore, even if the test mode is once set, it can be easily exited.

  When using the test function, the bonding pad portion 9 is connected to a terminal. Such setting is performed, for example, by wire bonding the leads of the lead frame and the pads on the chip. In this case, since the potential level of the address signal BA0 does not need to be higher than the power supply potential, the semiconductor memory device 1 can be easily set to the test mode upon receiving a mode setting command from a microcomputer or the like. In this case, the semiconductor memory device 1 again receives a mode setting command from the outside in order to exit from the test mode. Since no mode setting command is generated during operation except during initialization, the semiconductor memory device 1 will not accidentally exit the test mode once it is set to the test mode.

  FIG. 2 is a schematic block diagram showing the configuration of the memory circuit 2 and the normal operation control unit 3 shown in FIG.

  Referring to FIG. 2, normal operation control unit 3 receives address signals A0 to A7, address signals BA0 and BAl, clock signal CLK, and signals / CS, / RAS, / CAS, / WE from the outside. The normal operation control unit 3 receives the clock signal CLK and outputs the clock signals CLKI and CLKQ, and takes in the address signals A0 to A7 in synchronization with the clock signal CLK, the internal row address X, and the internal column address Y. And a control signal input buffer 203 for capturing signals / CS, / RAS, / CAS, / WE in synchronization with clock signal CLKI.

  The normal operation control unit 3 further receives an internal address signal from the address buffer 202, and controls the control signal int. RAS, int. CAS, int. A control circuit that receives WE and outputs a control signal to each block in synchronization with a clock signal CLKI, and a mode register that holds an operation mode recognized by the control circuit. In FIG. 2, the control circuit and the mode register are shown as one block 204. Block 204 receives the signal NMRS.

  The control circuit includes a bank decoder for specifying a bank from an address signal, and a control signal int. RAS, int. CAS, int. And a command decoder for receiving and decoding the WE.

  Memory circuit 2 includes memory cells MC arranged in a matrix for each memory array bank 14 # 0 to 14 # 3 and each memory array bank, and a plurality of word lines WL provided corresponding to the rows of memory cells MC. And bit line pairs BLP provided corresponding to the columns of memory cells MC. FIG. 2 representatively shows one memory cell MC, word line WL, and bit line pair BLP. Memory circuit 2 is further provided corresponding to each of memory array banks 14 # 0 to 14 # 3, and decodes row address signal X applied from address buffer 202, and output signals of these row decoders. And a word driver for driving the addressed row (word line) inside memory array bank 14 # 0-14 # 3 to the selected state. In FIG. 2, the row decoder and the word driver are collectively shown as blocks 10 # 0 to 10 # 3.

  Memory circuit 2 further decodes internal column address signal Y applied from address buffer 202 to generate a column selection signal, and column decoders 12 # 0-12 # 3 and memory array banks 14 # 0-14 # 3. Sense amplifiers 16 # 0 to 16 # 3 for detecting and amplifying data of memory cells connected to the selected row.

  Blocks 18 # 0-18 # 3 are preamplifiers and write drivers corresponding to the memory array banks 14 # 0-14 # 3, respectively.

  Memory circuit 2 further includes an input buffer 206 that receives external write data and outputs internal write data, a write driver that amplifies internal write data from input buffer 206 and transmits the amplified internal write data to a selected memory cell, A preamplifier for amplifying data read from the selected memory cell and an output buffer 205 for further buffering the data from the preamplifier and outputting the data to the outside are included.

  Next, the configuration and operation of the test operation control unit 4 in FIG. 1 will be described.

  FIG. 3 is a diagram illustrating an example of the configuration of the MRS / AREF determination unit 10 in FIG. The MRS / AREF determination unit 10 detects that the external command is MRS (mode register set) or AREF (auto-refresh) in synchronization with the clock signal CLK input from the outside, and indicates that the command has been detected. Generate a signal.

  Referring to FIG. 3, MRS / AREF determination unit 10 receives inverter circuits 301 to 303 connected in series to output a delay signal of clock signal CLK, and receives clock signal CLK and the output signal of inverter circuit 303. And an AND circuit 304 for calculating a logical product. The signal CLKP generated by the AND circuit 304 is a pulse synchronized with the rising edge of the clock signal CLK.

  MRS / AREF determination unit 10 further includes a NOR circuit 305 that receives signals / CS, / RAS, / CAS, / WE, and a logic gate 306. The NOR circuit 305 is a determination circuit that determines whether or not the command is MRS, and the logic gate 306 is a determination circuit that determines whether or not the command is AREF. Logic gate 306 outputs an H level signal when signals / CS, / RAS, / CAS are at L level and / WE is at H level.

  The MRS / AREF determination unit 10 further includes an OR circuit 307 that calculates the logical sum of the address signal A6 and the signal TMODE, and an AND circuit 308 that calculates the logical product of the output signal of the OR circuit 307 and the address signal A7. Including.

  The MRS / AREF determination unit 10 further includes an inverter circuit 309 that inverts the output signal of the AND circuit 308, an AND circuit 310 that calculates a logical product of the output signal of the AND circuit 305 and the output signal of the AND circuit 308, and AND An AND circuit 311 that calculates a logical product of the output signal of the circuit 305 and the output signal of the inverter circuit 309 is included.

  The MRS / AREF determination unit 10 further includes an inverter circuit 312 that inverts the output signal of the AND circuit 310, an inverter circuit 313 that inverts the output signal of the AND circuit 311, and an inverter circuit 314 that inverts the output signal of the logic gate 306. AND circuit 315 that calculates the logical product of the output signal of AND circuit 310 and signal CLKP, AND circuit 316 that calculates the logical product of the output signal of inverter circuit 312 and signal CLKP, and the output signal of AND circuit 311 AND circuit 317 that calculates the logical product of the output signal of the inverter circuit 313, AND circuit 318 that calculates the logical product of the output signal of the inverter circuit 313 and the signal CLKP, and the logical product of the output signal of the logic gate 306 and the signal CLKP. The AND circuit 319 that performs the operation and the output signal and signal of the inverter circuit 314 And an AND circuit 320 that arithmetically calculates a logical product of CLKP.

  The MRS / AREF determination unit 10 further includes a flip-flop 321 that is set by the output signal of the AND circuit 317, is reset by the output signal of the AND circuit 318, and outputs a signal NMRS indicating that the normal mode setting command has been received. .

MRS / AREF determination unit 10 further includes a flip-flop 322 that is set by the output signal of AND circuit 315, reset by the output signal of AND circuit 316, and outputs signal TMRS indicating that a test mode setting command has been received. .

  The MRS / AREF determination unit 10 is further a flip-flop that is set by the output signal from the AND circuit 319, reset by the output signal from the AND circuit 320, and outputs a signal AREF indicating that the auto-refresh command has been received at the H level. 323.

  FIG. 4 is a truth table of signals representing commands input from the outside in MRS / AREF determination unit 10.

  Referring to FIG. 4, MRS / AREF determination unit 10 activates (sets) each signal according to the rising edge of signal CLKP, and deactivates each signal according to the next rising edge of signal CLKP. Reset).

  The signal NMRS and the signal TMRS are distinguished by the address signal A7, the address signal A6, and the signal TMODE. The signal TMODE is L level in the normal mode, but is H level in the test mode.

  Signals NMRS are set with signals / CS, / RAS, / CAS, / WE all at L level, signal TMODE at L level, address signal A6 at L level, and address signal A7 at H level. The signal NMRS is set even when the signal TMODE and the address signal A6 are at an arbitrary logic level and the address signal A7 is at the L level.

  On the other hand, the signal NMRS is reset if the combination of the logic levels of the signals / CS, / RAS, / CAS, / WE, the address signals A6, A7, and the signal TMODE is a combination other than the combination that sets the signal NMRS described above. The

  Signal TMRS is set even if the level of signal TMODE is arbitrary as long as signals / CS, / RAS, / CAS, / WE are all at L level and address signals A6 and A7 are both at H level. Signal TMRS is set when signals / CS, / RAS, / CAS and / WE are all at L level, signal TMODE is at H level, address signal A6 is at L level, and address signal A7 is at H level.

  On the other hand, the signal TMRS is reset if the combination of the logic levels of the signals / CS, / RAS, / CAS, / WE, the address signals A6, A7, and the signal TMODE is a combination other than the combination that sets the signal TMRS described above. The

  The signal AREF is set even if the address signal A6, the address signal A7, and the signal TMODE are at arbitrary logic levels if the signals / RAS, / CAS, / CS are at L level and / WE is at H level. .

  On the other hand, the signal AREF is reset if the combination of the logic levels of the signal / RAS, / CAS, / CS, / WE, the address signal A6, the address signal A7, and the signal TMODE is a combination other than the above-described combination of the signal AREF. Is done.

In the configuration example of the MRS / AREF determination unit 10 shown in FIG. 3, the address signal A6 and the address signal A7 are used as signals for generating the signal NMRS as long as the address signals A6 and A7 are not simultaneously at the H level in the normal mode. Can be used. On the other hand, if the signal TMODE is at the H level, the address signal A7 can be used for setting the test mode, and the address signal A6 can be used as a signal for decoding the test function.

  FIG. 5 is a diagram showing an example of the configuration of the bonding pad portion 9 in FIG.

  The bonding pad unit 9 is used for a setting for not using the test function by a general user, or a setting for restricting the use of a test function that should not be used by a user using the test mode.

  Referring to FIG. 5, bonding pad portion 9 includes an option pad 401, an N channel MOS transistor 402, and inverter circuits 403 to 405.

  N channel MOS transistor 402 is connected between nodes N1 and N2. Inverter circuit 403 is connected between node N 3 and the gate of N-channel MOS transistor 402.

  The potential of the option pad 401 is determined by the connection with the lead by wire bonding at the time of assembly. The potential of the option pad is delayed by inverter circuits 404 and 405, and signal SIPON is generated.

  When option pad 401 is set to the non-connected state, N channel MOS transistor 402 is rendered conductive and the potential of node N3 becomes the ground potential, so that signal SIPON is at the L level. On the other hand, if option pad 401 is connected and the potential of option pad 401 is the power supply potential, N-channel MOS transistor 402 is non-conductive and signal SIPON is at H level.

  According to the configuration example of the bonding pad section 9 shown in FIG. 5, the use of the test function can be set to be valid or invalid depending on whether the logic level of the signal SIPON is H level or L level. For example, when the option pad 401 is not connected and the signal SIPON is at L level, the test function is disabled, the option pad 401 is connected to a predetermined terminal to supply a power supply potential, and when the signal SIPON is at H level, the test function is enabled. can do.

  FIG. 6 is a diagram illustrating an example of the configuration of the SVIH detection unit 11 in FIG. The SVIH detection unit 11 detects that a test signal having a potential exceeding the power supply potential is input from the outside in order to use the special test function.

  Referring to FIG. 6, SVIH detection unit 11 includes an operational amplifier 501 and N channel MOS transistors 502 to 505.

  N channel MOS transistors 502 to 504 are diode-connected in series between nodes N11 and N12 so as to be in the forward direction from node N11 to node N12. N-channel MOS transistor 505 is diode-connected between nodes N12 and N13 so as to be in the forward direction from node N12 toward node N13.

  The voltage of the node N12 is input to the non-inverting input terminal of the operational amplifier 501. The power supply potential VDD is input from the node N14 to the inverting input terminal of the operational amplifier 501 as a reference voltage for comparison operation. The result of the comparison operation of the operational amplifier 501 is output as a signal SVIHON.

An address signal BA0 is input to the node N11. When the signal voltage of the address signal BA0 is VBA0 and the threshold voltage of the N channel MOS transistors 502 to 504 is Vth, the voltage at the node N12 is a voltage drop from the voltage VBA0 by the threshold voltage Vth of the N channel MOSs 502 to 504. (VBA0-3 × Vth) is applied. However, since the power supply potential VDD is applied to the node N13, the voltage at the node N12 is equal to the threshold voltage Vth of the N-channel MOS transistor 505 from the power supply potential VDD if the potential of the node N11 is about the power supply potential VDD. A dropped voltage (VDD-Vth) is also applied.

  In the normal test mode, the voltage at the node N11 is equal to or lower than the power supply potential VDD. Therefore, since the potential at node N12 is about (VDD−Vth), signal SVIHON is at the L level. On the other hand, when the potential of address signal BA0 is sufficiently higher than power supply potential VDD and the potential of node N2 exceeds power supply potential VDD, output signal SVIHON becomes H level.

  In the configuration example of the SVIH unit 11 shown in FIG. 6, since a test signal exceeding the power supply potential that does not occur in a normal use state is input, it is possible to determine that the operation mode is the test mode.

  FIG. 7 is a diagram illustrating a configuration example of the test function decoding unit 13 in FIG. Test function decode unit 13 receives signals A0 to A6, signal TMODE, signal SVIHFLAG, and signal TMRS, and generates signals TF1 to TF3 for activating test function units 5 to 7.

  Referring to FIG. 7, test function decode unit 13 includes test function activation units 701, 702, and 703.

  Test function activation unit 701 receives signal TMRS and address signals A0 to A2 and performs a logical operation, logic gate 711 that receives address signals A3 to A6, a NOR circuit 712 that calculates a negative sum, and an output of logic gate 711 AND circuit 713 that receives a signal and an output signal of NOR circuit 712 and calculates a logical product, AND circuit 714 that receives AND circuit 713 and signal TMODE and calculates a logical product, and an inverter that receives and inverts signal TMODE The circuit 715 includes a flip-flop 717 that is set by an output signal from the AND circuit 714, is reset by an output signal from the inverter circuit 715, and outputs a signal TF1.

  Logic gate 711, NOR circuit 712, and AND circuit 713 form a decoding circuit that decodes signal TMRS and address signals A0 to A6 to generate signal TF1. The AND circuit 714, the inverter circuit 715, and the flip-flop 717 hold the signal TF1 when the output signal of the AND circuit 713 is input at the H level, and the signal TF1 when the signal TMODE is input at the L level. This is a latch circuit for releasing the holding.

  Test function activation unit 702 receives signal TMRS and addresses A0 to A2 and performs a logical operation, logical gate 721 which receives addresses A3 to A6 and performs a NOR operation, and an output signal of logical gate 721 An AND circuit 723 that receives the output signal of the NOR circuit 722 and calculates a logical product; an AND circuit 724 that receives the output signal of the AND circuit 723, the signal TMODE, and the signal SVIHFLAG; It includes an inverter circuit 725 that receives and inverts TMODE, and a flip-flop 727 that is set by an output signal from the AND circuit 724, is reset by an output signal from the inverter circuit 725, and outputs a signal TF2.

Logic gate 721, NOR circuit 722, and AND circuit 723 form a decoding circuit that decodes signal TMRS and address signals A0 to A6 to generate signal TF2. The AND circuit 724, the inverter circuit 725, and the flip-flop 727 hold the signal TF2 when the output signal of the AND circuit 723 is input at the H level, and the signal TF2 when the signal TMODE is input at the L level. This is a latch circuit for releasing the holding.

  Test function activation unit 703 receives signal TMRS and addresses A0 to A2 and performs logic operation, logic gate 731 which receives addresses A3 to A6 and performs logic operation, and logic gate 731 output signal and logic An AND circuit 733 that receives the output signal of the gate 732 and calculates a logical product, an AND circuit 734 that receives the output signal of the AND circuit 733 and the signal TMODE, and calculates a logical product, and receives and inverts the signal TMODE. The inverter circuit 735, the output signal of the inverter circuit 735 and the signal AREF are received, the OR circuit 736 for calculating the logical sum, and the output signal of the AND circuit 734 are set. The output signal from the OR circuit 736 is reset. And a flip-flop 737 that outputs TF3.

  Logic gate 731, logic gate 732, and AND circuit 723 constitute a decode circuit that decodes signal TMRS and address signals A 0 to A 6 to generate signal TF 3. The AND circuit 734, the inverter circuit 735, the OR circuit 736, and the flip-flop 737 hold the signal TF3 when the output signal of the AND circuit 733 is input at the H level, and the signal TMODE is input at the L level. Or a latch circuit that releases the holding of the signal TF3 when the signal AREF is input at the H level.

  FIG. 8 is a diagram showing a truth table of signals indicating commands for setting signals TF1 to TF3.

  First, the logic level of each signal for activating (setting) the signals TF1 to TF3 will be described.

  Referring to FIG. 8, signal TF1 is set at signal TMRS, signal TMODE, address signals A0 and A7 at H level, and address signals A1 to A6 at L level.

  Signal TF2 is set when signal TMRS, signal TMODE, address signals A1 and A7 are at the H level, and signal SVIHFLAG is at the H level. When the test mode is set by a microcomputer or the like, since the potential level of the address signal BA0 is equal to or lower than the power supply potential VDD, the signal SVIHFLAG is at the L level. That is, the signal TF2 cannot be set by a microcomputer or the like, a signal having a potential higher than the power supply potential VDD is input to the input terminal of the address signal BA0 from a dedicated memory tester or the like, and the signal TMRS is input to the test function activation unit 702 Need to be done.

  The signal TF3 is set when the signal TMRS, the signal TMODE, the address signals A0, A6, and A7 are at the H level and the address signal A1 and the address signals A2 to A5 are at the L level.

  Next, the logic level of each signal for initializing (resetting) the held values of the signals TF1 to TF3 will be described.

  The signals TF1 to TF3 are reset if the signal TMODE is at L level. If the signal TMRS is not set, the signal TF3 is reset regardless of the logic level of the signal TMODE if the signal AREF is at the H level.

FIG. 9 is a diagram showing an example of the configuration of the test mode determination unit 12 in FIG. In response to signal TMRS and signal SVIHON, test mode determination unit 12 activates signal TMODE indicating that semiconductor memory device 1 has been set to the test mode, and signal SVIHFLAG for using the special test function. . When either the signal NMRS or the signal AREF is input, the test mode determination unit 12 inactivates the signal TMODE and the signal SVIHFLAG.

  Referring to FIG. 9, test mode determination unit 12 receives AND signal 801 that receives signal TMRS and signal SVIHON and calculates a logical product, and AND circuit 802 that receives signal TMRS and signal SIPON and calculates a logical product. A logic gate 803 that receives the signal AREF and an inverted signal of the signal SIPON and performs a logical operation; an OR circuit 804 that receives the output signal of the AND circuit 801 and the output signal of the AND circuit 802 and calculates a logical sum; An OR circuit 805 that receives the signal NMRS and the output signal of the logic gate 803 and calculates a logical sum.

  The test mode determination unit 12 is further set by the output signal of the AND circuit 801, reset by the output signal of the OR circuit 805, and set by the output signal of the OR circuit 804 and the flip-flop 806 that outputs the signal SVIHFLAG. A flip-flop 807 that is reset by an output signal of the circuit 805 and outputs a signal TMODE.

  FIG. 10 is a diagram illustrating a truth table of signals for commands in the test mode determination unit 12.

  A case where the signal TMODE is activated (set) will be described with reference to FIG.

  In normal use by a general user who does not use the test mode, the option pad 401 in FIG. 5 is disconnected from the terminal, and the signal SIPON is at L level. If signal SIPON is at L level and both signals TMRS and SVIHON are at H level, signal TMODE is set. In order to set the signal TMRS, as already described with reference to FIG. 4, the command input from the outside must be MRS, and the logical levels of the address signals A7 and A6 must be H level.

  Further, in order for the signal SVIHON to be at the H level, the potential of the address signal BA0 must be sufficiently higher than the power supply potential VDD as already described with reference to FIG.

  Since all of these condition settings cannot be performed by a microcomputer or the like, the semiconductor memory device of the present invention is not erroneously set to the test mode in a normal use state. When all these input conditions are met using a dedicated memory tester or the like, both the signal TMRS and the signal SVIHON are at the H level, so that both the signal TMODE and the signal SVIHFLAG can be at the H level.

  On the other hand, when used by a user who uses the test mode, the option pad 401 in FIG. 5 is connected to a terminal and supplied with a power supply potential, so that the signal SIPON is at the H level. If signal SIPON is at H level, signal TMODE is at H level when signal TMRS is input. That is, even if the potential of the address signal BA0 is not equal to or higher than the power supply potential, the signal TMODE becomes H level. Since the signal TMODE can be set to the H level only by command and address control, the semiconductor memory device can easily enter the test mode using a microcomputer or the like.

  Next, the case where signal SVIHFLAG is set to H level will be described.

  In this case, the logic level of the signal SIPON is arbitrary. If the potential of address signal BA0 is equal to or higher than the power supply potential and signal TMRS is at H level, signal SVIHFLAG is set. Therefore, even if the option pad is connected, a special test function can be used by setting the potential of the address signal BA0 to be equal to or higher than the power supply potential using a dedicated memory tester.

  Next, a case where the held values of the signal TMODE and the signal SVIHFLAG are initialized (reset) will be described.

  In order to reset the signal TMODE and the signal SVIHFLAG, the signal NMRS must be input to the test mode determination unit 12. However, in the operation of the semiconductor memory device, a command indicating MRS is not generated during the operation except during the initialization period. Therefore, the semiconductor memory device of the present invention can prevent accidental exit from the test mode once it enters the test mode.

  In normal use by a general user who does not use the test mode, the signal SIPON is at L level as described above. In this case, when the signal AREF is input to the test mode determination unit 12, the signal TMODE and the signal SVIHFLAG are reset. In the SDRAM, a command indicating AREF is periodically input from the outside. Therefore, even if the semiconductor memory device of the present invention enters the test mode by mistake during the normal mode, it can easily exit from the test mode by a command signal periodically sent from a microcomputer or the like.

  FIG. 11 is a diagram illustrating operation timing when the option pad is set to the non-connection state. When the semiconductor memory device of the present invention is used for general purpose, the test function is not used on the user side, so the option pad is set to a non-connected state.

  Referring to FIG. 11, signal SIPON is at L level as described above.

  In clock cycle T0, since the command received from the outside is MRS, signal TMRS attains the H level in synchronization with the rise of signal CLKP. Further, the signal TMODE becomes H level in synchronization with the rise of the signal TMRS.

  The potential of the address signal BA0 is usually equal to or lower than the power supply potential. When a signal higher than the power supply potential VDD (indicated by a dotted line in the figure) is input from the dedicated memory tester through the input terminal of the address signal BA0, the signal SVIHON becomes H level in synchronization with the rise of the address signal BA0. . Further, the signal SVIHFLAG becomes H level in synchronization with the rise of the signal SVIHON.

  In clock cycles T1 to T3, signal TMRS rises in each clock cycle, signal TMRS and address signals A0 to A7 are decoded, and signals TF1, TF2, and TF3 sequentially become H level, and the operation mode is set to test mode. The

  In clock cycle T4, since the command received from the outside is AREF, signal AREF becomes H level in synchronization with the rise of signal CLKP. In synchronization with the rise of the signal AREF, the signals TF1 to TF3 change from the H level to the L level, and the signal TMODE and the signal SVIHFLAG change from the H level to the L level.

  In clock cycle T5, the command received from the outside is MRS, and signal NMRS rises to H level. The operation mode is set to the normal mode.

  As described above, if the signal SIPON is at the L level, the signals TF1 to TF3 change from the H level to the L level in synchronization with the rising of the signal AREF in the clock cycle T4. Therefore, the semiconductor memory device of the present invention can exit from the test mode by receiving a command indicating AREF from the outside even if the option pad is set in the non-connection state even if it is erroneously set to the test mode.

  FIG. 12 is a diagram illustrating the operation timing in a setting in which option pads are connected. When the semiconductor memory device of the present invention is inspected on the user side and enclosed in the same package as the microcomputer or the like, it is necessary to set a general user to open the test function. Therefore, at the time of assembly, the option pad 401 in FIG. 5 is connected to the terminal. Further, since a signal is sent from a microcomputer or the like, the potential level of the address signal BA0 is the power supply potential VDD.

  Referring to FIG. 12, signal SIPON is at the H level because option pad 401 in FIG. 5 is connected to the terminal and power supply potential VDD is applied.

  In the clock cycle T0, the signal TMRS becomes H level in synchronization with the rise of the signal CLKP, as in FIG. Further, the signal TMODE becomes H level in synchronization with the rise of the signal TMRS. Since the potential of address signal BA0 is about power supply potential VDD, signal SVIHON is at the L level. Therefore, signal SVIHFLAG is also at L level.

  In clock cycles T1 to T3, signal TMRS rises in each clock cycle, as in FIG. Signals TF1 and TF3 are set to H level by decoding signal TMRS and address signals A0 to A7, as in FIG. Since the signal SVIHFLAG is at the L level, the signal TF2 remains at the L level at the clock cycle T2.

  In clock cycle T4, as in FIG. 11, since the command received from the outside is AREF, signal AREF becomes H level in synchronization with the rise of signal CLKP. In synchronization with the rise of the signal AREF, the signal TF3 changes from H level to L level. Unlike FIG. 11, since the signal TMODE is at the H level, the signal TF1 remains at the H level.

  In clock cycle T5, as in FIG. 11, the command received from the outside is MRS, and signal NMRS rises to H level. In synchronization with the rise of the signal NMRS, the signal TF1 falls and the signal TMODE falls. The operation mode is set to the normal mode in synchronization with the fall of the signal TMODE.

  As described above, unlike FIG. 11, when the test mode is set, the signal TF1 is not affected by the signal AREF and changes from the H level to the L level in synchronization with the rise of the signal NMRS. Similarly to FIG. 11, the signal TF3 changes from the H level to the L level in synchronization with the rise of the signal AREF. Therefore, the semiconductor memory device of the present invention opens only the test function to be used by the user when the option pad is connected to a predetermined terminal. In addition, a test function that is not desired by the user can exit from the test mode when receiving a command indicating AREF from the outside even if the test mode is once set.

  FIG. 13 is a diagram showing operation timing when a high potential is applied to the address signal BA0 in FIG. Similar to FIG. 12, the option pad 401 of FIG. 5 is connected to a terminal during assembly. Further, a potential higher than the power supply potential VDD level is applied to the address signal BA0 using a dedicated memory tester or the like on the user side.

  The operation timing will be described with reference to FIG. 13, but the operation in clock cycles T0 to T3 is the same as in FIG. 11, and the subsequent description will not be repeated.

  In the clock cycle T4, as in FIGS. 11 and 12, the signal TF3 changes from the H level to the L level in synchronization with the rising edge of the signal AREF. The signal TF1 and the signal TF2 remain at the H level even when the signal AREF is input.

  In clock cycle T5, as in FIGS. 11 and 12, the command received from the outside is MRS, and signal NMRS rises to the H level. In synchronization with the rise of the signal NMRS, the signals TF1 and TF2 change from the H level to the L level, and the signal TMODE falls. The operation mode is set to the normal mode in synchronization with the fall of the signal TMODE.

  As described above, the signal TF2 becomes H level when a potential equal to or higher than the power supply potential VDD is applied to the address signal BA0, and becomes L level in synchronization with the rise of the signal NMRS. Therefore, the semiconductor memory device of the present invention can open available test functions according to the user.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram of a semiconductor memory device according to a first embodiment. 3 is a schematic block diagram showing configurations of a memory circuit 2 and a normal operation control unit 3. FIG. 3 is a diagram illustrating an example of a configuration of an MRS / AREF determination unit 10. FIG. FIG. 4 is a truth table of signals representing commands input from the outside in the MRS / AREF determination unit 10. It is a figure which shows an example of a structure of the bonding pad part 9 in FIG. It is a figure which shows an example of a structure of the SVIH detection part 11 in FIG. It is a figure which shows the structural example of the test function decoding part 13 in FIG. It is a figure showing the truth table of the signal which shows the command which sets signals TF1-TF3. It is a figure which shows an example of a structure of the test mode determination part 12 in FIG. It is a figure showing the truth table of the signal with respect to the command in the test mode determination part 12. FIG. It is a figure which shows the operation | movement timing when an option pad is set to a non-connection state. It is a figure which shows the operation timing in the setting which connected the option pad. FIG. 13 is a diagram showing an operation timing when a high potential is applied to an address signal BA0 in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor memory device, 2 Memory circuit, 3 Normal operation control part, 4 Test operation control part, 5-7 Test function part, 8 Test operation instruction part, 9 Bonding pad part, 10 MRS / AREF determination part, 11 SVIH detection part , 12 test mode determination unit, 13 test function decoding unit, 201 clock buffer, 202 address buffer, 203 control signal input buffer, 204 control circuit & mode register, 205 output buffer, 206 input buffer, 304, 308, 310, 311 315 to 320, 713, 714, 723, 724, 733, 734, 801, 802 AND circuit, 305, 712, 722 NOR circuit, 306, 711, 721, 731, 732, 803 logic gate, 307, 736, 804 805 OR circuit, 301-30 3,309,312-3
14, 403 to 405, 715, 725, 735 Inverter circuit, 321, 322, 323, 717, 727, 737, 806, 807 flip-flop, 401 option pad, 402, 502 to 505 N-channel MOS transistor, 501 operational amplifier, 701 703 Test function activation unit, N1 to N14 nodes, 10 # 0 to 10 # 3 row decoder & word driver, 12 # 0 to 12 # 3 column decoder, 14 # 0 to 14 # 3 memory array bank, 16 # 0 16 # 3 sense amplifier, 18 # 0-18 # 3 preamplifier & word driver.

Claims (5)

A semiconductor memory device having a test mode and a normal mode as operation modes,
A memory circuit;
A first operation control unit that performs a read operation and a write operation on the memory circuit in the normal mode;
A second operation control unit that performs a plurality of test operations on the memory circuit in the test mode;
The second operation control unit includes:
A designation unit for holding in a non-volatile manner designation information for designating that at least one test operation among the plurality of test operations is valid or invalid;
In response to the designation information and an address signal and a command setting signal given from the outside, a test operation instruction unit that instructs each of the plurality of test operations to be valid or invalid;
A semiconductor memory device including: a test operation unit that performs the plurality of test operations on the memory circuit in response to an instruction from the test operation instruction unit; The test operation instruction unit includes:
A high voltage signal detection unit that receives an address signal indicating a specific bit of the address signal and generates a high voltage detection signal indicating that the potential of the address signal is detected to be higher than a power supply potential;
The operation mode is determined in response to the address signal and the command setting signal, and when the operation mode is a test mode, a first test function instruction according to the address signal and the command setting signal, and the address An operation mode determination unit that switches and outputs a signal, the command setting signal, and a second test function instruction according to the high voltage detection signal according to the designation information;
A test function for selecting whether to enable a general test function and a first special test function different from the general test function according to the first test function instruction and the second test function instruction, respectively. The semiconductor memory device according to claim 1, further comprising an instruction unit. The test function instruction unit
A first test function active unit that receives the first test function instruction and gives an instruction to enable the general test function;
The semiconductor memory device according to claim 2, further comprising: a second test function active unit that receives the second test function instruction and issues an instruction to enable the first special test function. The test function instruction unit
3. The third test function activation unit according to claim 2, further comprising: a third test function activation unit that instructs to cancel the second special test function when a refresh operation is instructed by the command setting signal regardless of an instruction of the designation information. Semiconductor memory device. The designation unit is:
The pad section,
Information generating means for generating the designation information according to the potential of the pad portion;
The semiconductor memory device according to claim 1.

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