JP2005259120A - Signal processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processing device capable of reducing a cache miss and reducing a data transmission time and a data transfer amount.
[Solution]
The signal processing device 1 performs a decoding process using the first table 13 and the second table 14 of the first memory area 11 and the second memory area 12 of the main memory 10. The signal processing apparatus 1 includes a cache memory 34 for temporarily storing data of the first table 13 and the second table 14, and at least one of the first memory area 11 and the second memory area 12 via the cache memory 34. A processor 20 that reads data by accessing and a control unit 51 that secures a free area in the cache memory 34 when a free area temporarily stored in the cache memory 34 is insufficient, the control unit 51 includes a first memory An empty area is secured so that the data in the area 11 is held in the cache memory 34 in preference to the data in the second memory area 12.
[Selection] Figure 1

Description

  The present invention relates to a signal processing apparatus that performs signal processing using data in first and second memory areas, and in particular, accesses the first and second memory areas via a cache memory, and stores the first and second memory areas. The present invention relates to a signal processing device that performs signal processing by reading data.

  For example, signal processing is performed such that music data is encoded into a Huffman code using, for example, a Huffman codebook (for example, 8) of the MPEG-AAC standard, and the encoded code is decoded during reproduction.

FIG. 22 shows the Huffman codebook 8 of the MPEG-AAC standard.
How Huffman decoding is performed using this code book will be described below.

  For example, it is assumed that the Huffman-encoded input bit string continues as “01110110000111111011010001111xxxx”.

  In this case, since the first 5 bits match the first entry “01110” of the table, the decoding result is “0”, which indicates that the code length is 5 bits. Furthermore, since the subsequent bits are “110000111111011010001111xxxx”, the first 6 bits match the fourth entry “110000” in the table, so the decoding result is “3”, and the code length is 6 bits. It can be seen that it is. Furthermore, since the following bits are “111111011010001111xxxx”, the first 9 bits match the third entry “111111011” from the end of the table, so the decoding result is “61” and the code length is It can be seen that it is 9 bits. Furthermore, since the subsequent bits are “010001111xxxx”, the first 4 bits match the 11th entry “0100” of the table, so the decoding result is “10” and the code length is 4 bits. It can be seen that it is. Furthermore, since the subsequent bits are “01111xxxx”, the first 5 bits match the 17th entry “01111” of the table, so the decoding result is “16” and the code length is 5 bits. It can be seen that it is.

  In this way, Huffman decoding is performed by searching each line of the Huffman codebook 8 in a brute force manner.

  However, this decoding method has a problem that it requires a very long processing time because it is necessary to search the Huffman codebook 8 many times until a matching Huffman code is found.

  For this reason, the inventors of the present application have invented an apparatus for performing Huffman decoding at high speed (see, for example, Patent Document 1).

  A conventional technique to which the present invention is applied will be described below by taking as an example a process of decoding a code encoded using the Huffman codebook 8 of the MPEG-AAC standard.

  FIG. 23 is a diagram showing two tables for performing the Huffman decoding process at high speed. In particular, FIG. 23A shows the first table 5000, and FIG. 23B shows the second table 6000.

  These first and second tables 5000 and 6000 are stored at predetermined addresses of a memory such as SRAM, and the decoder subtracts the first and second tables 5000 and 6000 based on the bit string of the Huffman code, thereby performing the decoding process. Done.

  When these two first and second tables 5000 and 6000 are used, the input bit string is decoded as follows.

  For example, when the input bit string continues as “01110110000111111011010001111xxxx” as in the previous example, the decoder first extracts the first 6 bits, and draws the first table 5000 using the 6 bits as an address. In this case, since the first table 5000 is drawn with “011101” as the address, the decoder accesses the first access point α1 shown in FIG. 23A, the code length is 5 bits, and the decoding result is “ It turns out that it is "0". Since the code length of the decoder is 5 bits, when the bit string is advanced by 5 bits, the bit string becomes “110000111111011010001111xxxx”.

  Next, the decoder extracts the first 6 bits of the bit string in the same manner as described above, and draws the first table 5000 using the extracted 6 bits as an address. In this case, since the first table 5000 is drawn with “110000” as the address, the decoder accesses the second access point α2 shown in FIG. 23A, the code length is 6 bits, and the decoding result is It turns out that it is "3". Since the code length is 6 bits, when the bit string is advanced by 6 bits, the bit string becomes “111111011010001111xxxx”.

  Further, the decoder extracts the first 6 bits of the bit string in the same manner as described above, and draws the first table 5000 using the extracted 6 bits as an address. In this case, since the first table 5000 is drawn with “111111” as the address, the third access point α3 shown in FIG. 23A is accessed, the incomplete symbol “15”, and the next address pointer “1100010”. In order to obtain the number of bits 4 to be read next, the pointer is advanced to the address “1100010” of the second table 6000 shown in FIG. 23B, and after the bit string is advanced by 6 bits, further 4 bits are obtained, The second table 6000 is subtracted using 4 bits as an index from the address “1100010”. In this case, since the 4-bit value is “0110”, the fourth access point α4 shown in FIG. 23B is accessed, so the decoder has a code length of 3 bits and decodes It can be seen that the result is “61”. Since the code length is 3 bits, when the bit string is advanced by 3 bits, the bit string becomes “010001111xxxx”.

  Next, the decoder takes out the first 6 bits of the bit string in the same manner as before, and draws the first table 5000 using the 6 bits as an address. In this case, since the first table 5000 is drawn with “010001” as the address, the decoder accesses the fifth access point α5 shown in FIG. 23A, the code length is 4 bits, and the decoding result is “ 10 ". Since the code length is 4 bits, if the bit string is advanced by 4 bits, the bit string becomes “01111xxxx”.

  Next, the decoder takes out the first 6 bits of the bit string in the same manner as before, and draws the first table 5000 using the 6 bits as an address. In this case, since the first table 5000 is drawn using “01111x” as the address, the sixth access point α6 shown in FIG. 23A is accessed, the code length is 5 bits, and the decoding result is “16”. It can be seen that it is.

  As can be seen from the above process, Huffman decoding is completed with one table access for a code with a short code length (a code with a high frequency of occurrence). Since Huffman decoding is completed with only two table accesses only for a low frequency code), high-speed signal processing can be realized on average.

The above is the conventional technique invented by the authors.
By the way, in recent years, in a computer device such as a mobile phone, not only a phone call but also an audio playback, a video playback, and a mail transmission / reception can be performed. It is illustrated.

  In order to realize such a plurality of functions, if a circuit dedicated to each function is provided for each function, the circuit scale becomes enormous. For this reason, each function is realized without dropping the response by storing data such as a table in an external memory as necessary, and storing data in the external memory in a cache memory when necessary for signal processing. It is considered.

  Such an Huffman decoding process may be performed by an arithmetic unit (signal processing unit) equipped with a cache memory. The conventional technology in this case will be described. First, the behavior of the cache memory will be briefly described.

  FIG. 24 is a diagram showing the relationship among the main memory 1000, the processor 2000, and the cache memory device 3000.

  As shown in FIG. 24, the cache memory device 3000 includes a cache memory 3100 for storing data and a control unit 3200 for replacement control.

  The cache memory 3100 manages data in units called lines. Normally, the line size is a value such as 32 bytes or 128 bytes, and the cache memory size is a value such as 16 kbytes or 32 kbytes. Therefore, the cache memory 3100 is divided by several hundred to several thousand lines. However, here, in order to simplify the description, the description will be made assuming that the lines are divided by four lines.

  The storage area of the main memory 1000 is also divided for each line size. The number line of the main memory 1000 and where it is stored in the data area 3400 of the cache memory 3100 is managed in the tag information area (tag area) 3300 in the cache memory 3100.

  FIG. 24 shows a state in which data of Line 1, Line 3, Line 6, Line 8 of the main memory 1000 is stored in the data area 3400 of the cache memory 3100 and information for identifying the line is stored in the tag area 3300. Has been.

  Therefore, the processor 2000 can access the cache memory 3100 when accessing data on the line (Line1, Line3, Line6, Line8) of the main memory 1000.

  However, for example, when accessing the Line 9 of the main memory 1000, the area is not currently stored in the cache memory 3100, and there is no empty area in the cache memory 3100, so the area is now stored in the cache memory 3100. By temporarily writing back the data of one of the lines to the main memory 1000, a free area is secured in the cache memory 3100, and the data of Line 9 is stored in the free area.

  When the above-described Huffman decoding process is performed by a signal processing apparatus equipped with such a cache memory 3100, for example, in the case of the MPEG audio AAC method, a large memory area is required. All the necessary table data is stored, and the Huffman decoding process is performed while sequentially transferring the data to the cache memory 3100.

Here, “access” means reading or writing data by designating an address.
JP 2000-286717 A

  However, when the Huffman decoding process described above is performed by a signal processing apparatus using a cache memory, the following problems occur.

  FIG. 25 is a block diagram showing a configuration of a conventional signal processing apparatus when Huffman decoding is performed using the cache memory 3100. In order to clarify the difference between the conventional signal processing apparatus and the signal processing apparatus according to the present invention, here, instead of the first and second tables 5000 and 6000, first and second tables described later are used. The case where 13 and 14 are used will be described.

  As shown in FIG. 25, the signal processing apparatus includes a main memory 1000, a processor 2000 as an access unit, and a cache memory 3100. The first table 13 is stored in the first memory area 1001 of the main memory 1000, and This is configured by storing the second table 14 in the second memory area 1002 of the memory 1000.

  The first table 13 includes eight lines (Line 0 to Line 7), and the second table 14 includes seven lines (Line 8 to Line 14). Specific contents of the first table 13 and the second table 14 are shown in FIGS. 2 and 3, respectively. The first table 13 and the second table 14 are tables in which data similar to those shown in FIGS. 23A and 23B described above in the prior art are stored. The difference is that each size is separated.

  Now, when the input bit string continues as “01110110000111111011010001111xxxx” as in the previous example, the processor 2000 first draws the first table 13 using the first 6 bits of the bit string as an address. In this case, the first table 13 is drawn with “011101” as the address, but since the address corresponds to Line 3 as shown in FIG. 2, the data of Line 3 is transferred from the main memory 1000 to the cache memory 3100 ( The processor 2000 accesses the data, and it can be seen that the code length is 5 bits and the decoding result is “0”. Since the code length is 5 bits, the processor 2000 advances the bit string by 5 bits. Then, the next bit string becomes “110000111111011010001111xxxx”.

  Next, the processor 2000 draws the first table 13 using the first 6 bits of the bit string as an address, as before. In this case, the first table 13 is drawn with “110000” as the address. Since the address corresponds to Line 6 as shown in FIG. 2, the data of Line 6 is transferred from the main memory 1000 to the cache memory 3100. (See FIG. 27.) The processor 2000 accesses the data, and it can be seen that the code length is 6 bits and the decoding result is “3”. Since the code length is 6 bits, when the bit string is advanced by 6 bits, the bit string becomes “111111011010001111xxxx”.

  Further, as before, the processor 2000 draws the first table 13 using the first 6 bits of the bit string as an address. In this case, the first table 13 is drawn with “111111” as the address. Since the address corresponds to Line 7 as shown in FIG. 2, the processor 2000 causes the data of the Line 7 to be transferred from the main memory 1000 to the cache memory 3100. After the transfer (see FIG. 28), the data is accessed, and an incomplete symbol “15”, the next address pointer “1100010”, and the number of bits to be read “4” are obtained.

  Therefore, the processor 2000 advances the pointer to the address “1100010” of the second table 14, advances the bit string by 6 bits, and then subtracts the second table 14 using the subsequent 4-bit value as an index from the address “1100010”. In this case, since the 4-bit value is “0110”, “0110” is added to the address “1100010”, and the next access address is “1101000”. That is, the processor 2000 adds “0110” to the next address pointer “1100010” to calculate the next access address “1101000”.

  Since this address corresponds to Line 13, as shown in FIG. 3, the processor 2000 accesses the data after the data of Line 13 is transferred from the main memory 1000 to the cache memory 3100 (see FIG. 29), and the code length Is 3 bits and the decoding result is “61”. Since the code length is 3 bits, if the bit string is advanced by 3 bits, the bit string becomes “010001111xxxx”.

  Next, as before, the processor 2000 draws the first table 13 using the first 6 bits of the bit string as an address. In this case, the first table 13 is drawn using “010001” as an address. Since the address corresponds to Line 2 as shown in FIG. 2, the data of Line 2 is transferred from the main memory 1000 to the cache memory 3100. Try to access the data.

  However, there is no free space in the cache memory now. When there is no necessary data in the data in which the cache memory 3100 is completely filled, that is, when a cache miss occurs, the control unit 3200 writes the data of any line stored in the cache memory 3100 to the main memory 10. It is necessary to return and transfer the data of the Line 2 to the free space generated by that.

  When such a cache miss occurs, the most recently accessed Line is usually written back. In this case, the control unit 3200 writes Line 3 back (see FIG. 30), and Line 2 data is written there. (See FIG. 31). After that, the processor 2000 accesses the data of Line 2 and finds that the code length is 4 bits and the decoding result is “10”. Since the code length is 4 bits, if the bit string is advanced by 4 bits, the bit string becomes “01111xxxx”.

  Next, as before, the processor 2000 draws the first table 13 using the first 6 bits of the bit string as an address. In this case, the first table 13 is drawn using “01111x” as an address. Since the address corresponds to Line 3 as shown in FIG. 2, the data of Line 3 is transferred from the main memory 1000 to the cache memory 3100. Try to access the data. However, since there is no free space in the cache memory now, the control unit 3200 writes back the data of any line stored in the cache memory 3100 to the main memory 1000, and the data of the Line 3 in the free space generated thereby. Move.

  When such a cache miss occurs, the most recently accessed Line is normally written back by the LRU method. In this case, the control unit 3200 writes Line 6 back (see FIG. 32), and Line 3 is written there. (See FIG. 33). Thereafter, the processor 2000 accesses the data of the Line 3 and finds that the code length is 5 bits and the decoding result is 16.

  In the above process, in the above description, the Line 3 data and the Line 6 data are written back from the cache memory 3100 to the main memory 1000. However, in this series of operations, the Line 3 data and the Line 6 data are written. Since the value does not change while being stored in the cache memory, that is, the value on the cache memory is the same as the value on the main memory 1000, many conventional cache memory control methods There is no operation of writing back, and the process of overwriting the data of Line 2 on the cache memory 3100 in which the data of Line 3 is stored, or overwriting the data of Line 3 on the cache memory in which the data of Line 6 is stored Will be done.

  However, as is clear from the above process, since the replacement target is determined by the LRU method, there is a problem of frequent cache misses. Such frequent cache misses cause multiple transfers (two times) of data such as Line 3 between the main memory 1000 and the cache memory 3100 in a short time, and it takes a lot of time to transfer the data. This causes the problem of increased power consumption.

  Such a problem is not limited to the decoding process, and the signal processing apparatus performs signal processing by accessing the first and second memory areas via the cache memory and reading the data in the first and second memory areas. This is generally true.

  The present invention has been made in view of such conventional problems, and in a signal processing device using a cache memory, it is possible to reduce cache misses and reduce data transmission time and data transfer amount. An object of the present invention is to provide a possible signal processing device.

  By the way, the inventor of the present application has analyzed the conventional technique using the cache memory. As a result, the access frequency to the first table 13 is 85% and the access frequency to the second table 14 is 15% in the decoding process. In spite of this, since the algorithm that leaves the data of the second table in the cache memory by the LRU method has been adopted in the past, the replacement algorithm (Replacement Algorithm) is found to be inappropriate and the present invention is devised. It came to.

  Therefore, in order to achieve the above object, in the signal processing device according to the present invention, the signal processing device performs signal processing using data in the first and second memory areas, and temporarily stores the data. A cache memory, access means for reading out the data by accessing at least one of the first and second memory areas via the cache memory, and when a free area temporarily stored in the cache memory is insufficient And a control means for securing a free area in the cache memory, wherein the control means is such that the data in the first memory area is held in the cache memory in preference to the data in the second memory area. The free space is secured.

  With this configuration, if the frequently accessed data is stored in the first memory area, the replacement algorithm becomes appropriate. Therefore, it is possible to provide a signal processing device that uses a cache memory to reduce cache misses and reduce data transmission time and data transfer amount.

  In the signal processing device according to the present invention, the signal processing device further includes attribute storage means for storing an intensity attribute indicating that the first memory area is stronger than the second memory area, The control means may determine data to be held in the cache memory according to the strength attribute stored in the attribute storage means.

  With this configuration, the replacement algorithm is surely appropriate, and the data area of the cache memory allocated to the data in the second memory area can be minimized.

  In the signal processing device according to the present invention, the access means accesses the first memory area after transferring the data in the first memory area to the cache memory, and accesses the second memory area. The data in the second memory area may be accessed without being transferred to the cache memory.

  With this configuration, the replacement algorithm is surely appropriate, the cache memory data area allocated to the data in the second memory area can be eliminated, and the entire cache memory data area can be allocated to the data in the first memory area. .

  In the signal processing device according to the present invention, the first memory area stores data having a higher access frequency than the second memory area.

This configuration ensures that the replacement algorithm is appropriate.
In the signal processing device according to the present invention, the first and second memory areas hold first and second tables indicating conversion rules for converting input data according to a predetermined rule, respectively, and the control The means may secure the free area so that the data of the second table is discarded from the cache memory in preference to the data of the first table.

  With this configuration, if the first table with high access frequency is stored in the first memory area, the replacement algorithm is appropriate. Therefore, in a signal processing device using a cache memory, it is possible to provide a signal processing device that converts input data according to a certain rule while reducing cache misses and reducing data transmission time and data transfer amount. .

  In the signal processing device according to the present invention, the signal processing device further includes attribute storage means for storing an intensity attribute indicating that the first table is stronger than the second table, and the control means May determine the data to be discarded from the cache memory according to the strength attribute stored in the attribute storage means.

  With this configuration, if the first table with high access frequency is stored in the first memory area, the replacement algorithm is surely appropriate, and the cache memory data area allocated to the data in the second memory area is minimized. Can be

  Further, in the signal processing device according to the present invention, the signal processing device is a device that decodes a Huffman code that is input data, and the Huffman code has a longest code length of N bits, The table is a table for decoding code data of n bits or less when n is an integer of 1 to less than N, and the second table is for decoding code data longer than the n bits. It can also be characterized by being a table.

  With this configuration, since the first table for decoding a short Huffman code having a high code frequency is stored in the first memory area, the replacement algorithm is surely appropriate and assigned to the data in the second memory area. The data area of the cache memory can be minimized.

  Note that the present invention can be realized not only as such a signal processing device but also as a signal processing method using steps characteristic of the signal processing device as a step. It can also be realized as a program to be executed. Needless to say, such a program can be distributed via a recording medium such as a CD-ROM or a transmission medium such as the Internet.

  As is clear from the above description, according to the signal processing device according to the present invention, if the frequently accessed data is stored in the first memory area, the replacement algorithm becomes appropriate. In the signal processing device, it is possible to provide a signal processing device in which cache misses are reduced and data transmission time and data transfer amount are reduced.

  Therefore, according to the present invention, signal processing with fewer cache misses and reduced data transmission time and data transfer amount is possible, and the practical value of the present invention in the present day when computer devices such as multifunctional mobile phones have become widespread. Extremely expensive.

Hereinafter, a signal processing device according to an embodiment of the present invention will be described with reference to the drawings.
<Overall configuration>
(Embodiment 1)
FIG. 1 is a block diagram showing an overall configuration of a signal processing device 1 according to Embodiment 1 of the present invention. FIG. 1 illustrates a case where the signal processing apparatus 1 functions as a decoder that decodes a bit string encoded in a Huffman code using the MPEG-AAC standard Huffman codebook (for example, 8) in FIG. Yes.

  As shown in FIG. 1, the signal processing device 1 includes a main memory 10, a processor 20 as an access means, a cache memory device 30 and the like.

  The main memory 10 is composed of a DRAM or the like, and the first table 13 for one stage for decoding in the first memory area 11 in one stage and 2 for decoding in the second area 12 in two stages. A second stage table 14 is stored for each.

  The cache memory device 30 is configured by an SRAM or the like, and stores a tag area, a data area, a weak flag W indicating an attribute having a high probability of remaining in the data area, a dirty flag D indicating the necessity of writing back, and the like. A cache memory 34 that performs replacement control, a control unit 51 that performs replacement control, an attribute storage unit 52 that stores data (attribute data) for setting the probability of remaining in the cache memory 34, and the like, and is accessed by a so-called LRU method. Assuming replacement control that replaces cache entries that are out of order, data with low access frequency is retained by modifying the order data indicating the access order for determining the replacement target against the access order. Cache entry from cache memory for replacement It is configured to begin to have. Specifically, the order data is indirectly modified by adding a weak flag W indicating that the access order is considered to be the oldest to the cache entry. This eliminates the need for a complicated circuit for directly modifying the order data.

  When starting the decoding process, the processor 20 writes the first table 13 in the first memory area 11 of the main memory 10 and the second table 14 in the second memory area 12, or sets predetermined attribute value setting data. Based on this, an intensity attribute is set in the attribute storage unit 52. Then, the processor 20 acquires the decoding result by accessing the cache memory using the Huffman code string to be decoded as an address.

  FIG. 2 is a diagram showing the configuration of the first table 13, and FIG. 3 is a diagram showing the configuration of the second table 14.

  The first table 13 and the second table 14 show conversion rules for converting the input data according to a certain rule. Specifically, the first table 13 and the second table 14 correspond to the Huffman codebook used for encoding, Maps to the memory area 11 and the second memory area 12, respectively.

  The first table 13 is a table for decoding a relatively short code length Huffman code having a bit number equal to or less than a predetermined number (6 bits), which can be included in the predetermined bit number data read from the bit stream, into a decoding result. is there. The second table 14 is calculated based on the address pointer acquired by the first table 13 when decoding is not completed with a short Huffman code and the bit length Huffman code indicated by the next acquisition point. 3 is a table for decoding a Huffman code having a relatively long code length having a number of bits exceeding a predetermined number. As described above, the relatively short Huffman code and the relatively long Huffman code are decoded by the processing using the first table 13 and the second table 14.

  As shown in FIG. 2, the first table 13 includes a column in which data of a code length or an incomplete symbol (here, “15”) is stored, and a column in which data of a decoding result or a next address is stored. And a field for storing data of the next acquisition length. Note that, on the left side of the first table 13, for convenience of explanation, addresses and lines where these data are stored are shown.

  As shown in FIG. 3, the second table 14 includes a column for storing code-length data and a column for storing decoding result data. On the left side of the second table 14, for the convenience of explanation, the next index data for obtaining an address, an address where these data are stored, and a line are shown.

  In Huffman encoding, a shorter Huffman code is generally assigned to an input value having a higher appearance frequency, and a longer Huffman code is assigned to an input value having a lower appearance frequency. Therefore, in the decoding process, the first table 13 has a higher access frequency than the second table 14.

FIG. 4 is a diagram illustrating an example of the contents of attribute data stored in the attribute storage unit 52.
In this case, the strength of Line 0 to Line 7 corresponding to the first table 13 is high (the weak flag W is “0”), and the strength of Line 8 to Line 14 corresponding to the second table 14 is low (the weak flag W is “1”). It is shown. By setting such a strength attribute, an appropriate replacement algorithm is exhibited and cache misses are reduced.
<Specific Configuration of Cache Memory Device>
FIG. 5 is a block diagram illustrating a specific configuration example of the cache memory device 30. Here, as a specific example of the cache memory device 30, a configuration when the present invention is applied to a 4-way set associative cache memory will be described.

  As shown in FIG. 5, the cache memory device 30 includes an address register 31, a memory I / F 32, a decoder 33, four ways 34a to 34d (hereinafter also abbreviated as “way 0 to 3”), four comparators. 35a to 35d, four AND circuits 36a to 36d, a selector 38, a selector 39, a demultiplexer 41, and a cache control unit 42. The cache control unit 42 includes a replacement unit 42a and a W flag setting unit 42b.

  In the specific example of the cache memory device 30, the replacement unit 42a corresponds to the control unit 51 in FIG. 1, and the W flag setting unit 42b corresponds to the attribute storage unit 52 in FIG.

  The address register 31 is a register that holds an access address to the main memory 10. This access address is assumed to be 32 bits. As shown in FIG. 5, the access address includes a 21-bit tag address, a 4-bit set index (SI in FIG. 5), a 5-bit word index (WI in FIG. 5) in order from the most significant bit. Including. Here, the tag address indicates an area in the memory that is mapped to the way (its size is the number of sets × block). The size of this area is a size determined by address bits (A10 to A0) lower than the tag address, that is, 2k bytes, and is also the size of one way. The set index (SI) indicates one of a plurality of sets extending over the ways 0 to 3. There are 16 sets of sets because the set index is 4 bits. The cache entry specified by the tag address and the set index is a replacement unit, and is called line data or a line when stored in the cache memory. The size of the line data is a size determined by address bits lower than the set index, that is, 128 bytes. If one word is 4 bytes, one line data is 32 words. The word index (WI) indicates one word among a plurality of words constituting the line data. The least significant 2 bits (A1, A0) in the address register 31 are ignored during word access.

  The memory I / F 32 is used for accessing the main memory 10 from the cache memory device 30 such as loading data from the main memory 10 to the cache memory device 30 and writing back data from the cache memory device 30 to the main memory 10. I / F.

  The decoder 33 decodes the 4 bits of the set index and selects one of the 16 sets across the four ways 0 to 3.

  The four ways 0 to 3 are four ways having the same configuration and have a capacity of 4 × 2 kbytes. Each way has 16 cache entries.

  FIG. 6 is a diagram showing a detailed bit configuration in one cache entry shown in FIG.

  As shown in FIG. 6, one cache entry has valid flags V0 to V3, a 21-bit tag, 128-byte line data, a weak flag W, and dirty flags D0 to D3.

A tag is a copy of a 21-bit tag address.
The line data is a copy of 128-byte data in the block specified by the tag address and the set index, and consists of four 32-byte sub-lines.

  Valid flags V0 to V3 correspond to four sublines and indicate whether or not the sublines are valid.

  The weak flag W is a flag for regarding that the access order of the cache entry is the oldest. That is, when W = 1, it means that the processor 20 does not read or write any more to the cache entry, or the access frequency is low. Further, when W = 1, the cache memory device 30 means that the access order is the oldest regarding the replacement control, that is, the weakest (week) cache entry. When W = 0, it means not.

  Dirty flags D0 to D3 correspond to four sublines and indicate whether or not the processor 20 has written to the sublines. That is, the cached data exists in the sub-line, but it is different from the data in the main memory 10 by writing, and therefore it is shown whether it is necessary to write back to the main memory 10.

  The comparator 35a compares whether or not the tag address in the address register 31 matches the tag of the way 0 among the four tags included in the set selected by the set index. The comparators 35b to 35c are the same except that they correspond to the ways 34b to 34d.

  The AND circuit 36a compares whether or not the valid flag matches the comparison result of the comparator 35a. When the comparison result is “1”, it means that there is line data corresponding to the tag address and the set index in the address register 31, that is, a hit in way 0. If the comparison result is “0”, it means that a cache miss has occurred. The AND circuits 36b to 36d are the same except that they correspond to the ways 34b to 34d. The comparison result indicates whether the way 1 to 3 hit or a cache miss.

  The selector 38 selects the line data of the hit way among the line data of the ways 0 to 3 in the selected set.

  The selector 39 selects one word indicated by the word index from the 32-word line data selected by the selector 38.

  The demultiplexer 41 outputs write data to one of the ways 0 to 3 when writing data to the cache entry. This write data may be in units of words.

  The cache control unit 42 performs overall control of the cache memory device 30. In particular, setting of the W flag and replacement control according to the W flag are performed.

FIG. 7 is a block diagram illustrating a configuration of the cache control unit 42.
As described above, the cache control unit 42 includes the replacement unit 42a corresponding to the control unit 51 of FIG. 1 and the W flag setting unit 42b corresponding to the attribute storage unit 52 of FIG.

  In the case of replacement due to a cache miss, if there is a cache entry for which W = 1 is set, the replacement unit 42a considers that the access order of the cache entry is the oldest, selects it as a replacement target, and performs replacement.

  The W flag setting unit 42 b sets a weak flag W in accordance with a command from the processor 20. The processor 20 issues a command to the cache memory device 30 to instruct the setting of the weak flag W for a cache entry that is no longer being written or read.

FIG. 8 is a block diagram illustrating a configuration example of the W flag setting unit 42b.
As shown in FIG. 8, the W flag setting unit 42b includes a command register 421, a start address register 422, a size register 423, a start aligner 424, an adder 425, an end aligner 426, and a flag rewriting unit 427.

  The command register 421 is a register that is directly accessible from the processor 20 and holds the W flag setting command written by the processor 20.

FIG. 9A shows an example of an instruction for writing a command to the command register 421.
This instruction is a normal transfer instruction (mov instruction), and designates a command as a source operand and a command register (CR) as a destination operand.

  FIG. 9B shows an example of the command. This command is a specific code indicating a W flag setting command. The W flag setting command instructs the cache entry that sets data corresponding to the address range of the size held in the size register 423 from the start address held in the start address register 422 to set the W flag. It is a command.

  The start address register 422 is a register that is directly accessible from the processor 20 and holds the start address written by the processor 20. This start address indicates the start position of the address range in which the W flag is to be set.

  FIG. 9C shows an example of an instruction for writing a start address in the start address register 422. This instruction is also a normal transfer instruction (mov instruction) as in FIG.

  The size register 423 is a register that is directly accessible from the processor 20 and holds the size written by the processor 20. This size indicates an address range from the start address.

  FIG. 9D shows an example of an instruction for writing a size in the size register 423. This instruction is also a normal transfer instruction (mov instruction) as in FIG. The unit of size may be the number of bytes or the number of lines (number of cache entries), and may be a predetermined unit.

  The start aligner 424 adjusts the start address to the position of the line boundary. By this adjustment, the processor 20 can designate an arbitrary address as the start address regardless of the line size and the line boundary.

  The adder 425 adds the start address held in the start address register 422 and the size held in the size register 423. The addition result is an end address indicating the end position of the address range. The adder 425 may add as a byte address when the size designates the number of bytes, and add as a line address when the size designates the number of lines.

  The end aligner 426 adjusts the end address to the position of the line boundary. By this adjustment, the processor 20 can designate an arbitrary size as the size regardless of the line size and the line boundary.

FIG. 10 is an explanatory diagram of the start aligner 424 and the end aligner 426.
In FIG. 10, the start address designated by the processor 20 indicates an arbitrary position in the middle of the line N. The start aligner 424 adjusts to indicate the head of the next line (N + 1), and outputs the adjusted address as the align start address. The line indicated by the align start address is called the start line.

  The end address indicates an arbitrary position in the middle of the line M. The end aligner 426 adjusts to indicate the head of the immediately preceding line (M-1), and outputs the adjusted address as the align end address. The line indicated by the align end address is called an end line.

  In this case, the W flag is set in each line (cache entry) from the start line (line (N + 1)) to the end line (line (M-1)). As described above, the start aligner 424 and the end aligner 426 are aligned on the inner side of the address range from the start address to the end address specified by the processor 20. This is because there is a possibility of reading or writing from 20.

If the flag rewriting unit 427 is entered in the cache memory device 30 from the line indicated by the align start address to the line indicated by the align end address (from the line (N + 1) to the line (M−1) in the example of FIG. 10). Set the W flag to 1.
<W flag setting process>
FIG. 11 is a flowchart illustrating an example of the W flag setting process in the flag rewriting unit 427.

  When the W flag setting command is held in the command register 421, the flag rewriting unit 427 performs loop 1 processing (S82 to S86) while sequentially outputting each line address from the start line to the end line. Since the flag rewriting unit 427 performs the same process for each line, the process for one line will be described here.

  That is, the flag rewriting unit 427 outputs the line address to the address register 31 while the cache memory device 30 is not accessed from the processor 20 (S83), and compares the tag address of the address register 31 with the tag of the cache entry. The devices 35a to 35d are compared to determine whether or not they hit (S84). Further, the flag rewriting unit 427 sets the W flag to 1 for the hit cache entry when it hits (S85), and if there is a cache miss, it is not entered in the cache memory. do not do.

Thus, if each line from the start line to the end line is entered in the cache memory device 30, the W flag is set to “1”.
<Replace processing>
FIG. 12 is a flowchart showing the replacement process in the replacement unit 42a.

  In FIG. 12, when the memory access causes a cache miss (S91), the replacement unit 42a reads the 4-way weak flag W in the set selected by the set index (S92), and the logical sum of the four weak flags is It is determined whether or not 1, that is, whether there is a way of W = 1 (S93). If it is determined that there is a way with W = 1, the access order of the cache entry is regarded as the oldest, and one way with W = 1 is selected (S94), and it is determined that there is no way with W = 1. If one of the ways is selected, one way is selected by the normal LRU method (S95). At this time, if there are a plurality of ways having the weak flag W set to 1, the replacement unit 42a randomly selects one.

  Further, the replacement unit 42a replaces the cache entry of the selected way in the set (S96), and initializes the weak flag W of the cache entry after replacement (S97). At this time, the valid flag V and the dirty flag D are initialized to 1 and 0, respectively.

  As described above, when there is no way of W = 1, the replacement target is selected by the normal LRU method. When there is a way of W = 1, the replacement target is treated as the oldest access order of the way of W = 1, and as a result, the cache entry of the way of W = 1 is selected. As a result, it is possible to reduce cache misses caused by the fact that W = 1 data with low access frequency exists in the cache memory.

  As described above, according to the cache memory of the first embodiment, the line with the weak flag W = 1 is a line on which no further reading or writing is performed from the processor, and the access order is treated as the oldest. As a result, it is selected as the replacement target first. As a result, it is possible to reduce the occurrence of a cache miss due to data with low access frequency.

  In addition, since the access order is modified by adding the W flag indirectly without directly modifying the order data indicating the access order in the conventional LRU method, without adding a complicated hardware circuit, Can be realized.

Next, operations performed by each unit of the signal processing device 1 will be described.
13 to 19 are diagrams showing the flow of data stored in the cache memory 34.

  In the first embodiment, a signal processing apparatus 1 that decodes a code encoded using the Huffman codebook 8 of the MPEG-AAC standard in FIG. 22 will be described as an example.

  In order to clarify the difference in operation with the conventional signal processing apparatus, only four sets of one way of the cache memory 34 are used. It will be described as continuing.

  As shown in FIG. 13, the processor 20 first draws the first table 13 using the first 6 bits “011101” of the bit string as an address. In this case, since the address “011101” corresponds to Line 3 (see FIG. 2), after the data in Line 3 is transferred from the main memory 10 to the cache memory 34, the data at the address “011101” is accessed and the code length is 5 bits. Then, the decoding result “0” is acquired.

  More specifically, the processor 20 outputs a read signal to the cache memory device 30 using the first 6 bits “011101” of the bit string as an address. The cache memory device 30 that has received the read signal whose address is “011101” does not have Line 3 data in the cache memory 34. Write to one set. Line 3 is written in the tag, “0” is written in the W flag, and “0” is written in the dirty flag D. When these writings are completed, the cache memory device 30 outputs the data of the address “011101”, the code length of 5 bits, and the decoding result “0” to the processor 20.

  When the code length of 5 bits and the decoding result “0” are acquired, the processor 20 performs the subsequent signal processing (such as inverse quantization processing, IMDCT (Inverse Modified Discrete Cosine Transform) processing), and the like. After the “0” is output to the buffer or the like, since the code length is 5 bits, the bit string is advanced by 5 bits. That is, the acquisition point P is moved by 5 bits. Then, the next bit string becomes “110000111111011010001111xxxx”.

  When the next bit string is “110000111111011010001111xxxx”, as shown in FIG. 14, the processor 20 draws the first table 13 using the first 6 bits “110000” of the bit string as an address, as described above. In this case, since the address “110000” corresponds to Line 6 (see FIG. 2), after the data of Line 6 is transferred from the main memory 10 to the cache memory 34 (FIG. 14), the data at the address “110000” is accessed. The code length of 6 bits and the decoding result “3” are acquired.

  Note that Line 6 is written in the tag, “0” is written in the W flag, and “0” is written in the dirty flag D.

  Then, after outputting the decoding result “3”, the processor 20 advances the bit string by 6 bits because the code length is 6 bits. That is, the acquisition point P is moved by 6 bits. Since the code length is 6 bits, when the bit string is advanced by 6 bits, the next bit string is “111111011010001111xxxx”.

  When the next bit string is “111111011010001111xxxx”, as shown in FIG. 15, the processor 20 draws the first table 13 using the first 6 bits “111111” of the bit string as an address, as described above. In this case, since the address “111111” corresponds to the Line 7 (see FIG. 2), after the data of the Line 7 is transferred from the main memory 10 to the cache memory 34, the data at the address “111111” is accessed, and the incomplete symbol “15”, the next address pointer “1100010”, and the number of bits to be read “4” are acquired.

  Note that Line 7 is written in the tag, “0” is written in the W flag, and “0” is written in the dirty flag D. Here, since the data acquisition operation of the cache memory device 30 is the same as that described above, the description thereof is omitted below.

  Therefore, the pointer is advanced to the address “1100010” of the second table 14 shown in FIG. 3, the bit string is advanced by 6 bits, and the subsequent 4-bit value is used as an index from the address “1100010”. Pull. In this case, since the 4-bit value is “0110”, “0110” is added to the address “1100010”, and the next access address is “1101000”.

  That is, as shown in FIG. 16, the processor 20 acquires the next 4 bits “0110”, adds the next 4 bits “0110” to the previously acquired address “1100010”, and then accesses the next address. "1101000" is calculated.

  When the calculation is completed, the processor 20 draws the second table 14 using “1101000” obtained by the calculation as an address. Since this address “1101000” corresponds to the Line 13 (see FIG. 3), after the data of the Line 13 is transferred from the main memory 10 to the cache memory 34, the processor 20 accesses the data, the code length is 3 bits, and the decoding result “61” is acquired.

  Note that Line 13 is written in the tag, “1” is written in the W flag, and “0” is written in the dirty flag D.

  Then, after outputting the decoding result “61”, the processor 20 advances the bit string by 3 bits because the code length is 3 bits. That is, the acquisition point P is moved 6 + 3 = 9 bits. When the acquisition point P is moved, the next bit string becomes “010001111xxxx”.

  When the next bit string is “010001111xxxx”, as shown in FIG. 17, the processor 20 draws the first table 13 using the first 6 bits “010001” of the bit string as an address, as described above. In this case, since the address “010001” corresponds to Line 2 (see FIG. 2), it is necessary to access the data after moving the data of Line 2 from the main memory 10 to the cache memory 34.

  Now, since there is no free area in the cache memory 34, it is necessary to write back the data of any line stored in the cache memory 34 to the main memory 10 and move the data of the Line 2 to the free area generated thereby. There is.

  Here, the control unit 51 is one of those stored in the cache memory 34 based on the strength information of the first memory area 11 and the second memory area 12 of the main memory 10 specified by the attribute storage unit 52. It is determined whether to write back the data of this line back to the main memory 10. In this case, it is indicated that Line 0 to Line 7 corresponding to the first table 13 have a high strength, and Line 8 to Line 14 corresponding to the second table 14 have a low strength (see FIG. 4). Therefore, the data currently stored in the cache memory 34 as the data of the second table 14 is written back to the main memory 10. That is, since the data of Line 13 is currently stored in the cache memory 34, this data is written back to the main memory 10 (FIG. 17), and the data of Line 2 is moved to the free space generated thereby (FIG. 18).

  After that, the processor 20 accesses the data of the Line 2 and acquires the decoding result 10 with a code length of 4 bits. Since the code length is 4 bits, if the bit string is advanced by 4 bits, the bit string becomes “01111xxxx”.

  In this process, in the above description, it is assumed that the data of Line 13 is written back from the cache memory 34 to the main memory 10. However, in the process of this series of operations, the data of Line 13 is stored in the cache memory 34. Since the value has not changed, that is, the value on the cache memory 34 and the value on the main memory 10 are the same, many conventional cache memory control methods do not have an operation of rewriting, and Line 2 Is overwritten on the data of Line13.

  That is, when there is no free space in the cache memory 34, conventionally, the data of Line 3 is determined as a replacement target by the LRU method, and the data of Line 2 is overwritten on the line. On the other hand, the control unit 51 of the first embodiment searches for a line in which the weak flag W of the cache memory 34 is set to “1”, and determines the data of Line 13 as a replacement target. Then, the control unit 51 confirms that the value of the dirty flag D of Line 13 remains “0”, and overwrites the data of Line 2 on the line.

  As a result, since frequently accessed data remains in the cache memory 34, the probability of hits increases and the probability of occurrence of cache misses decreases.

  When the next bit string is “01111xxxx”, the processor 20 draws the first table 13 using the first 6 bits of the bit string as an address, as described above. In this case, the address “01111x” corresponds to Line 3 (see FIG. 2). Now, since the data of Line 3 is stored in the cache memory 34, it hits and the processor 20 immediately accesses the data of the address “01111x”, and immediately acquires the decoding result 16 of 5 bits in code length.

  In this process, in the conventional technique described above, when there is no free space in the cache memory 34, the most recently accessed Line is usually written back, so the data in Line 3 is stored in the main memory 10 a plurality of times. And the cache memory 34 are repeatedly moved, but the frequently accessed data is preferentially cached by the functions of the control unit 51 (replacement unit 42a) and the attribute storage unit 52 (W flag setting unit 42b). As a result, the number of times of data movement between the main memory 10 and the cache memory 34 can be reduced.

  As described above, according to the first embodiment, the first memory area 11, the second memory area 12 of the main memory 10, the cache memory 34 for temporarily storing data in the memory areas 11 and 12, A processor 20 for accessing the first and second memory areas 11 and 12 via the cache memory 34 and a control unit 51 for securing a free area when the cache memory 34 runs out of free area are used. Thus, the control unit 51 secures a free area while preferentially holding the data (first table 13) of the first memory area 11 in the cache memory 34, so that the main memory 10 And the number of transfers between the cache memory 34 and the cache memory 34 can be reduced.

  In the Huffman decoding process according to the present embodiment, the decoding is completed by accessing the first memory area 11 once, or the second memory area 12 is accessed after the first memory area 11 is accessed once. Although the process has been described in which the decoding is completed by two accesses, i.e., decoding is completed by accessing once in the above, it is not always necessary.

  For example, as shown in Japanese Patent Laid-Open No. 2000-286717 (Embodiment 1), decoding is completed by accessing the memory once, or if not, the memory is accessed one or more times more than once. In this case, the decoding may be completed. In this case, for example, a memory area that may be accessed for the first time is assigned to the first memory area 11 in the present embodiment, and a memory area that may be accessed for the second time or later is assigned to the main memory area. What is necessary is just to allocate to the 2nd memory area 12 as used in the embodiment.

  Alternatively, when m is a relatively small integer, a memory area that may be accessed by the mth time is assigned to the first memory area 11 in the present embodiment, and accessed after the mth time. There is also a method of allocating a possible memory area to the second memory area 12 in this embodiment.

  Also in this case, the main memory 10 and the cache memory 34 are secured by securing a free area while preferentially holding the data (first table 5000) in the first memory area 11 in the cache memory 34. Thus, the number of transfers to and from can be greatly reduced as compared with the prior art.

(Embodiment 2)
Next, the signal processing device 2 according to Embodiment 2 of the present invention will be described.

  By the way, in the signal processing apparatus 1 according to the first embodiment, the control unit 51 is provided so that data with low access frequency does not remain in the cache memory. That is, in the signal processing device 1, the data in the second table 14 is temporarily stored in the cache memory 34, and when there is no free space, the data in the second table 14 is targeted for replacement.

  However, if it does so, the probability that the data of the 1st table 13 will exist in the cache memory 34 will become low. That is, the allocation area for the data of the first table 13 is reduced.

  Therefore, control is performed so that data with low access frequency is not stored in the cache memory.

In that case, the configuration is as shown in FIG.
That is, as shown in FIG. 20, the signal processing device 2 accesses the main memory 10 via the main memory 10, the processor 20, the function of accessing the main memory 10 via the cache memory, and the cache memory. A cache memory device 60 having a function to store the first table 13 stored in the first memory area 11 of the main memory 10 and accessed via the cache memory, and the second memory area 12 of the main memory 10. The second table 14 is stored and accessed without going through the cache memory.

  The cache memory device 60 includes a cache memory 61, a control unit 62, an access control unit 63, an attribute storage unit 64, and the like.

  The cache memory 61 has a configuration in which the weak flag W is deleted from the cache memory 34.

The control unit 62 determines a replacement target by a normal LRU method.
The attribute storage unit 64 stores strength attribute data based on a command for setting an attribute output from the processor 20.

FIG. 21 is a diagram illustrating an example of the contents of attribute data stored in the attribute storage unit 64.
In this case, it is indicated that Line 0 to Line 7 corresponding to the first table 13 have a high strength (cache), and Line 8 to Line 14 corresponding to the second table 14 have a low strength (non-cache). By setting such a strength attribute, an appropriate replacement algorithm is exhibited and cache misses are reduced.

  The access control unit 63 determines whether to access via the cache memory 61 or to access the second table 14 based on the data stored in the attribute storage unit 64. Specifically, when the address accessed by the processor 20 is in the range of Line 0 to Line 7, the access control unit 63 enables the cache memory 61 and mediates reading of the data of Line 0 to Line 7 via the cache memory 61. To do. When the address accessed by the processor 20 is in the range of Line 8 to Line 14, the access control unit 63 disables the cache memory 61 and stores the second table 14 stored in the second memory area 12 of the main memory 10. The data at the corresponding address is directly accessed, and the read data is output to the processor 20.

  With such a configuration, the processor 20 can access the first table 13 through the cache memory 61 and can access the second table 14 without going through the cache memory 61. The data of the second table 14 with low access frequency can be prevented from being stored in the cache memory 61.

As a result, once the frequently accessed data in the first table 13 is stored in the cache memory, it is more likely to be held as it is, and as a result, the number of transfers between the main memory 10 and the cache memory 61 can be reduced. Become.
<Modification>
The cache memory of the present invention is not limited to the configuration of the first embodiment, and various modifications can be made. Hereinafter, some modified examples will be described.

  (1) In the first embodiment, the weak flag W indicates that the access order is the oldest, but the access order may indicate that the access order is the latest or not the oldest. In this case, the replacement unit 42a may consider that the cache entry with W = 1 is not the oldest and select another cache entry without selecting it as a replacement target. By adding a weak flag W indicating that it is not the oldest to a cache entry that holds data having a high access frequency or data having a medium access frequency, it is possible to prevent unnecessary replacement.

  (2) The processor 20 executes a special store instruction that instructs the setting of the weak flag W = 1 and the writing of data, and the cache control unit 42 further includes an instruction detection unit that detects the special store instruction; It is good also as a structure provided with the flag setting part which sets W = 1 at the time of the write by the said store instruction.

  (3) In the first embodiment, a 4-way set associative cache memory has been described as an example. However, the number of ways may be any number. In the first embodiment, an example in which the number of sets is 16 has been described. However, any number of sets may be used.

  (4) In the first embodiment, a set-associative cache memory has been described as an example. However, a full-associative cache memory may be used.

  (5) In the first embodiment, the size of the sub-line is set to 1/4 of the size of the line, but other sizes such as 1/2, 1/8, and 1/16 may be used. In that case, each cache entry may hold the same number of valid flags and dirty flags as sublines.

  (6) In the above embodiment, the case where the encoded data of music data is decoded using a table corresponding to, for example, the Huffman codebook (for example, 8) of the MPEG-AAC standard has been described. This can be applied when decoding using a table corresponding to. Also, the present invention can be applied when decoding encoded data such as MP3. Furthermore, it goes without saying that the present invention can be applied to various signal processes such as decoding compressed and encoded video data.

  The signal processing device according to the present invention has the effect of reducing cache misses and reducing the time and amount of data transfer between the cache memory and the main memory, and is composed of a device composed of a processor and a storage device, for example, a personal computer Useful in computers and the like. Further, the present invention can be applied to devices such as digital televisions, DVD devices, mobile phones, portable information terminals, and headphone stereos that process digitized audio signals and video signals by a processor and a storage device.

It is a figure which shows the structure of the signal processing apparatus 1 which concerns on Embodiment 1 of this invention. 5 is a diagram showing an example of the contents of a first table 13. FIG. It is the figure which showed an example of the content of the 2nd table. It is the figure which showed an example of the data content which the attribute storage part 52 stores. FIG. 2 is a block diagram illustrating a configuration example of a cache memory device 30 illustrated in FIG. 1. The detailed bit structure of a cache entry is shown. 3 is a block diagram showing a configuration of a cache control unit 42. FIG. It is a block diagram which shows the structural example of a W flag setting part. (A) It is a figure which shows an example of the command which writes a command in a command register. (B) It is a figure which shows an example of a command. (C) It is a figure which shows an example of the command which writes a start address in a start address register. (D) It is a figure which shows an example of the command which writes size in a size register. It is a figure which shows explanatory drawing of a start aligner and an end aligner. It is a flowchart which shows the W flag setting process in a flag rewriting part. It is a flowchart which shows the replacement process in a replacement part. It is the figure which showed the flow of the data stored in a cache memory. It is the figure which showed the flow of the data stored in a cache memory. It is the figure which showed the flow of the data stored in a cache memory. It is the figure which showed the flow of the data stored in a cache memory. It is the figure which showed the flow of the data stored in a cache memory. It is the figure which showed the flow of the data stored in a cache memory. It is the figure which showed the flow of the data stored in a cache memory. It is a block diagram which shows the structure of the signal processing apparatus 2 which concerns on Embodiment 2 of this invention. It is the figure which showed an example of the content of the attribute data which the attribute storage part 64 stores. It is a figure which shows the Huffman codebook 8 of an MPEG-AAC standard. (A) It is a figure which shows the 1st table 5000 for performing a Huffman decoding process at high speed. (B) It is a figure which shows the 2nd table 6000 for performing a Huffman decoding process at high speed. It is the figure which showed the relationship between a cache memory, main memory, and a processor. It is a block diagram in the case of performing Huffman decoding using a conventional cache memory. It is the figure which showed the flow of the data stored in a cache memory by the prior art. It is the figure which showed the flow of the data stored in a cache memory by the prior art. It is the figure which showed the flow of the data stored in a cache memory by the prior art. It is the figure which showed the flow of the data stored in a cache memory by the prior art. It is the figure which showed the flow of the data stored in a cache memory by the prior art. It is the figure which showed the flow of the data stored in a cache memory by the prior art. It is the figure which showed the flow of the data stored in a cache memory by the prior art. It is the figure which showed the flow of the data stored in a cache memory by the prior art.

Explanation of symbols

10 main memory 11 first memory area 12 second memory area 13 first table 14 second table 20 processor 30, 60 cache memory device 34, 61 cache memory 51, 62 control unit 52, 64 attribute storage unit

Claims (9)

A signal processing device that performs signal processing using data in first and second memory areas,
A cache memory for temporarily storing the data;
Access means for reading the data by accessing at least one of the first and second memory areas via the cache memory;
Control means for securing free space in the cache memory when there is a shortage of free space to be temporarily stored in the cache memory;
The signal processing apparatus, wherein the control means reserves the free area so that the data in the first memory area is held in the cache memory in preference to the data in the second memory area. The signal processing apparatus further includes attribute storage means for storing an intensity attribute indicating that the first memory area is stronger than the second memory area,
The signal processing apparatus according to claim 1, wherein the control unit determines data to be held in the cache memory according to an intensity attribute stored in the attribute storage unit. The access means accesses the first memory area after transferring the data in the first memory area to the cache memory, and accesses the data in the second memory area for the second memory area. The signal processing apparatus according to claim 1, wherein the signal processing apparatus is accessed without moving to the process. The signal processing apparatus according to claim 1, wherein the first memory area stores data having a higher access frequency than the second memory area. The first and second memory areas respectively hold first and second tables indicating conversion rules for converting input data according to a certain rule,
2. The signal according to claim 1, wherein the control unit reserves the free space so that the data in the second table is discarded from the cache memory in preference to the data in the first table. Processing equipment. The signal processing device further includes attribute storage means for storing an intensity attribute indicating that the first table is stronger than the second table,
The signal processing apparatus according to claim 5, wherein the control unit determines data to be discarded from the cache memory according to an intensity attribute stored in the attribute storage unit. The signal processing device is a device for decoding a Huffman code that is input data,
In the Huffman code, the longest bit of the code length is N bits,
The first table is a table for decoding code data of n bits or less when n is an integer greater than or equal to 1 and less than N;
The signal processing apparatus according to claim 5, wherein the second table is a table for decoding code data longer than the n bits. A cache comprising first and second memory areas, a cache memory for temporarily storing the data, and access means for reading the data by accessing the first and second memory areas via the cache memory A control method for a memory device, comprising:
The free space is secured so that the data in the first memory area is held in the cache memory in preference to the data in the second memory area when there is a shortage of free space to be temporarily stored in the cache memory. A cache memory control method comprising the steps of: A program for a signal processing device that performs signal processing using data in first and second memory areas,
A program for causing a computer to execute the steps included in the control method according to claim 8.

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