JP2005283922A - Image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display device equipped with an auxiliary wiring which can easily be formed. <P>SOLUTION: On a substrate, a TFT (thin-film transistor) and an organic EL (electroluminescence) element are formed. A lower pixel electrode that the EL element has is connected to the drain electrode of the TFT. Further, a conductive film for reducing the resistance of an upper pixel electrode is formed on the upper pixel electrode facing the lower pixel electrode across the organic EL layer. The conductive film is formed having at least two end parts. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image display device.

  The thin film display device has a structure in which a light emitting element (for example, an organic EL element) is provided on a transparent insulating substrate. The light emitting element includes a light emitting layer sandwiched between a lower pixel electrode formed on a transparent insulating substrate and an upper pixel electrode facing the lower pixel electrode. In such a configuration, light emitted from the light emitting element is extracted from the transparent insulating substrate side. However, since this structure has a limit in increasing the aperture ratio, a top emission type structure in which light is extracted from the opposite side of the transparent insulating substrate has been proposed. In this case, an upper pixel electrode capable of transmitting light is essential. In order to realize such an electrode, a laminated structure of a transparent electrode and a metal layer is employed (see, for example, Patent Document 1).

However, in the case of such a structure, there is a limit in ensuring the transmittance for visible light by sufficiently reducing the resistance of the upper pixel electrode. Therefore, a technique for forming an auxiliary wiring for reducing the resistance of the upper pixel electrode has been proposed. According to this, the resistance of the upper pixel electrode can be sufficiently lowered, and the transmittance can be secured. In this configuration, the auxiliary wiring is formed in a continuous annular shape so as to completely surround each pixel, for example (see, for example, Patent Document 2).
JP-A-10-294182 Japanese Patent Laid-Open No. 2001-230086

  For example, when the light emitting element is an organic EL element, it is considered that the auxiliary wiring is formed by vapor deposition or the like, not by a method such as film formation and patterning, in order to prevent deterioration of characteristics of the organic EL layer. However, when the annular auxiliary wiring as described above is formed, it is impossible to realize a vapor deposition mask having an annular opening corresponding to the shape of the auxiliary wiring. Moreover, even if it can be created, it is expected that the deposition mask is very difficult to create. As described above, the conventional technique has a problem that the process for forming the auxiliary wiring is very difficult and the auxiliary wiring cannot be easily formed.

  Therefore, an object of the present invention is to provide an image display device including auxiliary wiring that can be easily formed.

  In order to achieve the above object, an image display device of the present invention includes a substrate, at least a transistor formed on the substrate, a light emitting element formed on the substrate and connected to the transistor, and the light emitting element. A conductive film formed thereon, and the light-emitting element includes at least a pair of electrodes and a light-emitting layer sandwiched between the pair of electrodes, and the pair of electrodes At least one of the pair of electrodes is capable of transmitting light, one of the pair of electrodes is connected to a drain electrode of the transistor, the conductive film has at least two ends, and the pair of electrodes It is formed on the other.

  According to this invention, since the conductive film has at least two ends, the conductive film can be easily formed by vapor deposition or the like.

  The image display device may include a plurality of pixels, and the conductive film may be formed in a region corresponding to the plurality of pixels.

  Each of the plurality of pixels may have a rectangular shape, and the width of the conductive film may be narrower than the length of each long side of the plurality of pixels.

  The width of the conductive film may be 1/10 or less of the length of each long side of the plurality of pixels.

  In this way, for example, even if the conductive film covers the pixel region, the aperture ratio is not greatly reduced. Therefore, it can be prevented from being recognized as dark by human eyes.

  The conductive film may have a resistivity lower than a resistivity of the other of the pair of electrodes.

  Thereby, the other resistance of the pair of electrodes included in the light emitting element can be reduced.

  The light emitting layer may be formed of an organic electroluminescent material.

  ADVANTAGE OF THE INVENTION According to this invention, an image display apparatus provided with the auxiliary wiring which can be formed easily can be provided.

  The present invention realizes an image display device including auxiliary wiring that can be easily formed. The image display device is, for example, an active display device including a switching element formed on a substrate and a light emitting element formed on the substrate on which the switching element is formed. The switching element is, for example, a field effect thin film transistor. The light emitting element is, for example, an organic EL (electroluminescence) element. An image can be displayed by causing the light emitting element to emit light using the switching element.

  The organic EL element includes a pair of electrodes and an organic layer sandwiched between the pair of electrodes. The organic layer includes a light emitting layer and emits light when a predetermined voltage is applied. Here, of the pair of electrodes, an electrode formed on the substrate side is a lower pixel electrode, and an electrode facing the lower pixel electrode with the light emitting layer interposed therebetween is an upper pixel electrode. Also, a plurality of lower pixel electrodes are formed so as to correspond to a plurality of pixels, for example. On the other hand, the organic layer and the upper pixel electrode are formed as a single film so as to correspond to all the pixels, for example.

  When a flat upper pixel electrode auxiliary wiring is formed between lower pixel electrodes on a substrate on which a thin film transistor (TFT) is formed, and an organic layer and an upper pixel electrode are uniformly formed thereon, the upper pixel electrode and the auxiliary pixel electrode An organic layer exists between the wiring. For this reason, the wiring resistance of the upper pixel electrode cannot be lowered by the auxiliary wiring. Therefore, consider the following structure.

  A lower pixel electrode, an organic layer, and an upper pixel electrode are formed on the substrate on which the TFT is formed, and a lower resistivity than the upper pixel electrode is provided in a region corresponding to the space between the lower pixel electrodes on the upper pixel electrode. The auxiliary wiring having is formed. Accordingly, since the auxiliary wiring is in direct contact with the upper pixel electrode, the auxiliary wiring can sufficiently perform the function of reducing the wiring resistance of the upper pixel electrode.

Here, in order to realize sufficient gradation, the contact resistance between the auxiliary wiring and the upper pixel electrode is preferably 500 kΩ or less. Moreover, the lower limit value of the contact resistance is about 1.0 × 10 ⁻² Ω. If the contact resistance is 500 kΩ or less, it is possible to suppress a voltage drop caused by the contact resistance. As a result, the organic EL element can emit light without applying an unnecessary voltage to the switching element, and the light emission luminance does not vary.

  Further, as described above, the auxiliary wiring for the upper pixel electrode is formed in a region corresponding to between the lower pixel electrodes, that is, a region corresponding to a plurality of pixels. In this case, the width of the auxiliary wiring is set sufficiently narrower than the length of the long side of one pixel (or one lower pixel electrode). Specifically, the width of the auxiliary wiring is set to, for example, 1/10 or less of the long side of one pixel. Thereby, the fall of the aperture ratio in each pixel can be suppressed. That is, even if the auxiliary wiring overlaps with the pixel, the aperture ratio is not lowered and is not recognized as dark.

  In addition, a plurality of upper pixel electrode auxiliary wirings in the present embodiment are formed in a region corresponding to between pixels. The plurality of auxiliary wirings each have a linear shape with a predetermined length, and are separated from each other and formed discontinuously. Alternatively, the upper pixel electrode auxiliary wiring in the present embodiment is arranged such that a plurality of linear conductive films having a predetermined length are continuously connected to each other, so that the entire pixel region is arranged in a region corresponding to the pixel. It is formed continuously so that there are no discontinuous portions. Thus, the auxiliary wiring can be easily formed by vapor deposition using a mask having a plurality of linear openings having a predetermined length.

  In the case of performing color display using light emitted from the organic EL element, a color filter and a color conversion layer are required in addition to the above configuration. When light is extracted from the upper pixel electrode side, the upper pixel electrode is formed of a material that transmits light so that the counter substrate on which the color filter and the color conversion layer are formed faces the substrate on which the organic EL element is formed. Be placed. Thus, a color display device can be realized using a light emitting element that emits white light or blue light.

  On the other hand, when light is extracted from the lower pixel electrode side, the lower pixel electrode is formed of a material that transmits light, and a color filter and a color conversion layer are formed between the TFT and the organic EL element. Thus, a color display device can be realized using a light emitting element that emits white light or blue light.

  Next, a method for manufacturing the image display device according to the present embodiment will be described with reference to FIGS. FIG. 1 shows a method of manufacturing a field effect thin film transistor (FET) constituting the layer display device. FIG. 1 shows an example of a method for manufacturing an N-type FET. FIG. 2 shows a method for manufacturing an organic EL element constituting the image display apparatus. FIG. 3 shows an emission spectrum for explaining the emission characteristics of the organic EL element that emits blue-green light. FIG. 4 shows the configuration of the organic EL element connected to the P-type FET. FIG. 5 shows an emission spectrum for explaining the emission characteristics of the organic EL element that emits white light. FIG. 6 shows an arrangement of color filters constituting the image display apparatus. FIG. 7 is a conceptual diagram for explaining a state in which the organic EL element and the color filter are bonded together.

First, a method for manufacturing an N-type FET will be described with reference to FIG.
In the step shown in FIG. 1A, first, a substrate 1 made of quartz or glass is prepared. Then, a SiO ₂ layer (not shown) is formed on the substrate 1 to a thickness of about 100 nm by, for example, sputtering. Subsequently, an amorphous silicon layer is formed on the SiO ₂ layer to a thickness of about 100 nm by, for example, a CVD (Chemical Vapor Deposition) method. The conditions for forming the amorphous silicon layer are, for example, as follows. The flow rate of the Si ₂ H ₆ gas is 100 SCCM, the pressure condition is 0.3 Torr, and the temperature condition is 480 ° C. Then, the amorphous silicon layer is crystallized by the solid phase growth method. As a result, the amorphous silicon layer becomes a polysilicon layer. The conditions for solid phase growth are, for example, as follows. For example, the flow rate of N ₂ gas is 1 SLM, the temperature condition is 600 ° C., and the treatment time is 5 to 20 hours. Thereafter, the active silicon layer 20 is obtained by patterning the polysilicon layer into a predetermined shape.

Next, in the step shown in FIG. 1B, an SiO ₂ layer 21 to be a gate oxide film is formed on the active silicon layer 20 to a thickness of about 100 nm by, for example, a plasma CVD method. The conditions for forming the SiO ₂ layer 21 are, for example, as follows. The power is 50 W, the flow rate of TEOS (tetraethoxysilane) gas is 50 SCCM, the flow rate of O ₂ gas is 500 SCCM, the pressure condition is 0.1 to 0.5 Torr, and the temperature condition is 350 ° C.

Subsequently, in the step shown in FIG. 1C, the amorphous silicon layer to be the gate electrode 3 is formed on the SiO ₂ layer 21 under the same conditions as those for forming the active silicon layer 20 described above, for example. A thickness of about 400 nm is formed by the method. Further, this amorphous silicon layer becomes a polysilicon layer by being annealed under the same conditions as those for forming the active silicon layer 20 described above, for example. Thereafter, the SiO ₂ layer 21 and the polysilicon layer on the SiO ₂ layer 21 are patterned into a predetermined shape by dry etching, for example. Thereby, the gate electrode 3 and the gate oxide film 21 are formed.

  Next, in the step shown in FIG. 1D, the gate electrode 3 is used as a mask, and an N-type impurity (for example, P (phosphorus)) is separated from the source region and the drain region of the active silicon layer 20 by ion doping. Doped to the part that should be. When manufacturing a P-type FET, a P-type impurity (for example, B (boron)) is doped.

  1E, the active silicon layer 20 is heated at about 550 ° C. for 5 hours in a nitrogen atmosphere. Thereby, the dopant implanted into the active silicon layer 20 is activated. Further, the active silicon layer 20 is heated at about 400 ° C. for 30 minutes in a hydrogen atmosphere (hydrogenation process). Thereby, the defect level density of the semiconductor contained in the active silicon layer 20 decreases. In this way, a source region and a drain region are formed in the active silicon layer 20.

Next, in the step shown in FIG. 1 (f), a SiO ₂ layer serving as an interlayer insulating layer 22 is formed on the entire surface of the substrate 1 with a thickness of about 400 nm by, for example, CVD using TEOS as a starting material. The The conditions for forming the interlayer insulating layer 22 are, for example, as follows. The power is 50 to 300 W, the flow rate of TEOS gas is 10 to 50 SCCM, the flow rate of O ₂ gas is 500 SCCM, the pressure condition is 0.1 to 0.5 Torr, and the temperature condition is 350 ° C. Note that the surface of the interlayer insulating film 22 may be planarized by, for example, a CMP (Chemical Mechanical Polishing) method, if necessary.

  In the step shown in FIG. 1G, a portion of the interlayer insulating layer 22 corresponding to the source region and the drain region of the active silicon layer 20 is removed by etching. As a result, contact holes 23 reaching the source region and the drain region of the active silicon layer 20 are formed.

  As described above, the FET constituting the layer display device is manufactured. In addition, although the manufacturing method of N type FET was shown as an example above, the manufacturing process of P type FET is also almost the same as the manufacturing method of N type FET. Specifically, P-type TFE can be manufactured by the same process as described above by changing the conductivity type or the like of the impurity implanted into the active silicon layer 20.

Next, the manufacturing method of the organic EL element which comprises an image display apparatus is demonstrated. The organic EL element is connected to the N-type FET as described below.
First, in the process shown in FIG. 2A, an Al film is formed on the entire surface of the substrate 1 on which the N-type FET is formed by vapor deposition. Then, the Al wiring 24 is formed by patterning the Al film into a predetermined shape. The Al wiring 24 is connected to the source region or the drain region of the active silicon layer 20 through the hole 23.

  Next, in the step shown in FIG. 2B, an Al · Mg metal (Mg 90 mol%) film is formed in a predetermined region on the substrate 1 by vapor deposition. Specifically, the Al · Mg metal (Mg 90 mol%) film is formed in a region including the arrangement region of the organic EL element. Then, the lower pixel electrode (cathode) 25 of the organic EL element is formed by patterning the Al · Mg metal (Mg 90 mol%) film into a predetermined shape. The lower pixel electrode 25 may be formed on the Al wiring 24 or may be connected to the Al wiring 24 by a connector formed by patterning. In addition to Al / Mg metal, a material having a work function of about 4 eV or less can be used.

  In the step shown in FIG. 2C, the polyimide film is formed by, for example, vapor deposition polymerization so as to cover the edge portion of the lower pixel electrode 25 and expose the lower pixel electrode 25 of the light emitting portion. Thereby, the edge cover 26 covering the edge portion of the lower pixel electrode 25 is formed.

  In the step shown in FIG. 2D, the oxide film formed on the surface of the lower pixel electrode 25 is removed by sputter etching in the multi-chamber. Thereafter, on the lower pixel electrode 25 and the edge cover 26, for example, a first organic layer 8-1, a light emitting layer 8-2, a hole transporting layer 8-3, and a hole injecting layer 8-4 serving as an electron transporting layer are formed. In this order by vapor deposition. As a result, the organic EL layer 8 is formed on the lower pixel electrode 25 and the edge cover 26.

The first organic layer 8-1 is composed of DQX represented by the following chemical formula 1. The light emitting layer 8-2 is composed of DPA represented by the following chemical formula 2. The hole transport layer 8-3 is composed of TPD represented by the following chemical formula 3. The hole injection layer 8-4 is composed of MTDATA represented by the following chemical formula 4. In Chemical Formula 2, Rn represents a methyl group or an ethyl group.

Next, an upper pixel electrode (anode) 9 made of a transparent conductive material is formed on the organic EL layer 8. The transparent conductive material is, for example, IZO (In ₂ O ₃ .ZnO (5 mol%)). Thereby, an organic EL element is manufactured.

As shown in FIG. 2D, the drain region of the N-type FET and the organic EL element are connected to each other via an Al wiring 24. At this time, gate polysilicon or active silicon of an N-type FET is used as a load resistance exhibiting linear characteristics. The upper pixel electrode 9 may be formed of ITO (In ₂ O ₃ , SnO ₂ (10 mol%)) or the like other than IZO.

  FIG. 3 is a diagram showing the light emission characteristics of the organic EL element having the above configuration. The vertical axis of FIG. 3 shows the emission intensity, and the horizontal axis shows the wavelength. The organic EL element described above has a wavelength-output intensity characteristic (relative value) as shown in FIG. 3 and emits blue-green light.

  Although the case where the N-type FET and the organic EL element are connected has been described above, the same structure as described above can be adopted when the P-type FET and the organic EL element are connected. Thereby, also when connecting P type FET and an organic EL element, the process similar to FIG. 2 (a)-FIG.2 (d) is employable. That is, it is substantially the same as that of the N-type FET except that the lower pixel electrode 25 is an anode and the upper pixel electrode 9 is a cathode.

  Next, the structure and manufacturing method of the organic EL element that emits white light will be described. It is assumed that the FET connected to the organic EL element is a P-type FET. That is, the lower pixel electrode 25 is an anode, and the upper pixel electrode 9 is a cathode. In this case, the lower pixel electrode (anode) 25 preferably has a laminated structure of a transparent electrode and a metal layer or a laminated structure of a plurality of metal layers. For example, the lower pixel electrode (anode) 25 is composed of a laminate of a TiN layer that reflects light and a transparent ITO layer formed on the TiN layer.

  As shown in FIG. 4, a hole injection layer 8′-1, a hole transport layer 8′-2, a lower light emitting layer 8′-3, and an upper light emitting layer 8′− are formed on the lower pixel electrode 25 and the edge cover 26. 4. An electron transport layer 8′-5 and an inorganic electron injection layer 8′-6 are formed in this order by vapor deposition. Thereby, the organic EL layer 8 ′ is formed on the lower pixel electrode 25 and the edge cover 26.

  The hole injection layer 8′-1 is composed of N, N′-diphenyl-N, N′-bis (N- (4-methylphenyl) -N-phenyl (4-aminophenyl))-1,1′-bis. Formed from phenyl-4,4'-diamine. The hole transport layer 8'-2 is formed from N, N'-diphenyl-N, N'-bis (1-naphthyl) -1,1'-diphenyl-4,4'-diamine. The lower light emitting layer 8'-3 is formed of a material containing a compound X represented by the following chemical formula 5 and a compound Y represented by the following chemical formula 6 in a volume ratio of 100: 3. The upper light emitting layer 8'-4 is formed of a material containing a compound X represented by the following chemical formula 7 and a compound Z represented by the following chemical formula 8 in a volume ratio of 100: 3. The electron transport layer 8'-5 is formed from tris (8-hydroxyquinoline) aluminum. The inorganic electron injection layer 8'-6 is made of LiF.

  A transparent upper pixel electrode (cathode) 9 is formed on the organic EL layer 8 'formed as described above. The upper pixel electrode 9 is formed by laminating a ZnO—Al (ZnO, Al (3 mol%)) layer and an Au layer. Thus, an organic EL element that emits white light is manufactured.

As shown in FIG. 4, the P-type FET and the organic EL element are connected to each other via an Al wiring 24. At this time, gate polysilicon or active silicon of a P-type FET is used as a load resistance exhibiting linear characteristics. The upper pixel electrode 9 may be made of IZO (In ₂ O ₃ , ZnO ₂ (5 mol%)), ITO, or the like, in addition to the stacked body of the ZnO—Al layer and the Au layer. The organic EL element having the above configuration has a wavelength-output intensity characteristic (relative value) as shown in FIG. 5 and emits white light.

  Next, a case where the substrate 1 on which the FET is formed and the substrate on which the color filter is formed are bonded together will be described. Note that the image display device according to the present embodiment has auxiliary wiring formed on the upper pixel electrode 9, but is not shown in FIG. The formation of the auxiliary wiring will be described in detail later.

  As shown in FIG. 6, there are three types of color filters 31: a red filter 31R, a green filter 31G, and a blue filter 31B. The red filter 31R, the green filter 31G, and the blue filter 31B are arranged in a predetermined order on a transparent counter substrate 30 such as a glass plate. Note that the fluorescent filter 34 may be laminated only on the red filter 31R in order to increase the emission intensity.

  As shown in FIG. 7, the counter substrate 30 on which the color filter 31 as shown in FIG. 6 is formed and the substrate 1 on which the FET and organic EL element as shown in FIG. Can be pasted together. As shown in FIG. 7, the FET 53 formed on the substrate 1 is connected to the lower pixel electrode 25 of the organic EL element via the Al wiring 24 or directly. On the lower pixel electrode 25, the organic EL layer 8 (or 8 ') and the upper pixel electrode 9 are formed. On the other hand, a color filter 31 is formed on the counter substrate 30 facing the substrate 1 so as to face the upper pixel electrode 9. When the color filter 31 is the red filter 31R, the fluorescent filter 34 may be provided as described above.

  In the above description, the configuration in which the RGB color filter 31 is provided in the organic EL element that emits blue-green light or white light has been described. However, other configurations may be employed. For example, when the organic EL element emits blue light, a configuration in which a fluorescent filter 34 is provided in each of the red filter 31R and the green filter 31G may be employed. Further, when the organic EL element emits blue light and red light, a configuration in which a fluorescent filter 34 is provided on the green filter 31G may be employed.

The inorganic electron injection layer 8′-6 is formed of n-type amorphous SiC, the hole transport layers 8-3 and 8′-2 are formed of p-type amorphous SiC, and the light emitting layers 8-2 and 8 ′. In the case where −3,8′-4 is formed from tris (8-hydroxyquinoline) aluminum represented by the following chemical formula 9, the light emitting layers 8-2, 8′-3, 8′-4 are made of n-type amorphous SiC and You may form from the material which mixed p-type amorphous SiC.

  By adopting the configuration shown above, a constant voltage TFT drive type top emission type panel that emits light from the counter substrate 30 side can be realized. However, in a constant voltage TFT drive type top emission type panel, it is difficult to increase the size and definition of the panel unless the upper pixel electrode auxiliary wiring is employed and the wiring resistance of the upper pixel electrode is reduced. Therefore, the configuration and manufacturing method of the constant voltage TFT driving type top emission type panel having the auxiliary wiring for the upper pixel electrode according to the present embodiment will be described with reference to FIG. In FIG. 8, unlike the above-described FIG. 2, for example, an interlayer insulating film covering the transistor is formed on the entire surface of the substrate with a substantially constant thickness.

  As shown in FIG. 8, a thin film transistor (TFT) 74 formed by a thin film process similar to the above is provided on an insulating substrate 71. At least one TFT 74 is formed per pixel. In FIG. 8, two TFTs 74 are shown as an example. A plurality of lower pixel electrodes 78 are formed on the insulating film 83 covering the TFT 74 so as to correspond to the plurality of pixels, respectively. The lower pixel electrode 78 is composed of two layers, a metal layer 76 and an ITO layer 77. The lower pixel electrode 78 is electrically connected to a drain electrode 75d included in one TFT 74 through a hole 83a formed in the insulating film 83. The gate electrode 75g of one TFT 74 and the drain electrode 73d of the other TFT 74 are connected by a connection wiring (not shown). The source electrode 73s included in the other TFT 74 and the source electrode 75s included in the one TFT 74 are connected to a connection wiring (not shown) to form a signal line and a power supply electrode. The drain electrode 75d included in one TFT 74 is connected to the light emitting element. When the lower pixel electrode 78 is an anode, the TFT 74 connected to the lower pixel electrode 78 is a P-type TFT. When the lower pixel electrode 78 is a cathode, the TFT 74 connected to the lower pixel electrode 78 is an N-type TFT.

  A region between the lower pixel electrodes 78, that is, a region corresponding to the interval between the pixels is filled with a resist, thereby forming an edge cover 81 that covers an edge portion of the lower pixel electrode 78. Note that the edge cover 81 is formed thicker than the lower pixel electrode 78. An organic EL layer 79 is formed on the entire surface of the lower pixel electrode 78 and the edge cover 81. The organic EL layer 79 can employ the above-described configuration. An upper pixel electrode 80 is formed on the entire surface of the organic EL layer 79. The upper pixel electrode 80 is composed of two layers, for example, a LiF layer and a ZnO.Al layer.

  A conductive film 82 having a lower resistivity than the upper pixel electrode 80 is formed as an auxiliary wiring for the upper pixel electrode in a region corresponding to the area between the pixels on the upper pixel electrode 80. The conductive film 82 is formed by vapor deposition as will be described later. At this time, a plurality of linear conductive films 82 having a predetermined length are formed so as to be separated from each other and discontinuously arranged. Alternatively, a plurality of linear conductive films 82 having a predetermined length are formed so as to be continuously connected to each other. Since the conductive film 82 has such a configuration, the conductive film 82 can be easily formed by vapor deposition.

  The width of the conductive film 82 is set to be sufficiently narrower than the length of the long side of one pixel. Specifically, the width of the conductive film 82 is set to 1/10 or less of the length of the long side of one pixel. For this reason, even if the formation position of the conductive film 82 is slightly deviated, the light emitting region is not greatly reduced, and it is not recognized by humans that it is dark. That is, the aperture ratio is not greatly reduced.

  On the other hand, a color filter 84 is formed on the counter substrate 72 so as to correspond to each pixel. The configuration of the color filter 84 is the same as described above. Further, a black matrix 85 that blocks light may be formed in a region corresponding to between pixels on the counter substrate 72.

  The constant voltage TFT driving according to the present embodiment is performed by bonding the substrate 71 on which the TFT 74 and the organic EL element as described above and the counter substrate 72 on which the color filter 84 is formed as shown in FIG. A system top emission type panel is realized. In the panel having the above configuration, when a predetermined voltage is applied between the lower pixel electrode 78 and the upper pixel electrode 80, light is emitted from the organic EL layer 79 sandwiched therebetween. The emitted light is radiated to the outside through the upper pixel electrode 80, the color filter 84, and the counter substrate 72 as indicated by arrows in FIG.

  In the top emission type panel having the above configuration, the contact resistance between the upper pixel electrode auxiliary wiring 82 and the entire upper pixel electrode 80 is preferably 200 kΩ or less. The sheet resistance value of the upper pixel electrode 80 is, for example, 8Ω / □.

  Next, a method for producing the constant voltage TFT driving type top emission type panel shown in FIG. 8 will be described. The order of the steps for producing the TFT substrate is substantially the same as that in FIG.

(1) First, a substrate 71 made of quartz or glass is prepared. Then, an amorphous silicon layer is formed on the substrate 71 to a thickness of about 100 nm by a CVD (Chemical Vapor Deposition) method. The film forming conditions are, for example, as follows. The flow rate of the Si ₂ H ₆ gas is 100 SCCM, the pressure condition is 0.3 Torr, the temperature condition is 480 ° C., and the like. Then, the amorphous silicon layer is crystallized by the solid phase growth method. As a result, the amorphous silicon layer becomes a polysilicon layer. The conditions for solid phase growth are as follows. The flow rate of N ₂ gas is 1 SLM, the temperature condition is 600 ° C., and the treatment time is 5 hr to 20 hr. Thereafter, the active silicon layer 20 is obtained by patterning the polysilicon layer into a predetermined shape.

(2) On the active silicon layer 20, a SiO ₂ layer 21 to be a gate oxide film is formed with a thickness of about 100 nm by a plasma CVD method. The film formation conditions for the SiO ₂ layer 21 are as follows. The power is 50 W, the flow rate of TEOS (tetraethoxysilane) gas is 50 SCCM, the flow rate of O ₂ gas is 500 SCCM, the pressure condition is 0.1 to 0.5 Torr, and the temperature condition is 350 ° C.

(3) An N-type amorphous silicon layer to be the gate electrodes 73g and 75g is formed on the SiO ₂ layer 21 to a thickness of about 400 nm by the CVD method. The conditions for forming the N-type amorphous silicon layer are as follows. For example, the flow rate of (Si ₂ H ₆ + 0.5% PH ₃ ) gas is 100 SCCM, the pressure condition is 0.3 Torr, and the temperature condition is 480 ° C. The amorphous silicon layer is annealed under the same conditions as in (1) above. Thereby, an N-type polysilicon layer to be the gate electrodes 73g and 75g is formed. Thereafter, the polysilicon layer and the SiO ₂ layer 21 formed in the above (2) are patterned into a predetermined shape by dry etching. Thereby, the gate electrodes 73g and 75g and the gate oxide film 21 are formed.

(4) Using the gate electrodes 73g and 75g as a mask, P-type impurities (for example, B (boron)) are added to the portions of the active silicon layer 20 to be the source region and the drain region by ion doping. Doping is performed with an implantation amount of 10 ¹⁵ (ions / cm ² ).

  (5) Then, the active silicon layer 20 doped with impurities is heated at about 550 ° C. for 5 hours in a nitrogen atmosphere. Thereby, the implanted dopant is activated. Further, the active silicon layer 20 is heated at about 400 ° C. for 30 minutes in a hydrogen atmosphere. Thereby, the active silicon layer 20 is hydrogenated, and the defect level density of the semiconductor is reduced. As described above, the source region and the drain region are formed in the active silicon layer 20.

(6) Next, an SiO ₂ layer 83b serving as a first interlayer insulating layer is formed on the entire surface of the substrate 71 with a thickness of about 400 nm by using a CVD method. The conditions for forming the SiO ₂ layer 83b are as follows. The power is 50 to 300 W, the flow rate of TEOS gas is 10 to 50 SCCM, the flow rate of O ₂ gas is 500 SCCM, the pressure condition is 0.1 to 0.5 Torr, and the temperature condition is 350 ° C.

  (7) Then, a portion of the first interlayer insulating layer 83b corresponding to the source region and the drain region of the active silicon layer 20 is removed by etching. As a result, contact holes 23 reaching the source region and the drain region of the active silicon layer 20 are formed.

  (8) A TiN layer is formed on the first interlayer insulating film 83b to a thickness of about 150 nm by sputtering. Then, by patterning the formed TiN layer into a predetermined shape, source electrodes 73 s and 75 s connected to the source region of the active silicon layer 20 and drain electrodes 73 d and 75 d connected to the drain region of the active silicon layer 20 are formed. It is formed.

(9) Then, a SiO ₂ layer 83c to be a second interlayer insulating film is formed on the first interlayer insulating film 83b to a thickness of about 400 nm by the CVD method. The conditions for forming the SiO ₂ layer 83c to be the second interlayer insulating layer are the same as in (6). Then, a portion of the second interlayer insulating layer 83c corresponding to the source electrode 73s included in the other TFT 74 is removed by etching. Thereby, a contact hole (not shown) reaching the source electrode 73s is formed.

  (10) Next, an Al-0.18 wt% Sc layer for power supply wiring is formed on the second interlayer insulating film 83c to a thickness of about 1000 nm by sputtering. Then, by patterning the formed Al-0.18 wt% Sc layer into a predetermined shape, a power supply wiring (not shown) connected to the source electrode 73 s included in the other TFT 74 is formed.

(11) Then, an SiO ₂ layer 83d to be a third interlayer insulating film is formed on the second interlayer insulating film 83c to a thickness of about 400 nm by a CVD method. The deposition conditions for the SiO ₂ layer 83d to be the third interlayer insulating layer are the same as in (6). Note that the surface of the third interlayer insulating layer 83d may be planarized by a CMP method or the like as necessary.

  (12) Then, the portions of the second and third interlayer insulating films 83c and 83d corresponding to the drain electrode 75d included in one TFT 74 are removed by etching. As a result, a contact hole 83a reaching the drain electrode 75d included in one TFT 74 is formed. The hole 83a penetrating the second and third interlayer insulating films 83c and 83d is used to connect the metal layer 76 constituting the lower pixel electrode 78 and the drain electrode 75d included in one TFT 74.

  Through the above steps, a TFT substrate having a configuration as shown in FIG. 8 is produced. In addition, the above process (1)-(12) is for producing a TFT substrate. The insulating film 83 is composed of first to third interlayer insulating films 83b, 83c, 83d.

  Next, as shown in FIG. 8, a TiN film (metal layer) 76 is formed on the entire surface of the TFT substrate, that is, the entire surface of the insulating film 83 to a thickness of about 50 nm by sputtering, for example. Subsequently, an ITO film 77 is formed on the TiN film 76 to a thickness of about 100 nm by sputtering, for example. Then, as shown in FIG. 8, by patterning the TiN film 76 and the ITO film 77 into a predetermined shape, a plurality of lower pixel electrodes 78 respectively corresponding to the plurality of pixels are formed.

  Thereafter, as shown in FIG. 8, an edge cover 81 covering the edge portion of the lower pixel electrode 78 is formed by filling the region between the lower pixel electrodes 78, that is, the lattice region corresponding to the interval between the pixels. Is done. At this time, the edge cover 81 is formed thicker than the lower pixel electrode 78.

  Next, as shown in FIG. 8, an organic EL layer 79 is formed on the entire surface of the lower pixel electrode 78 and the edge cover 81 by, for example, vapor deposition. At this time, the lower light emitting layer is formed of a material containing, for example, the above-described compound X and compound Y in a volume ratio of 100: 3, and has a thickness of about 10 nm. The upper light emitting layer is made of a material containing, for example, the above-described compound X and compound Z in a volume ratio of 100: 3, and has a thickness of about 30 nm.

  Thereafter, as shown in FIG. 8, a LiF film is formed on the entire surface of the organic EL layer 79 to a thickness of about 5 nm, for example, by vapor deposition. Then, a ZnO.Al film is formed on the entire surface of the LiF layer to a thickness of about 120 nm by, for example, sputtering. Subsequently, an Au film is formed on the entire surface of the ZnO.Al film to a thickness of about 10 nm, for example, by vapor deposition. Further, a ZnO.Al film is formed on the entire surface of the Au film to a thickness of about 80 nm, for example, by sputtering. Thus, the upper pixel electrode 80 having a laminated structure of the LiF film and the ZnO.Al/Au/ZnO.Al film is formed. Here, the upper pixel electrode 80 was formed so that the average transmittance of the upper pixel electrode 80 in visible light was 70% and the sheet resistance was 8Ω / □.

  As described above, the edge cover 81 is formed thicker than the lower pixel electrode 78. For this reason, the surface of the upper pixel electrode 80 is raised in a region corresponding to between pixels. The conductive film 82 serving as the upper pixel electrode auxiliary wiring is formed on the raised portion of the upper pixel electrode 80.

  Specifically, an Al film is formed as a conductive film 82 to a thickness of about 0.3 μm by vapor deposition. At this time, for example, masks as shown in FIGS. 9A to 9D are used. Each mask has a plurality of linear openings having a predetermined length and arranged in a predetermined arrangement. Which mask is used to form the conductive film 82 is determined in accordance with, for example, the purpose of use of the constant voltage TFT drive type top emission type panel or the required performance. When the contact resistance between the conductive film 82 thus formed and the upper pixel electrode 80 was measured, the contact resistance was 20 kΩ. The arrangement patterns of the conductive film 82 formed by the masks of FIGS. 9A to 9D are as shown in FIGS. 10A to 10D, respectively.

By using the mask as described above, a plurality of linear conductive films 82 having a predetermined length are formed in the regions corresponding to the pixels. In this case, the plurality of conductive films 82 are arranged separately from each other, but can directly perform the function of reducing the wiring resistance because they are in direct contact with the upper pixel electrode 80. In addition, since the width of the conductive film 82 is set to 1/10 or less of the long side of one pixel, the width of the corresponding mask opening is set to be sufficiently narrow compared to the long side of one pixel. As a result, the strength of the mask is sufficiently strong, and the mask is not bent. In the case where the plurality of conductive films 82 are connected continuously, the vapor deposition process may be performed a plurality of times using, for example, the mask shown in FIG. At this time, the position of the mask may be moved by a predetermined distance every time the vapor deposition process is performed.
As described above, the TFT 74, the organic EL element, and the conductive film 82 are formed on the substrate 1.

  On the other hand, R (red), G (green), and B (blue) color filters 84 are regularly arranged on the counter substrate 72 facing the substrate 71, and a black resin layer (black matrix) is interposed between the color filters. 85 is formed. By attaching the counter substrate 72 and the substrate 71 to each other with an adhesive, the organic material has a diagonal size of 4.0 inches (aspect ratio 4: 3), a resolution of VGA, and a display color number of 260,000 colors. An EL full color panel is created. For example, as shown in FIG. 11, the cathode pad 141 of the organic EL full-color panel 140 is disposed around the panel 140 (upper and lower left and right portions).

  The above organic EL full-color panels were prepared under different conditions, and the surface average brightness at each part of each panel was compared. As a condition, the mask used when forming the conductive film 82 was changed. The masks used are those shown in FIGS. 9 (a) to 9 (d). The structure of the conductive film 82 is as described above. The measurement points are as shown in FIG. In any case, if the conductive film 82 having a width of 1/10 or less of the long side of one pixel is formed in the portion corresponding to the area between the pixels on the upper pixel electrode 80, the in-plane luminance variation at the measurement location. Was within ± 3%.

  As described above, the conductive film 82 having a width equal to or smaller than 1/10 of the long side of one pixel is formed in a portion corresponding to the space between the pixels on the upper pixel electrode 80, thereby wiring the upper pixel electrode 80. Resistance can be lowered, and variations in light emission luminance can be suppressed to a low level. Further, the conductive film 82 is formed in a straight line having a predetermined length. Thereby, the conductive film 82 can be easily formed by vapor deposition using a mask.

  In the above description, the case where the conductive film 82 is formed in a straight line having a predetermined length has been described. However, the conductive film 82 may not be linear. For example, an L shape or a cross shape as shown in FIG. 13 may be used. That is, each conductive film 82 formed by one deposition process may have any shape as long as it has a shape having at least two ends instead of a closed shape like a ring. However, also in this case, as described above, the width of the conductive film 82 is set sufficiently narrower than the length of the long side of one pixel.

  Further, the image display device to which the present invention is applied can be used for any device including an image display panel such as a car stereo or a portable device.

FIG. 1 is a diagram showing a method for manufacturing a field effect thin film transistor (FET) constituting an image display device. FIG. 2 is a diagram illustrating a method for manufacturing an organic EL element constituting the image display apparatus. FIG. 3 is a diagram showing an emission spectrum for explaining the emission characteristics of the organic EL element that emits blue-green light. FIG. 4 is a diagram showing a configuration of an organic EL element connected to the P-type FET. FIG. 5 is a diagram showing an emission spectrum for explaining the emission characteristics of the organic EL element that emits white light. FIG. 6 is a diagram showing the arrangement of color filters constituting the image display apparatus. FIG. 7 is a conceptual diagram for explaining a state in which the organic EL element and the color filter are bonded together. FIG. 8 is a diagram showing a configuration of a constant voltage TFT drive type top emission type panel according to the embodiment of the present invention. FIG. 9 is a diagram showing an example of a mask used when forming a conductive film constituting the panel of FIG. FIG. 10 is a diagram showing an arrangement pattern of conductive films formed using the mask of FIG. FIG. 11 is a diagram showing the arrangement of the cathode pads constituting the organic EL full-color panel. FIG. 12 is a diagram showing measurement points when measuring the surface average luminance of the organic EL full-color panel. FIG. 13 is a diagram illustrating an example of another shape of the conductive film.

Explanation of symbols

1 Substrate 3 Gate electrode 8 Organic EL layer 8-1 First organic layer (electron transport layer)
8-2 Light-Emitting Layer 8-3 Hole Transport Layer 8-4 Hole Injection Layer 8 ′ Organic EL Layer 8′-1 Hole Injection Layer 8′-2 Hole Transport Layer 8′-3 Lower Light-Emitting Layer 8′- 4 Upper light emitting layer 8'-5 Electron transport layer 8'-6 Inorganic electron injection layer 9 Upper pixel electrode 20 Active silicon layer 21 Gate oxide film 22 Interlayer insulating layer 23 Hole 24 Al wiring 25 Lower pixel electrode 26 Edge cover 30 Counter substrate 31 Color filter 31R Red filter 31G Green filter 31B Blue filter 34 Fluorescent filter 53 TET
71 Insulating substrate 72 Counter substrate 73s Source electrode 73d Drain electrode 74 TFT
75s Source electrode 75d Drain electrode 76 Metal layer 77 ITO layer 78 Lower pixel electrode 79 Organic EL layer 80 Upper pixel electrode 81 Edge cover 82 Conductive film 83 Insulating film 83a Hole 83b First interlayer insulating film 83c Second interlayer insulating film 83d First 3 interlayer insulation film 84 Color filter 85 Black matrix

Claims (6)

A substrate,
A transistor formed on at least the substrate;
A light emitting element formed on the substrate and connected to the transistor;
A conductive film formed on the light emitting element;
Comprising
The light emitting element comprises at least a pair of electrodes and a light emitting layer sandwiched between the pair of electrodes,
At least one of the pair of electrodes can transmit light;
One of the pair of electrodes is connected to the drain electrode of the transistor,
The conductive film has at least two ends and is formed on the other of the pair of electrodes.
An image display device characterized by that. The image display device has a plurality of pixels,
The conductive film is formed in a region corresponding to the plurality of pixels.
The image display apparatus according to claim 1. Each of the plurality of pixels has a rectangular shape,
The width of the conductive film is narrower than the length of each long side of the plurality of pixels.
The image display device according to claim 2.   The image display apparatus according to claim 3, wherein a width of the conductive film is 1/10 or less of a length of each long side of the plurality of pixels.   The image display device according to claim 1, wherein the conductive film has a resistivity lower than a resistivity of the other of the pair of electrodes. The image display device according to claim 1, wherein the light emitting layer is made of an organic electroluminescence material.

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