JP2005293728A - Semiconductor memory device - Google Patents

Abstract

An object of the present invention is to suppress an increase in chip area in a semiconductor memory device, to enable correction of a soft error, and to improve the reliability of the semiconductor memory device.
A parity value of a local parity cell 18a in a row corresponding to an error cell 18 bit-inverted by a soft error, and a parity value of a global cell in a corresponding read / write circuit and error correction circuit 18b are detected. The error cell 18 is known by reversing the inverted local parity row and global parity column. Error correction can be performed by further inverting the error cell. That is, by changing the parity value of the read / write circuit and error correction circuit 18b in which an error has been detected and the local parity cell 18a in which an error has been detected, it is possible to correct the error cell with the data inverted.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor memory device having a soft error correction function.

  A dynamic random access memory (hereinafter referred to as DRAM) is widely used as a low-cost, large-capacity main memory mainly in electronic computers. The basic structure of a DRAM memory cell currently used is composed of one transistor and one capacitor.

  When a cosmic ray having an electric charge such as α rays reaches the capacitor and collides with the capacitor, the amount of electric charge stored in the capacitor changes. On the other hand, when cosmic rays that do not have charges such as neutrons collide with a semiconductor substrate having DRAM, the amount of charge stored in the capacitor changes due to the influence of ions generated at that time, and the stored data is lost. There is a case.

  A malfunction of the memory circuit caused by such a phenomenon is temporary and accidental, and is called a soft error, and is distinguished from a hard error that causes fatal damage to the memory circuit. A soft error that occurs at a normal frequency can be sufficiently dealt with by providing an error correction function in the DRAM alone or in the system.

  As a conventional error correction method, an error correction code (hereinafter referred to as ECC) circuit is mainly used. For example, 64 bits of data to be stored in one unit and stored together with 8 bits of redundant data obtained from this data by a logical operation, and a data error of up to 2 bits among the data of 72 bits in total is logically stored. This is a method that enables correction by calculation.

  Further, devices such as a test circuit and a test method for recognizing an error even when an error correction circuit such as ECC is used have been proposed. (For example, refer to Patent Document 1).

  FIG. 10 is a conceptual diagram when performing a conventional error correction method using ECC. For example, an additional cell block 70 for parity is added for 8 column blocks. In the conventional ECC method, 72 (64 + 8) block configuration must be used as a unit due to restrictions. Therefore, the area increase rate is 72 / 64≈ + 5.882%. That is, the chip area is increased by 9/8 times. Therefore, the cost of the product increases.

In the DRAM market, where price competition is intense, it is necessary to reduce the chip area as much as possible, increase the number of chips per semiconductor substrate, and reduce costs. Therefore, it is required to suppress an increase in chip area in the DRAM, to correct a soft error, and to improve the reliability of the DRAM.
JP 2003-157696 A (page 10, FIG. 1)

  The present invention suppresses an increase in chip area in a semiconductor memory device, enables correction of a soft error, and improves reliability in the operation of the semiconductor memory device.

  In order to solve the above problems, according to a first aspect of the present invention, a semiconductor memory device includes a memory cell array in which memory cells are arranged in a row direction and a column direction, a row decoder circuit, a column decoder circuit, and a memory in the column direction. A sense amplifier corresponding to the cell, and a read / write circuit corresponding to the memory cell in the column direction, an arithmetic means for calculating a parity value of each row and a parity value of each column in the memory cell array, and the parity value Storage means for storing; check means for checking the occurrence of a parity error with respect to the parity value; identification means for identifying a memory cell in which an error has occurred based on information on a row and a column in which the parity error has occurred; And correction means for correcting the memory cell in which an error has occurred.

  According to a second aspect of the present invention, as a semiconductor memory device, a memory cell array (m, n) having a block configuration in which memory cell blocks having memory cells in m rows and n columns are arranged in M rows and N columns. , M and N are positive integers), row decoder circuit, column decoder circuit, sense amplifier corresponding to the memory cell in the column direction of the memory cell block, and read / write arranged for each block column of the block configuration An arithmetic circuit for calculating a parity value of m rows and n columns of memory cells common to each memory cell block and a parity value of the memory cells arranged in the memory cell block of the block column. Means, storage means for storing the parity value, check means for checking occurrence of a parity error with respect to the parity value, and Identifying means for identifying a memory cell in which an error has occurred based on information on the row and column of the memory cell block in which the error has occurred, and information on the row and column in the memory cell block, and the memory in which the error has occurred Correction means for correcting the cell.

  According to the present invention, by using a local parity cell and a global parity cell, it is possible to provide a semiconductor memory device that can suppress an increase in the area of the entire chip and can perform error correction as compared with the conventional ECC system.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing the basic principle of a first embodiment of a semiconductor memory device according to the present invention.

  The semiconductor memory device of this embodiment is a DRAM, and has 1 kilobit, that is, 32 rows × 32 columns of data memory cells 11 in a memory cell array 10. Each row has one local parity cell 12. The parity value in each row is stored in the local parity cell 12. The local parity value is stored as even parity by calculating the data related to all cells in the row by exclusive OR.

  Also, a row decoder 13 is arranged for the word lines, a first sense amplifier and precharge circuit 14 for the bit lines, a read / write circuit and error correction circuit 15, a parity operation circuit 16 and a column decoder 17 are arranged. Yes.

  In the read / write circuit and the error correction circuit 15, a register (not shown) which is a global parity cell for storing 1 bit as global parity is prepared. The global parity value is stored as even parity by calculating all cell data of each column by exclusive OR.

  Next, the principle of error detection will be described. When one of the data memory cells, for example, the error cell 18 is bit-inverted due to a soft error, the parity value of the local parity cell 18a in the row corresponding to the error cell 18 and the global parity cell in the corresponding read / write circuit and error correction circuit 18b The parity value of is reversed from the previous calculated value. That is, the error cell 18 can be known by following the previous calculated value, the local parity row and the global parity column in which the current calculated value is inverted.

  Error correction can be performed by further inverting the error cell.

  FIG. 2 is a block diagram showing a memory cell array and main peripheral circuits in the second embodiment of the present invention.

  The semiconductor memory device in this embodiment is a DRAM, and the memory cell array 20 has 512 rows × 64 columns of data memory cell blocks 21 arranged in 32 rows and 32 columns, and the local parity cell block 22 is in the center of the column. Placed in the part. Therefore, a total of 33 memory cell blocks are arranged in the column direction.

  Also, a row decoder 23 is arranged for the word lines, a first sense amplifier and precharge circuit 24, a read / write circuit and error correction circuit 25, a parity operation circuit 26 and a column decoder 27 are arranged for the bit lines. Yes.

  The principle of error detection will be described below. When one of the data memory cells is bit-inverted due to, for example, a soft error, first, the parity value in the local parity cell of the local parity cell block 28a in the column corresponding to the data memory cell block 28 including the error cell, and the corresponding read / write circuit The parity value in the global parity cell in the error correction circuit 28b is inverted from the previous calculated value. That is, the memory cell block 28 including the error cell can be known by following the previous calculated value, the row of the local parity block and the column of the global parity block whose current calculated value is inverted. Further, in the memory cell block 28 including the error cell, the cell that actually caused the error is the same as the error part of the local parity cell block in which the error was detected.

  Similarly to the first embodiment, error correction can be performed by inverting the error cell.

  FIG. 3 is a circuit diagram showing the arrangement of the data memory cells 31 in the data memory cell block 30. Data memory cells 31 are arranged in 512 rows × 64 columns, and first sense amplifiers and precharge circuits 35 are arranged in 64 columns on the right end.

  Next, the operation in the data memory cell block 30 will be described. First, when waiting for a memory operation, the first sense amplifier and the precharge circuit in the precharge circuit 35 reset all the bit lines BL0 to / BL63 to the same potential, that is, an intermediate potential between the high level and the low level. Is done.

  Next, only one row selection line 33 is selected from WL0 to WL511 as a row selection line 33 corresponding to a row address given from outside (not shown), and goes to a high level.

  As a result, the charge of the data stored in the capacitor 32a connected to the transistor 32 is transferred to the bit line via the transistor 32 connected to the selection line, and BLn or / BLn (n: integer from 0 to 63) Increase or decrease the potential of either one of several hundred millivolts.

  Subsequently, the first sense amplifier and the first sense amplifier in the precharge circuit 35 are operated, and the potential difference between BLn or / BLn on the side where the potential is increased or decreased and the other where the potential is not increased or decreased is a logical high level potential. Alternatively, it is amplified to a low level potential. By this amplification, the capacitor that has released the charge when WL is selected is charged again. This is a refresh operation.

  Next, for a column address given from outside (not shown), one line is selected from the 64 column selection lines 37 and connected to the intra-block data bus 36. Further, it is connected to the data bus 39 under the control of the block selection line 38. The data bus 39 is connected to a read / write circuit (not shown). Data from the data bus 39 is output to the read / write circuit as Dn and / Dn (n: integer from 0 to 31).

  When the above-described data memory cell block is applied to the entire block diagram shown in FIG. 2, one data memory cell can be simultaneously read and written from 32 data memory cell block columns arranged in the column direction.

  FIG. 4 shows the local parity block 30a in detail, and the structure is the same as that of FIG. However, the data from the data bus 39 is output to the read / write circuit as Dp and / Dp.

  FIG. 5 shows a detailed circuit diagram of the read / write circuit and error correction circuit 25 in the block diagram of the present embodiment shown in FIG. The read / write circuit 50 is basically the same as a circuit used for a normal DRAM.

  First, a read operation (read) will be described. As shown in FIG. 5, the data Dn and / Dn output through the data bus 51 are amplified using the second sense amplifier 52 and output as read data DataN and / DataN (N: integer from 0 to 31). . When amplifying using the second sense amplifier 52, a timing signal RDE is given. Here, between Dn and DataN and between / Dn and / DataN are independent as nodes. The amplified signal DataN is sent to the output circuit in the normal operation, and the read operation (read) is completed.

  Next, the write operation (write) in FIG. 5 will be described. In normal writing, Wn as data write data from an input buffer circuit (not shown) is input, while WTE is given as a write timing signal. The combination of the inverter, NAND circuit and NOR circuit gives WRT0n or WRT1n for activating the write gate 53, and the signal Dn or / Dn is dropped to the low level, and the first sense amplifier of the memory cell described above The data is written into the memory cell via 35.

  In this embodiment, in addition to normal read and write operations, read and write operations associated with memory cell error checking and error correction are required. The error check and error correction will be described below.

  First, when performing an error correction operation, data is output to a local parity calculation circuit 60 and an error correction circuit 50a, which will be described later, in order to check the occurrence of an error cell.

  FIG. 6 shows a local parity calculation circuit for detecting local parity. The arithmetic circuit unit 61 of the local parity arithmetic circuit 60 is configured by an exclusive OR circuit. Data0-Data31 signals obtained by amplifying the data D0-D31 generated from the respective data memory cell blocks are read out, and the local parity value DataP is output with the final operation result as the local parity operation data 62. Since the exclusive OR circuit is used, when one data is inverted due to an error, DataP as the final data is also inverted.

  Next, an error correction function and its operation will be described. FIG. 7 shows a read / write circuit 50b and an error correction circuit 50a corresponding to the local parity cell block.

  First, in writing local parity, DataP shown in FIG. 6 is input as data write signal DataP in synchronization with write timing signal WTE shown in FIG. The signal PWRT0 or PWRT1 for activating the write gate 53 is given by the combination of the inverter, NAND circuit and NOR circuit, and either the DP or / DP signal is dropped to the low level, and the first sense amplifier of the memory cell The data is written into the memory cell via 35.

  On the other hand, reading of the local parity value is the same as in FIG. As a result, the value stored in the cell is amplified and output as LP and / LP which are local parity signals.

  The error check circuit 57 performs local parity error check. This reads out the parity value written in the local parity cell last time, compares the value with DataP which is the result of the current parity calculation, and generates a local parity generation signal LPERR if they do not match.

  Next, error correction will be described. Data DataN sent from the read / write circuit 50 of FIG. 5 is input to the error correction circuit 50a. Further, an operation with the data stored in the global parity operation register 54 is performed by an exclusive OR circuit, and the result is sent to the global parity operation register 54 through the first shift register 56a. Here, when the data sent in sequence is processed and the processing of one column in the data memory cell block is completed, the result of the calculation is sent to the global parity storage register 54a, which is a global parity cell, via the second shift register 56b. Store the data. This data is a global parity value.

  After a series of processing ends, a reset signal GPRST is sent to the global parity calculation register 54 to perform calculation processing for the next column.

  To detect a global parity error, the global parity value stored in the global parity storage register 54a and the data sent to the global operation register 54 are calculated using an exclusive OR circuit. That is, if the two do not match, an error occurs.

  The result is stored in the global parity error status circuit 55. When a global parity error occurs, data in which Dn or Dn is inverted from DataN and / DataN is written in synchronization with the timing signal CWTE together with a signal indicating the local parity error LPERR, and error correction is performed. The occurrence of a global parity error is controlled by a timing signal GPCCHECK.

  In this embodiment, the refresh cycle is used to calculate and store local parity and global parity, and to perform error correction internally when the calculation result and the stored result do not match.

  FIG. 8 is a conceptual diagram for explaining the error correction operation in this embodiment. The horizontal axis represents time (time), and the vertical axis represents a refresh address or an error occurrence address. In order to make the explanation easy to understand, the addresses are only 0 to 3, and the time axis which is the horizontal axis is set to 1 for the refresh interval. The white circles ○ and black circles ● in the figure indicate the refresh operation time and its address.

  As the refresh operation step S1, address 0 is refreshed at time 0, address 1 is refreshed at time 1, and thereafter, refresh is repeated in the order of addresses. The Δ mark at time 3 indicates the time when the soft error occurred and its address.

  When a soft error occurs, the occurrence of a local parity error is detected during the refresh operation at time 5 in the refresh operation step S2 starting from time 4. Subsequently, occurrence of a global parity error is detected at the end of the refresh operation step S2 at time 7.

  Further, this global parity error is held, and the occurrence of a local parity error is detected at the time of refresh at time 9 in the refresh operation step S3. At this time, the error correction is performed by combining the local parity error and the global parity error. Thereafter, at the end of the refresh operation step S3, the global parity error is reset. At this stage, the normal state without error is restored.

  After that, when a soft error occurs again at the time Δ, the error can be corrected by the procedure after the refresh operation step S4 as in the case of the soft error at time 3.

  When this is compared to the actual time axis in the embodiment of FIG. 2, every time a refresh command is received, 32-bit cell data is read, local parity cell calculation and global parity calculation are performed, and the refresh rule is defined. Is 8,192 times / 64 milliseconds, it takes 8.192 seconds to refresh a 32-Mbit cell array once. Therefore, an error with a frequency of 1 bit can be corrected in twice that of 16.384 seconds.

  For example, when screening a cell that is vulnerable to a soft error with a low occurrence frequency of several hours / bit or less, it is necessary to use the test apparatus for several hours to several days or more, resulting in an increase in test cost. In the present invention, these error cells are automatically relieved in the DRAM, so that the number of defective products can be reduced, the test cost can be reduced, and the reliability can be improved.

  FIG. 9 shows the number of memory cell blocks in the column direction of FIG. 2 increased from 33 (32 + 1) to 65 (64 + 1). Even in this case, the only block added for error correction is the local parity cell block 22, and the area increase rate is small. For example, if the memory cell area without the soft error correction function is 100%, the area increase rate in the soft error correction method of FIG. 2 is 33/32 = + 13.1250%, and the area in the soft error correction method of FIG. The increase rate is 65/64 = + 1.5625%.

  Thus, in the case of the present invention, as the number of memory cell blocks in the column direction increases, the area increase required for incorporating the error correction function decreases.

1 is a block diagram showing the basic principle of a first embodiment of a semiconductor memory device according to the present invention. FIG. 5 is a block diagram generally showing a memory cell array and main peripheral circuits in a second embodiment of the semiconductor memory device according to the present invention. FIG. 6 is a circuit diagram of a data cell array portion in a second embodiment of the semiconductor memory device according to the present invention. FIG. 6 is a circuit diagram of a parity cell array portion in a second embodiment of the semiconductor memory device according to the present invention. FIG. 6 is a circuit diagram showing a read / write circuit and an error correction circuit connected to a data cell array portion in a second embodiment of the semiconductor memory device according to the present invention. FIG. 6 is a circuit diagram showing a parity operation circuit in a second embodiment of the semiconductor memory device according to the present invention. FIG. 6 is a circuit diagram showing a read / write circuit and an error correction circuit connected to a parity cell array portion in a second embodiment of the semiconductor memory device according to the present invention. The conceptual diagram which shows the timing of the refresh operation and error correction in the 2nd Example of the semiconductor memory device by this invention. FIG. 3 is a block diagram showing a memory cell array and main peripheral circuits when the number of blocks in the column direction is increased with respect to the invention of FIG. 2 according to the present invention. The block diagram which shows the memory cell array and main peripheral circuit which use the conventional correction system.

Explanation of symbols

10, 20 Memory cell array 11, 31 Data memory cell 12 Local parity cell 13, 23 Row decoder 14, 24 First sense amplifier 15, 25 Read / write circuit and error correction circuit 16, 26 Parity operation circuit 17, 27 Column decoder 18 Error cell 18a Local parity cells 18b and 28b in which an error is detected Read / write circuit and error correction circuit 21 and 30 in which an error is detected Data memory cell block 22 Local parity cell block 28 Data memory cell block 28a including error cells Detected local parity cell block 32 Transistor 32a Capacitor 33 Row selection line 34 Bit line 35 First sense amplifier and precharge circuit 36 In-block data bus 37 Column selection line 38 Data selection line 39 Data bus 30a Local parity memory cell block 31a Local parity cells 50, 50b Read / write circuit 50a Error correction circuit 51 Data bus 52 Second sense amplifier circuit 53 Write gate 54 Global parity operation register 54a Global parity storage Register 55 Global parity error status circuit 56a First shift register 56b Second shift register 60 Parity operation circuit 61 Operation circuit unit 62 Local parity operation data 70 Additional cell block for parity

Claims (5)

A memory cell array in which memory cells are arranged in a row direction and a column direction, a row decoder circuit, a column decoder circuit, a sense amplifier corresponding to the memory cells in the column direction, and a read / write circuit corresponding to the memory cells in the column direction Equipped,
Arithmetic means for calculating the parity value of each row and the parity value of each column in the memory cell array;
Storage means for storing the parity value;
Check means for checking the occurrence of a parity error with respect to the parity value;
Identification means for identifying the memory cell in which the error has occurred, based on the row and column information in which the parity error has occurred;
And a correction means for correcting the memory cell in which an error has occurred.   A local memory cell that stores the parity value of each row as a part of the memory cell array, and a global memory cell that stores a parity value of each column as a part of the error-correction circuit. The semiconductor memory device according to claim 1. Memory cell array (m, n, M, N is a positive integer) having a block configuration in which memory cell blocks having memory cells in m rows and n columns are arranged in M rows and N columns, a row decoder circuit, and a column decoder A circuit, a sense amplifier corresponding to the memory cell in the column direction of the memory cell block, and a read / write circuit arranged for each block column of the block configuration,
Arithmetic means for calculating a parity value of m rows and n columns of memory cells common in each memory cell block, and a parity value of the memory cells arranged in the memory cell block of the block column;
Storage means for storing the parity value;
Check means for checking the occurrence of a parity error with respect to the parity value;
Identification means for identifying the memory cell in which the error has occurred based on the row and column information of the memory cell block in which the parity error has occurred, and the row and column information in the memory cell block;
A semiconductor memory device, comprising: correction means for correcting the memory cell in which an error has occurred.   The memory cell block further includes m rows and n columns of local memory cells that store parity values of m rows and n columns of memory cells common in each memory cell block, and the (N + 1) th row of memory cell blocks, and 4. The semiconductor memory device according to claim 3, further comprising a global memory cell that stores a parity value of the memory cell arranged in the memory cell block of the block column as part of an error correction circuit. .   The calculation of the parity value, the occurrence of the parity error, the identification of the memory cell in which the error has occurred, and the correction of the memory cell in which the error has occurred are performed when the memory cell is refreshed. The semiconductor memory device according to claim 1.

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