JP2005202430A - Liquid crystal drive circuit and load drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal driving circuit capable of reducing power consumption and a load driving circuit capable of reducing settling time.
The present invention includes a shift register, a data latch circuit, a load latch circuit, a level shifter, a decoder, an output selection circuit, a bleeder, and a buffer amplifier. Yes. Since the number of driving of the flip-flop in the amplifier enable circuit 25 and the latch unit in the data latch circuit 2 is switched according to the number of gradations, power is not consumed by unnecessary flip-flops and the power consumption can be reduced. The buffer amplifier 6 is composed of a two-stage amplifier, and a resistor and a switch are connected in series between the output terminal of the buffer amplifier 6 and each load. As a result, the time constant becomes constant even when the load amount fluctuates, the settling time is shortened, and stable operation is possible.
[Selection] Figure 1

Description

  The present invention relates to a liquid crystal driving circuit capable of gradation display and a load driving circuit for selectively driving a capacitive load.

  Since the cellular phone is limited in space, a large-capacity battery cannot be mounted, and it is necessary to reduce the power consumption of the circuit inside the phone as much as possible. On the other hand, mobile phones equipped with color liquid crystal panels have been increasing.

  A conventional source driver IC for driving a liquid crystal panel includes a buffer amplifier for each signal line in the panel. For this reason, in a source driver IC having m drive output terminals, m (for example, 384 and 420) buffer amplifiers are always operated, causing an increase in power consumption.

  FIG. 11 is a block diagram showing a schematic configuration of such a conventional signal line driving circuit. The signal line driver circuit of FIG. 11 shifts the shift pulse supplied from the outside in order in synchronization with the transfer clock, and the digital signal in synchronization with the shift pulse output from each output terminal of the shift register 1. A plurality of data latch circuits 2 for latching key data, a load latch circuit 3 for latching outputs of the plurality of data latch circuits 2 at the same timing, a level shifter 4 for converting the level of the output of the load latch circuit 3, and a level shifter 4 A D / A converter 5 for outputting an analog voltage corresponding to the output of the output, a buffer amplifier 6 for buffering the output of the D / A converter 5, and a bleeder 7 for generating an analog reference voltage corresponding to digital gradation data. The output of the buffer amplifier 6 is supplied to each signal line.

  In brief, the bleeder 7 generates an analog reference voltage by dividing an external voltage and a ground voltage by a plurality of resistance elements connected in series.

JP-A-11-150427

As described above, in the conventional signal line driving circuit shown in FIG. 11, as one method that can solve the problem of increased power consumption, an analog reference voltage is supplied instead of providing a buffer amplifier for each signal line. A method of providing a buffer amplifier for each reference voltage line has been proposed. In this case, if the number of gradations is n, it is sufficient to provide 2 ⁿ buffer amplifiers, and the number of buffer amplifiers can be greatly reduced as compared with the case where a buffer amplifier is provided for each signal line. Reduction can be achieved.

  As described above, when a buffer amplifier is provided for each of the reference voltage lines that supply the analog reference voltage, the buffer amplifier 6 is generally configured by an operational amplifier 11 including two stages of amplifiers. In order to improve the stability, as shown in FIG. 12A, the output terminal of the operational amplifier 11 at the subsequent stage is fed back to the input terminal via the capacitor element C10 to secure a phase margin by mirror compensation. Yes. Alternatively, as in the circuit of FIG. 13A proposed in Patent Document 1, phase compensation is performed by using a zero point based on a resistor Rz and a load capacitance CL connected in series to the output to ensure a phase margin.

In the circuit of FIG. 12A, as shown in the frequency characteristic diagram of FIG. 12B, the second pole appearing in the open loop frequency characteristic is the transconductance g _m2 of the second gain stage. It depends on the frequency g _m2 / C _L determined by the load capacity C _L. Note that the phase rotates 90 degrees per pole.

In the case of the circuit of FIG. 12A, as the load capacity increases, the frequency of the second pole decreases as g _m2 / (m · C _L ) in accordance with the number m of loads to be driven. In the case of a capacitor, there is a problem that the phase is rotated from a low frequency to reduce the phase margin, and when m is large, the phase margin is lost and oscillation is likely to occur.

On the other hand, in the circuit of FIG. 13A, as shown in the frequency characteristic diagram of FIG. 13B, the frequency of the second pole is common even when the load changes, but the frequency of the first pole. And the frequency of the zero point changes according to the load. Further, the circuit of FIG. 13 (a), the greater the number of loads increases, the low-pass characteristic which is formed by the resistor Rz and the load capacitance m · C _L, waveform rounding, occurs a problem that the settling time becomes longer .

  The present invention has been made in view of such a point, and an object thereof is to provide a liquid crystal driving circuit capable of reducing power consumption. Another object is to provide a load driving circuit capable of shortening the settling time.

  According to one aspect of the present invention, in a load driving circuit that selectively drives m (m is an integer of 1 or more) loads based on the output of an operational amplifier, the connection between each of the loads and the operational amplifier A switch for switching whether or not to cut off the path, an impedance element connected to a path from the output terminal of the operational amplifier through the switch to the m loads, and an output terminal of the operational amplifier in series A pseudo-impedance element, a pseudo switch, and a pseudo-capacitor element to be connected, and the product of the impedance of the pseudo-impedance element and the capacitance of the pseudo-capacitor element is the product of the impedance of the impedance element and the capacitance of the load. Make approximately equal.

  According to the present invention, since the impedance element is connected between the output terminal of the operational amplifier and each load, the stability can be maintained even when the load amount increases or decreases, and the waveform is rounded. Since it is suppressed, the settling time can be shortened.

  Hereinafter, the liquid crystal drive circuit and the load drive circuit according to the present invention will be specifically described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a liquid crystal driving circuit according to the present invention, and shows a configuration of a signal line driving unit. In FIG. 1, the same reference numerals are given to components common to FIG. 11, and different points will be mainly described below.

  As in FIG. 11, the liquid crystal drive circuit of FIG. 1 includes a shift register 1, a data latch circuit (first latch circuit) 2, a load latch circuit (second latch circuit) 3, a level shifter 4, a decoder 21, and the like. , An output selection circuit 22, a bleeder (reference voltage generation circuit) 7, and a buffer amplifier 6.

  The buffer amplifier 6, the bleeder 7, the decoder 21 and the output selection circuit 22 constitute the D / A converter 5.

  For example, as shown in FIG. 2A, the bleeder 7 divides the power supply voltage and the ground voltage by a plurality of resistors and outputs an analog reference voltage. Alternatively, as shown in FIG. 2B, at least a part of the analog reference voltage may be supplied from the outside via the buffers 31, 32 and the like.

  In addition, the liquid crystal driving circuit of FIG. 1 includes a gradation data use determination circuit 23 that determines the type of digital gradation data, and a gradation mode circuit 24 that controls the data latch circuit 2 and the like based on the gradation mode signal. The amplifier enable circuit 25 is provided.

FIG. 3 is a circuit diagram showing a detailed configuration of the gradation data use determination circuit 23. As shown in the figure, the gradation data use determination circuit 23 includes 2 ⁶ = 64 logic determination circuits 23 ₁ to 23 ₆₄ . Each logic determination circuit 23 ₁ to 23 ₆₄ includes three 6-input NAND gates G1, G2, and G3, a 3-input NAND gate G4, two NOR gates G5 and G6, and an inverter IV1. The output of the 3-input NAND gate G4 is held by NOR gates G5 and G6.

The gradation data use determination circuits 23 ₁ to 23 ₆₄ have 6-bit digital gradation data of (0,0,0,0,0,0) to (1,1,1,1,1,1). Is equal to RGB 6-bit signals RED [0: 5], GREEN [0: 5], and BLUE [0: 5] are input to the 6-input NAND gate, respectively. If at least one of these three types of 6-bit signals becomes (0,0,0,0,0,0), the output of the logic judgment circuit 23 ₁ becomes “1”.

Similarly, if at least one of RGB 6-bit digital gradation data is (0,0,0,0,0,1), the output of the logic determination circuit 23 ₂ is “1”. Further, if at least one of the RGB of 6-bit digital gray scale data is (1,1,1,1,1,1), the output of the logic decision circuit 23 ₆₄ is "1".

  The gradation mode circuit 24 in FIG. 1 determines the number of gradations by generating an n-bit discrimination signal based on a gradation mode signal supplied from the outside. As an example of the gradation mode, for example, in the case of a liquid crystal driving circuit for a mobile phone, there are a multi-gradation mode during normal use and a low gradation mode during standby.

  The output of the gradation mode circuit 24 is supplied to a plurality of data latch circuits 2 and an amplifier enable circuit 25. Each of the data latch circuits 2 has a latch unit for the maximum number of gradations, and each latch unit corresponds to an n-bit discrimination signal that is an output of the gradation mode circuit 24, that is, according to the number of gradations. Set to enabled or disabled.

  Specifically, as the number of gradations increases, the number of latch units in the data latch circuit 2 that is enabled increases, and as the number of gradations decreases, the number of latch units in the data latch circuit 2 that becomes enabled. Decrease. As a result, when the number of gradations is small, the number of latch units that are enabled is reduced to reduce power consumption.

The amplifier enable circuit 25 includes a plurality of flip-flops 31 that can latch the outputs OUT [0: 2 ⁿ −1] of the gradation data use determination circuit 23, as shown in detail in FIG. These flip-flops 31 latch the output of the gradation data use determination circuit 23 in synchronization with the shift pulse output from the last register of the shift register 1. Instead of synchronizing with the shift pulse output from the last register of the shift register 1, the output of the gradation data use determination circuit 23 is latched using the load signal input to the load latch circuit 3. A synchronization signal may be generated.

A signal k [0: 2 ⁿ −1] is supplied from the gradation mode circuit 24 to the set terminal or reset terminal of each flip-flop 31. Depending on the logic of the signal k [0: 2 ⁿ -1], the number of flip-flops 31 that are enabled changes according to the number of gradations.

The flip-flop 31 in the enabled state latches the corresponding output (any one of OUT [0: 2 ⁿ -1]) of the gradation data use determination circuit 23 in synchronization with the clock PLS. It is supplied to the enable terminal of the corresponding buffer amplifier 6.

  When the number of gradations decreases, some bits constituting the digital gradation data supplied to the gradation data use determination circuit 23 from the outside are fixed to a predetermined logic. Accordingly, the gradation data use determination circuit 23 whose detailed configuration is shown in FIG. 3 can accurately determine the type of digital gradation data even in the low gradation mode.

  Specifically, based on the output of the gradation mode circuit 24, the output of the logic determination circuit 23 corresponding to the flip-flop circuit 31 in FIG. Regardless, the logic of some bits is fixed so as to be “0”.

  FIG. 5 is a circuit diagram showing an example of the configuration of the buffer amplifier 6. As shown in the figure, the buffer amplifier 6 has a configuration in which a first amplifier 41 that drives on the high voltage side and a second amplifier 42 that drives on the low voltage side are connected in parallel. Both the first and second amplifiers 41 and 42 have a voltage follower configuration in which the output is fed back to the input side.

  In addition, the first and second amplifiers 41 and 42 can select enable / disable by AND gates G7 and G8 based on the logic of the output ENB of the amplifier enable circuit 25 and the polarity selection signals V0N and V0P. ing. That is, only one of the first and second amplifiers 41 and 42 can be operated by setting one of the polarity selection signals V0N and V0P to a high level.

  As shown in FIG. 5, the reason for providing the two amplifiers 41 and 42 is to reduce the output amplitude of one amplifier to reduce the power consumption. May be configured.

In FIG. 5, the signal IN input to the first and second amplifiers 41 and 42 is the same as REF [0: 2 ⁿ −1] in FIG. 4 and is an analog reference voltage output from the bleeder 7.

  Next, the operation of the liquid crystal display circuit of FIG. 1 will be described. In the following, the operation when the liquid crystal driving circuit is built in a driving IC (hereinafter referred to as a source driver) will be described.

  FIG. 6 is a block diagram showing the entire configuration of the liquid crystal display device, and shows an example in which all signal lines of the liquid crystal panel are driven using a plurality of source drivers incorporating the liquid crystal drive circuit of FIG. The liquid crystal display device of FIG. 6 includes a liquid crystal panel LCDP in which signal lines and scanning lines are arranged, a plurality of source drivers SD1 to SDq (q is an integer of 1 or more), each driving a plurality of signal lines, and Includes a plurality of gate drivers GD1 to GDp (p is an integer of 1 or more) for driving a plurality of scanning lines, and a controller CTRL for controlling the source drivers SD1 to SDq and the gate drivers GD1 to GDp.

  The source drivers SD1 to SDq are supplied with the clock CPH1 output from the controller CTRL and the input signal DI / O11, and output voltage signals necessary for driving the signal lines of the liquid crystal panel LCDP. The gate drivers GD1 to GDp are supplied with the clock CPH2 output from the controller CTRL and the input signal OI / O21, and output a voltage signal necessary for driving the gate line of the liquid crystal panel LCDP. Each of the source drivers SD1 to SDq drives a part of the signal lines (hereinafter referred to as blocks) in the horizontal direction of the liquid crystal panel LCDP in a line sequential manner.

  The gradation data use determination circuit 23 in FIG. 1 determines the type of external digital gradation data in units of m data to be input within a predetermined period and output to m output terminals. A signal indicating whether to drive the buffer amplifier 6 is supplied to the amplifier enable circuit 25.

As shown in FIG. 4, the amplifier enable circuit 25 converts the signal OUT [0: 2 ⁿ −1] from the gradation data use determination circuit 23 into the shift pulse output from the last register in the shift register 1. Synchronized and supplied to the buffer amplifier 6. Alternatively, the synchronization signal may be generated based on the load signal.

  As a result, only the buffer amplifier 6 related to the m digital gradation data is enabled, and the power consumption can be reduced.

On the other hand, the gradation mode circuit 24 determines the number of gradations based on a gradation mode signal supplied from the outside. An n-bit discrimination signal and a signal k [0: 2 ⁿ -1] from the gradation mode circuit 24 are supplied to the amplifier enable circuit 25 and the data latch circuit 2, respectively. The flip-flop and the data latch circuit 2 in the amplifier enable circuit 25 are switched between being enabled and disabled by a signal from the gradation mode circuit 24.

As described above, in the present embodiment, the drive number of the flip-flop in the amplifier enable circuit 25 and the latch unit of the data latch circuit 2 is switched according to the number of gradations. For example, when the number of gradations is set to k bits (1 ≦ k ≦ n−1), only the upper or lower k-bit latch unit of the data latch circuit 2 is detected by a signal from the gradation mode circuit 24. In operation, the amplifier enable circuit 25 enables the corresponding flip-flops 31 so that every 2 ^nk buffer amplifiers 6 are enabled. For this reason, there is no possibility that power is consumed by unnecessary flip-flops and buffer amplifiers, and power consumption can be reduced.

  The output of the buffer amplifier 6 is supplied to the output selection circuit 22. The output selection circuit 22 selects the output of the buffer amplifier 6 corresponding to the digital gradation data, and supplies the selected analog voltage to the signal line. At this time, the buffer amplifier 6 corresponding to the flip-flop 31 of the amplifier enable circuit 25 in the enabled state is also unrelated to the m digital gradation data, and the output “0” from the gradation data use determination circuit 23. Is input, the buffer amplifier 6 is disabled, and the power consumption is further reduced.

(Second Embodiment)
In the second embodiment, the settling time is shortened by devising the configuration around the buffer amplifier 6.

  Since the second embodiment is common to the first embodiment except for the configuration around the buffer amplifier 6, the description thereof is omitted.

  FIG. 7 is a circuit diagram showing a configuration around the buffer amplifier 6. When the buffer amplifier 6 is configured by the first and second amplifiers 41 and 42 as shown in FIG. 5, each of the first and second amplifiers 41 and 42 is configured as shown in FIG.

The buffer amplifier 6 shown in FIG. 7 has an operational amplifier including two-stage amplifiers 51 and 52, and resistors R _{1 to} R _N and switches SW ₁ to SW ₁ are connected between the output terminal of the amplifier 52 in the subsequent stage and each load. SW _N and the switch SW ₁ to SW _N that are connected in series corresponding to the analog switch (not shown) in the output selection circuit 22, the resistor R ₁ to R _N are the buffer amplifier 6 in FIG. 1 and the output selection circuit 22 The load capacitors CL1 to CLN are the load capacitances of the signal line, and are the total of the capacitance of the pixel TFT itself connected to the signal line, the liquid crystal capacitance, the auxiliary capacitance, and the like.

The switches SW _{1 to} SW _N are for switching the number of loads, and at least one of the switches SW _{1 to} SW _N is turned on. When the load is not connected, the buffer amplifier 6 is not affected by the load capacity of the path by cutting off the corresponding switches SW ₁ to SW _N.

In the following, the transconductances of the amplifiers 51 and 52 in the buffer amplifier 6 are (−g _m1 ) and (−g _m2 ), respectively, the output conductance of the amplifier input stage is g _o1 , and the output conductance of the amplifier output stage is g _o2 . The load capacity of each load is C _L1 , C _{L2 ,.}

FIG. 8 is a frequency characteristic diagram of the buffer amplifier 6 of FIG. 7. The solid line indicates the characteristic when only one load is provided, and the dotted line indicates the characteristic when the load is N. As shown in the figure, the frequency of the first pole (pole) of the open-loop frequency characteristic when there is only one load is g _o2 / C _L , the frequency of the second pole is g _o1 / C ₁ , and the zero point The frequency is 1 / (C _L · R).

When the number of loads is N, the frequency of the first pole is g _o2 / (N · C _L ), the frequency of the second pole is g _o1 / C ₁ , and the zero point frequency is 1 / (N · C _L · R / N).

As described above, when the load becomes N times, the load capacity also becomes N times. However, in the case of the buffer amplifier 6 of FIG. 7, since the resistors R _{1 to} R _N are provided corresponding to each load, the impedance is It becomes 1 / N times. As a result, the time constant is always a constant value C _L · R even when the load amount varies, and the zero point frequency is always constant regardless of the load amount.

  Further, since the frequency of the second pole does not fluctuate, the phase margin is ensured as compared with the conventional case.

  When the buffer amplifier 6 of this embodiment is compared with the conventional buffer amplifier 6 shown in FIG. 13A, when the load capacitance increases in the past, the time constant determined by the resistance Rz and the load capacitance becomes large, and the waveform becomes distorted. There was a problem of long settling time. On the other hand, in the present embodiment, since the time constant is constant even when the load capacity varies, the rounding of the waveform does not increase, so that the settling time does not increase.

In FIG. 7, resistors R _{1 to} R _N are connected between the output terminal of the buffer amplifier 6 and the switches SW _{1 to} SW _N , but the resistor R is connected between the switches SW _{1 to} SW _N and the load. it may be connected to ₁ to R _N.

(Third embodiment)
In the third embodiment, a dummy load circuit is added to the buffer amplifier 6 of the second embodiment.

FIG. 9 is a circuit diagram showing the configuration of the periphery of the buffer amplifier 6 of the third embodiment, in which a dummy load circuit 61 is added to the output terminal of the amplifier 52 in the subsequent stage of FIG. The dummy load circuit 61 includes a resistor Rd, the switch SW _d and the capacitor Cd is obtained by series connection.

In the case of the second embodiment, it is assumed that at least one of the switches SW _{1 to} SW _N connected to the load is turned on. However, if all the switches SW _{1 to} SW _N are turned off, the buffer amplifier 6 may become unstable and oscillate.

In contrast, the buffer amplifier 6 in Fig. 9, all connected switches SW ₁ to SW _N load is turned off, and turn on a switch SW _d of the dummy load circuit 61. If the time constant between the resistor Rd and the capacitor Cd in the dummy load circuit 61 is set to be equal to the time constant between the load capacitances C _{L1 to} C _LN and the resistors R _{1 to} R _N , the load other than the dummy load circuit 61 Similarly, the buffer amplifier 6 operates stably in the case where it is driven and in the case where the dummy load circuit 61 is driven.

Thus, according to the present embodiment, even if all the switches SW ₁ to SW _N are turned off, the stable operation is ensured by turning on the switch SW _d in the dummy load circuit 61.

(Fourth embodiment)
In the fourth embodiment, a common resistor is connected between the output of the buffer amplifier 6 and the resistor.

FIG. 10 is a circuit diagram showing a peripheral configuration of the buffer amplifier 6 according to the fourth embodiment. One end is connected to the output terminal of the buffer amplifier 6 and the other end is connected to the resistors R _{1 to} R _N. Rz. The common resistor Rz is smaller than the sum of the resistance values of the switches SW ₁ to SW _N ON resistance and the switch SW ₁ to SW _N connected to the resistor R ₁ to R _N, preferably switch SW ₁ to SW _N ON Has a resistance value smaller than the resistance.

  By providing such a common resistor Rz, the frequency of the zero point in the frequency characteristic diagram of FIG. 8 can be slightly lowered, and the frequency difference between the frequency of the second pole and the frequency of the zero point can be reduced. it can. Thereby, the phase margin when the gain is 1 is increased, and more stable operation is possible.

  If the resistance value of the common resistor Rz is too large, the waveform becomes distorted and the settling time becomes longer as in the circuit of FIG. 13A. Therefore, the resistance value of the common resistor Rz is small as described above. It is desirable to do.

  10 shows an example in which the common resistor Rz is added to the configuration of FIG. 7, the common resistor Rz may be added to FIG. 9.

1 is a block diagram showing a schematic configuration of an embodiment of a liquid crystal driving circuit according to the present invention. The circuit diagram which shows the detailed structure of a bleeder. The circuit diagram which shows the detailed structure of a gradation data use determination circuit. The circuit diagram which shows the detailed structure of an amplifier enable circuit. The circuit diagram which shows the structure of a buffer amplifier. 1 is a block diagram illustrating an overall configuration of a liquid crystal display device. FIG. 3 is a circuit diagram showing a configuration around a buffer amplifier. The frequency characteristic figure of the buffer amplifier of FIG. FIG. 5 is a circuit diagram showing a configuration around a buffer amplifier according to a third embodiment. FIG. 9 is a circuit diagram showing a configuration around a buffer amplifier according to a fourth embodiment. The block diagram which shows schematic structure of the conventional signal line drive circuit. The circuit diagram around the conventional buffer amplifier and its frequency characteristic diagram. The circuit diagram around the conventional buffer amplifier and its frequency characteristic diagram.

Explanation of symbols

1 shift register 2 data latch circuit 3 load latch circuit 4 level shifter 5 D / A converter 6 buffer amplifier 7 bleeder 21 decoder 22 output selection circuit 23 gradation data use determination circuit 24 gradation mode circuit 25 amplifier enable circuit

Claims (4)

In a load driving circuit for selectively driving m (m is an integer of 2 or more) loads based on the output of an operational amplifier,
A switch for switching whether or not to cut off a connection path between each of the loads and the operational amplifier;
An impedance element connected to a path from the output terminal of the operational amplifier through the switch to the m loads. In a load driving circuit for selectively driving m (m is an integer of 1 or more) loads based on the output of an operational amplifier,
A switch for switching whether or not to cut off a connection path between each of the loads and the operational amplifier;
Impedance elements respectively connected on a path from the output terminal of the operational amplifier through the switch to the m loads;
A pseudo impedance element, a pseudo switch and a pseudo capacitor element connected in series to the output terminal of the operational amplifier,
A load driving circuit, wherein a product of an impedance of the pseudo-impedance element and a capacitance of the pseudo-capacitor element is substantially equal to a product of an impedance of the impedance element and a capacitance of the load.   3. The load drive circuit according to claim 1, further comprising a common impedance element, one end of which is connected to an output terminal of the operational amplifier on the path and is provided in common to the m loads. .   The load drive circuit according to claim 3, wherein an impedance value of the common impedance element is smaller than a sum of an impedance value of the impedance element and an ON resistance of the switch.

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