JP2005204091A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem, wherein in a conventional PLL for use in control of a pulse-width modulation type converter apparatus, phase control cannot adapt quickly to the rapid fluctuations with respect to the frequency of a system power source. <P>SOLUTION: A PLL circuit is provided with a phase comparison circuit for detecting lagging or leading the phase differences; a phase integration circuit which counts up or down at each one cycle in a lagging or leading phase, accumulates the counted values, and converts the accumulated values into an analog voltage; and a voltage-controlled oscillation circuit for controlling an output frequency according with the analog voltage. In this PLL circuit, phase integration circuit is replaced by a phase proportional integration circuit, phase difference is converted into a numerical value by each cycle detected by the phase comparison circuit; and the converted numerical value is set to a positive value for the lagging phase and a negative value for the leading phase, the converted positive numerical value or negative value is multiplied by proportional gain coefficients to obtain a proportional value, a value which is obtained by multiplying the converted value by the integral gain coefficients is accumulated to obtain an integral value, the proportional value is added to the integral value to obtain a proportional integral value, and the proportional integral value is converted into an analog voltage. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a PLL (phase control) circuit used for frequency control of a carrier generator of a pulse width modulation type inverter device.

  FIG. 9 is a block diagram of a conventional PLL circuit. In FIG. 9, the phase comparison circuit PF detects the phase difference between the reference frequency signal Fi and the feedback frequency signal Fo / N, and outputs the phase comparison signal Ud at the low level when the feedback frequency signal Fo / N is in a delayed phase. When the feedback frequency signal Fo / N is in a leading phase, the phase comparison signal Ud is set to a high level and output.

  The phase integration circuit is formed by a count circuit CO and a DA conversion circuit, and the count circuit CO counts up every period when the phase comparison signal Ud is a low-level delay phase and 1 when the phase is a high-level advance phase. It counts down every period and accumulates and outputs the values counted up or down. The DA converter circuit converts the accumulated value into an analog voltage signal and supplies the analog voltage signal as a control voltage Vct to the voltage controlled oscillation circuit VCO. The voltage controlled oscillation circuit VCO controls the output frequency Fo according to the control voltage Vct. The frequency dividing circuit 1 / N divides the output frequency Fo and supplies it to the phase comparison circuit PF as a feedback frequency signal Fo / N.

  When the reference frequency signal Fi has a delayed phase, the count value of the count circuit CO is initially small, and therefore the control voltage of the DA converter circuit is also low. The count circuit CO counts up and accumulates after detecting a phase difference between the reference frequency signal Fi and the feedback frequency signal Fo / N for each period when the phase comparison signal Ud is at a low level, and the phase comparison signal Ud is high. Continue counting up until reaching level.

  When the count circuit CO exceeds a predetermined target cumulative value, the count circuit CO outputs the phase comparison signal Ud at a high level. In this way, in a stable state, the counter circuit CO reciprocates two count values with count-up or count-down across the target cumulative value. (Refer to Patent Document 1 disclosing the above-mentioned conventional technology)

Japanese Patent Laid-Open No. 4-196715

  In a conventional PLL circuit used for frequency control of a carrier generator of a pulse width modulation type inverter device, a phase difference between a reference frequency signal and a feedback frequency signal is generated in a pulse signal, and the pulse signal is formed by a resistor and a capacitor. Is integrated by a low-pass filter (LPF), and the output frequency is changed in accordance with the integrated value. However, it is necessary to narrow the band of the low-pass filter, and a sudden reference frequency signal is generated. There was a problem that could not cope with the fluctuations. A method for solving the above problem is disclosed in Japanese Patent Laid-Open No. 4-196715. The above technique is effective for a CD player, a BS tuner, or the like in which the reference frequency signal is used at a high frequency. When the reference frequency signal used for controlling the apparatus is a low frequency of 50 Hz or 60 Hz of the system power supply, it cannot cope with a sudden change in the reference frequency signal and repeats unevenness with respect to the target value.

  In order to solve the above-described problem, the first invention detects a phase difference between a reference frequency signal and a feedback frequency signal, and detects a delayed phase difference when the feedback frequency signal is delayed in phase from the reference frequency signal. When the phase of the feedback frequency signal is advanced from that of the reference frequency signal, a phase comparison circuit that detects and outputs an advanced phase difference and counts every cycle when the detected phase difference is a delayed phase difference. On the contrary, when the detected phase difference is the leading phase, it counts down every cycle and continues counting up or down until the delayed phase difference or leading phase difference disappears, and converts the counted value into an analog voltage signal Output phase integration circuit, a voltage controlled oscillation circuit for controlling the output frequency in accordance with the converted analog voltage signal, and the output frequency in advance. In a PLL circuit having a frequency dividing circuit that divides the frequency into a predetermined value and outputs it as a feedback frequency signal, the phase integrating circuit is replaced with a phase proportional integrating circuit, and the replaced phase proportional integrating circuit is the phase comparing circuit. When the phase difference for each period between the reference frequency signal and the feedback frequency signal detected by (1) is a lagging phase, the numerical value is converted to a positive value, and when the phase difference is a leading phase, the numerical value is converted to a negative value. The proportional value is calculated by multiplying the converted positive or negative numerical value of the phase difference for each period by a predetermined proportional gain coefficient, and the positive or negative numerical value of the phase difference for each period after the numerical conversion is determined in advance. The integral value is multiplied and the multiplied value is accumulated to calculate an integral value. The calculated proportional value and the integral value are added to calculate a proportional integral value. Analog voltage signal A PLL circuit and converting and outputting.

  In the second invention, the proportional gain coefficient Kp of the proportional integration circuit is set by Kp = (20 to 35) / F [MHz], and the integral gain coefficient Ki is set to Ki = (5 to 15) / F [MHz]. The PLL circuit according to claim 1, wherein the PLL circuit is set by:

  According to a third aspect of the present invention, a phase difference correction limiting circuit is provided between the proportional integration circuit and the voltage controlled oscillation circuit, and a predetermined proportional integral upper limit value and proportional integral lower limit value are set in the phase difference correction limit circuit. When the proportional integral value exceeds the set proportional integral upper limit value, the proportional integral upper limit value is output as the proportional integral signal, and when the proportional integral value is less than the set proportional integral lower limit value, the proportional integral lower limit value is output. A value is output as the proportional integral signal, and the proportional integral value is output to the voltage controlled oscillation circuit when the proportional integral value is less than the set proportional integral upper limit value and greater than or equal to the proportional integral lower limit value. A PLL circuit according to claim 1 or 2.

  According to the first invention and the second invention, the conventional low-pass filter (LPF) is used by using PI control in the PLL circuit used for controlling the pulse width modulation type inverter device of the system power supply. Responsiveness of phase control can be increased with respect to the PLL circuit. Furthermore, phase control can be performed in a wide range of the reference frequency signal from a high frequency region to a low frequency region.

  According to the third invention, the output frequency can be prevented from greatly deviating from an appropriate value with respect to a sudden change in the reference frequency signal, and the frequency of the switching element of the pulse width modulation type inverter device exceeds the appropriate value. The destruction of the switching element which arises can be prevented. In addition, the tracking range of the phase control frequency is limited, and the phase control response can be increased.

[Embodiment 1]
Hereinafter, an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a PLL circuit of the present invention used for control of a pulse width modulation type inverter apparatus, and includes a phase comparison circuit PFD, a phase proportional integration control circuit, a phase difference correction control circuit REC, and a voltage control oscillation circuit VCO. The phase proportional integration control circuit is formed by a phase difference count circuit PCO and a proportional integration control circuit PI (hereinafter referred to as a PI control circuit).

  FIG. 2 is a detailed circuit diagram of the phase comparison circuit PFD shown in FIG. As illustrated, the phase comparison circuit PFD is formed by a first D flip-flop FF1, a second D flip-flop FF2, and an AND circuit AND. The input terminal D of the first D flip-flop FF1 is connected to the power supply voltage. When the reference frequency signal Fi is input to the clock input terminal CK, the delayed phase difference signal Fup is output from the output terminal Q. The input terminal D of the second D flip-flop FF2 is connected to the power supply voltage. When the feedback frequency signal Fo / N is input to the clock input terminal CK, the lead phase difference signal Fdo is output from the output terminal Q. .

  The AND circuit AND is a two-input AND gate, and a delayed phase difference signal Fup and a lead phase difference signal Fdo are input to two input terminals, respectively. The output signal Ad of the AND circuit AND is supplied as a reset signal to the input terminals R of the first D flip-flop FF1 and the second D flip-flop FF2. As described above, the phase comparison circuit PFD detects a phase difference for each cycle between the reference frequency signal Fi and the feedback frequency signal Fo / N, and outputs it as a delayed phase difference signal Fup or an advanced phase difference signal Fdo.

  FIG. 3 is a detailed circuit diagram of the phase difference count circuit forming the phase proportional integration circuit. As shown in the figure, it is formed by an up / down counter circuit UDC, a reset generation circuit RS, and a register circuit LD. The up / down counter circuit UDC is also referred to as a reversible counter, and operates as a count-up during a period in which the delayed phase difference signal Fup that is an input signal of the input terminal UP is at a high level, and a pulse of the clock signal Clk having a predetermined period is generated. Each time it is applied to the input terminal CK, it is incremented by one. Further, while the lead phase difference signal Fdo, which is an input signal of the input terminal DO, is in a high level period, it operates as a countdown, and is decremented by 1 every time a pulse of the clock signal Clk is applied to the input terminal CK, and is changed at every cycle. Count up or down the phase difference.

  The reset generation circuit RS operates when the input terminal D is switched from the High level to the Low level, and generates a reset signal Rs for a predetermined period in synchronization with the clock signal Clk input to the input terminal CK. / Supplied to the input terminal R of the down counter circuit UDC and the input terminal WE of the register circuit LD shown below.

  The register circuit LD converts the count-up or count-down value for each period counted by the up / down counter circuit UDC into a positive value or a negative value and holds it. When the reset signal Rs is input to the input terminal WE, The value that is converted and held is output as the phase difference count signal Pc. Then, the count-up or count-down value of the next one cycle is converted into a numerical value and held.

  FIG. 4 is a detailed circuit diagram of the PI control circuit forming the phase proportional integration circuit. The phase difference count signal Pc and the clock signal Clk, which are numerically converted as shown in the figure, are inputted, and a coefficient Kp of a predetermined proportional gain is inputted. And a predetermined integral gain coefficient Ki, and a proportional value is obtained by multiplying the value of the phase difference count signal Pc for each period by the proportional gain coefficient Kp according to the PI control equation shown in FIG. Calculate, multiply the value of the phase difference count signal Pc for each period by the integral gain coefficient Ki, accumulate the multiplied values, calculate an integral value, and add the calculated proportional value and integral value Then, a proportional integral value for each cycle is obtained and output as a proportional integral signal Pi.

  FIG. 5 is a detailed circuit diagram of the phase difference correction limiting circuit REC shown in FIG. 1. As shown in the figure, the proportional integration upper limit setting circuit HRF, the proportional integration lower limit setting circuit LRF, the comparison discriminating circuit DC, the multiplexer circuits MS and DA It is formed by a conversion circuit D / A. The proportional integral upper limit setting circuit HRF sets a predetermined proportional integral upper limit set value Hr, and the proportional integral lower limit setting circuit LRF sets a predetermined proportional integral lower limit set value Lr.

  The comparison discriminating circuit DC compares the value of the proportional integral signal Pi with the proportional integral upper limit set value Hr and the proportional integral lower limit set value Lr, and when the value of the proportional integral signal Pi exceeds the proportional integral upper limit set value Hr An output signal D1 is output, and when the value of the proportional integral signal Pi is equal to or less than the proportional integral upper limit set value Hr and greater than or equal to the proportional integral lower limit set value Hr, the output signal D2 is output, and the value of the proportional integral signal Pi Is less than the proportional integral lower limit set value Lr, the output signal D3 is output.

  The multiplexer circuit SE selects the proportional integration upper limit set value Hr when the output signal D1 from the comparison discriminating circuit DC is input, selects the proportional integration signal Pi when the output signal D2 is input, and receives the output signal D3. Then, the proportional integration lower limit set value Lr is selected and input to the DA converter circuit D / A. The DA conversion circuit D / A converts the value of the proportional-integral signal Pi that has been numerically converted into an analog voltage signal and outputs it as a phase difference correction signal Re.

  The voltage controlled oscillation circuit VCO controls the output frequency Fo according to the value of the phase difference correction signal Re converted to an analog voltage, and the frequency dividing circuit 1 / N divides the output frequency Fo to a predetermined value. And output as a feedback frequency signal Fo / N.

  The operation of the present invention will be described with reference to the waveform timing chart of FIG. 6A shows the clock signal Clk having a predetermined frequency, FIG. 6B shows the reference frequency signal Fi, FIG. 6C shows the feedback frequency signal Fo / N, and FIG. ) Indicates an AND signal Ad. 6E shows the delayed phase difference signal Fup, FIG. 6F shows the advanced phase difference signal Fdo, FIG. 6F shows the reset signal Rs, and FIG. 6G shows the up / down counter. The signal Cd is shown, and FIG. 6 (H) shows the numerically converted phase difference count signal Pc.

  At time t = t1 shown in FIG. 6B, when the reference frequency signal Fi becomes high level, the clock input terminal CK of the first D flip-flop FF1 becomes high level and is output from the output terminal Q (FIG. The delayed phase difference signal Fup shown in E) is set to High level and output.

  At time t = t2 shown in FIG. 6C, when the feedback frequency signal Fo / N becomes High level, the clock input terminal CK of the second D flip-flop FF2 shown in FIG. 2 becomes High level, and the output terminal Q Is output at a high level. The AND circuit AND receives the delayed phase difference signal Fup and the output signal of the output terminal Q of the second D flip-flop FF2 at two input terminals, and creates the AND signal Ad shown in FIG. The signals are supplied to the input terminals R of the first D flip-flop FF1 and the second D flip-flop FF2. The output terminal Q of the first D flip-flop FF1 and the output terminal Q of the second D flip-flop FF2 quickly become low level when the AND signal Ad shown in FIG. The delayed phase difference signal Fup shown in (E) is set to the Low level, and the delayed phase difference period T1 for each cycle is detected.

  When the delayed phase difference signal Fup shown in FIG. 6 (E) is input to the input terminal UP of the up / down counter circuit UDC shown in FIG. 3, the delay phase difference signal Fup operates as a count-up. Each time the clock signal Clk shown in FIG. 6A is applied to the input terminal CK, it is incremented by one and added, and the counted up value shown in FIG. 6G is output as the up counter signal Cd. When the reset signal Rs is input to the input terminal R, the up counter signal Cd is cleared.

  The register circuit LD shown in FIG. 3 converts the count-up value shown in FIG. 6G, which is measured every cycle, into a numerical value and holds it as a positive value. At time t = t2, the reset signal is input to the input terminal WE. When Rs is input, the held positive numerical value is output as a phase difference count signal Pc shown in FIG.

  When the positive numerical phase difference count signal Pc shown in FIG. 6 (H) is input to the PI control circuit shown in FIG. 4, the proportional value is determined in advance as the positive numerical value by the PI control equation shown in FIG. Calculated by multiplying the proportional gain coefficient Kp, and multiplying the positive value by a predetermined integral gain coefficient Ki and accumulating the multiplied value, and calculating the proportional value and the integral value. To obtain a proportional integral value and output it as a proportional integral signal Pi.

  The phase difference correction limiting circuit REC shown in FIG. 5 converts the digitized value of the proportional integration signal Pi into an analog voltage signal and inputs it to the voltage controlled oscillation circuit VCO. The voltage controlled oscillation circuit VCO increases the output frequency Fo in accordance with the value of the analog voltage signal, and the frequency dividing circuit 1 / N divides the output frequency Fo to a predetermined value and returns the feedback frequency signal Fo /. Output as N. Thereafter, the above is repeated and the phase control is performed so that the delay phase difference period T1 shown in FIG. 6C becomes zero.

  When the feedback frequency signal Fo / N becomes high level at time t = t5 shown in FIG. 6C, the clock input terminal CK of the second D flip-flop FF2 shown in FIG. 2 becomes high level, and the output terminal Q The advanced phase difference signal Fdo shown in FIG. 6 (F) is output at high level and output.

  When the reference frequency signal Fi becomes High level at time t = t6 shown in FIG. 6B, the clock input terminal CK of the first D flip-flop FF1 shown in FIG. 2 becomes High level, and the output terminal Q becomes High level. Output as level. The AND circuit AND advances to two input terminals and receives the phase difference signal Fdo and the output signal of the output terminal Q of the first D flip-flop FF1, and receives the AND signal Ad of the AND circuit AND shown in FIG. As a production, the first D flip-flop FF1 and the second D flip-flop FF2 are supplied. The output terminal Q of the first D flip-flop FF1 and the output terminal Q of the second D flip-flop FF2 quickly become low level when the AND signal Ad shown in FIG. The lead phase difference signal Fdo shown in (F) is set to the Low level to detect the lead phase difference period T2 for each cycle.

  When the advance phase difference signal Fdo shown in FIG. 6 (F) is input to the input terminal DO of the up / down counter circuit UDC shown in FIG. 3, it operates as a countdown, and during the period when the advance phase difference signal Fdo is at a high level, FIG. Each time the clock signal Clk of 6 (A) is applied to the input terminal CK, it counts down by 1 and outputs the counted down value shown in FIG. 6 (G) as the down counter signal Cd. When the reset signal Rs is input to the input terminal R, the down counter signal Cd is cleared.

  The register circuit LD shown in FIG. 3 converts the countdown value shown in FIG. 6 (G) measured every cycle and holds it as a negative value. At time t = t6, the reset signal Rs is input to the input terminal WE. Is input, the held negative numerical value is output as a phase difference count signal Pc shown in FIG.

  When the negative numerical phase difference count signal Pc shown in FIG. 6 (H) is input to the PI control circuit shown in FIG. 4, the proportional value is determined in advance as the negative numerical value according to the PI control equation shown in FIG. The integral value is calculated by multiplying the negative numerical value by a predetermined integral gain coefficient Ki and accumulating the multiplied value, and the calculated proportional value and integral value are calculated. To obtain a proportional integral value and output it as a proportional integral signal Pi.

  The phase difference correction limiting circuit REC shown in FIG. 5 converts the digitized value of the proportional integration signal Pi into an analog voltage signal and inputs it to the voltage controlled oscillation circuit VCO. The voltage controlled oscillation circuit VCO reduces the output frequency Fo in accordance with the value of the analog voltage signal, and the frequency dividing circuit 1 / N divides the output frequency Fo to a predetermined value and feedback frequency signal Fo / Output as N. Thereafter, the above is repeated and phase control is performed so that the lead phase difference period T2 shown in FIG. 6C becomes zero.

[Embodiment 2]
FIG. 7 is a waveform diagram for explaining the operation of the second embodiment. The operation of the second embodiment will be described with reference to FIG.

The proportional gain Kp of the PI control circuit shown in FIG. 4 is uniquely determined by the frequency F [MHz] of the clock signal Clk. For example, in the pulse width modulation type inverter device, the frequency of the clock signal Clk is 40 [MHz], and in order to quickly synchronize with the reference frequency signal Fi (system frequency) 50 [Hz], the range of Kp-range Is set to 20 to 35 according to experimental results, and the proportional gain Kp is set to
Kp = Kp-range / F [MHz]
Calculate from In FIG. 7, the frequency of the reference frequency signal Fi is set to 50 [Hz], the frequency of the clock signal Clk is set to 40 [MHz], the Kp-range is set to 32, and the proportional gain Kp is set to 0.8. .

The integral gain Ki of the PI control circuit shown in FIG. 4 is uniquely determined by the frequency F [MHz] of the clock signal Clk as described above. In the pulse width modulation type inverter device, 40 [MHz] is used, and the range of Ki-range for quickly synchronizing with the reference frequency signal Fi (system frequency) 50 [Hz] is set to 5 to 15 according to the experimental results. Set the integral gain Ki
Ki = Ki-range / F [MHz]
Calculate from In FIG. 7, the frequency of the reference frequency signal Fi is set to 50 [Hz], the frequency of the clock signal Clk is set to 40 [MHz], Ki-range is set to 8, and the integral gain Ki is set to 0.2. .

  FIG. 7 is a waveform diagram obtained by calculation with the proportional gain Kp set to 0.8, the integral gain Ki set to 0.2, and the reference frequency signal Fi (system frequency) set to 50 [Hz]. As shown in FIG. 7, for example, even if the reference frequency signal suddenly changes from 50 [Hz] to 52.5 [Hz], the feedback frequency signal Fo / N responds quickly, and the reference frequency signal Fi and the feedback frequency The phase difference Fi-Fo / N from the signal Fo / N is quickly reduced. In contrast, a PLL circuit using a conventional low-pass filter (LPF) has a slower phase control response than the present invention using PI control. Although not shown, the same effect can be obtained even if the frequency of the reference frequency signal Fi is changed to the system frequency 60 [Hz].

[Embodiment 3]
FIG. 5 is a detailed circuit diagram of the phase difference correction limiting circuit REC of the third embodiment. The proportional integral upper limit setting circuit HRF for setting a numerically converted predetermined proportional integral upper limit value and a numerically converted predetermined value are shown. It is formed by a proportional integral lower limit setting circuit LRF for setting a proportional integral lower limit value, a comparison discriminating circuit DC, a multiplexer circuit MS, and a DA converter circuit D / A.

  When the proportional integration signal Pi is input, the phase difference correction limiting circuit REC compares the value of the proportional integration signal Pi with the proportional integration upper limit value Hr and the proportional integration lower limit value Lr by the comparison discriminating circuit DC, and the proportional integration signal Pi. An output signal D1 is output when the value of the signal Pi is less than the proportional integral lower limit Lr, and an output signal D2 when the value of the proportional integral signal Pi is less than the proportional integral upper limit Hr and greater than or equal to the proportional integral lower limit Lr. When the value of the proportional integration signal Pi is equal to or greater than the proportional integration upper limit value Hr, the output signal D3 is output and input to the multiplexer circuit MS.

  The multiplexer circuit MS selects and outputs the proportional integration lower limit Lr when the signal D1 is input, selects and outputs the proportional integration signal Pi when the signal D2 is input, and is proportional when the signal D3 is input. The integral upper limit value Hr is selected and output. The DA conversion circuit D / A converts the numerically converted proportional integral lower limit value Lr, proportional integral signal Pi, and proportional integral upper limit value Hr into an analog voltage signal and outputs it as a phase difference correction signal Re.

  FIG. 8 shows the feedback frequency signal Fo / N when the proportional gain Kp is set to 0.8, the proportional gain Kp is set to 0.2, and the reference frequency signal Fi (system frequency) 50 [Hz] is rapidly changed. FIG. 6 is a diagram obtained by calculation, and shows a state in which the feedback frequency signal Fo / N is limited so as not to fluctuate by 52 [Hz] or more by a predetermined proportional integral upper limit value Hr of the phase difference correction limiting circuit REC. Show. By providing the phase difference correction limiting circuit REC as described above, even if the reference frequency signal Fi (system frequency) 50 [Hz] => 52.5 [Hz] => 50 [Hz] varies rapidly, the proportional integral upper limit value Hr By providing the limit control, the feedback frequency signal Fo / N can respond quickly.

  From the above, the upper limit of the operating frequency of the inverter circuit of the pulse width modulation type inverter device is set, so that the operation of the inverter circuit does not leave the standard range, and the snubber circuit not shown is normally protected. Since the surge voltage applied to the switching element can be removed by operating as a circuit, the switching element can be prevented from being destroyed.

  The phase difference correction limiting circuit REC described above has a variation range of 44.68 [Hz] to 56.75 [Hz], 60 [Hz] with respect to the reference frequency signal Fi (system frequency) 50 [Hz] based on experimental results and the like. Good results were obtained when limiting to 52.50 [Hz] to 70.00 [Hz] with respect to [Hz].

It is a block diagram which shows the PLL circuit of this invention. FIG. 2 is a detailed circuit diagram of the phase comparison circuit shown in FIG. 1. FIG. 2 is a detailed circuit diagram of the phase difference count circuit shown in FIG. 1. FIG. 2 is a detailed circuit diagram of a PI control circuit shown in FIG. 1. FIG. 2 is a detailed circuit diagram of the phase difference correction limiting circuit shown in FIG. 1. It is a waveform timing diagram for demonstrating operation | movement of the PLL circuit of this invention. FIG. 6 is a waveform diagram for explaining the operation of the second embodiment. FIG. 10 is a waveform diagram for explaining the operation of the third embodiment. It is a block diagram which shows the PLL circuit of a prior art.

Explanation of symbols

AND AND circuit CO counter circuit D / A DA conversion circuit DC comparison determination circuit FF1 1st D flip-flop FF2 2nd D flip-flop HRF proportional integration upper limit setting circuit LD register circuit LRF proportional integration lower limit setting circuit 1 / N frequency division Circuit MS Multiplexer circuit UDC Up / down counter circuit VCO Voltage controlled oscillation circuit PI PI control circuit (proportional integration circuit)
PCO phase difference count circuit PFD phase comparison circuit RS reset generation circuit REC phase difference correction limiting circuit Cd up / down counter signal Clk clock signal Fi reference frequency signal Fo output frequency Fo / N feedback frequency signal Fup delayed phase difference signal Fdo advance phase difference Signal Hr Proportional integral upper limit set value Lr Proportional integral lower limit set value Pc Phase difference count signal Pi Proportional integral signal Re Phase difference correction signal

Claims (3)

  A phase difference between a reference frequency signal and a feedback frequency signal is detected, and when the feedback frequency signal is delayed in phase from the reference frequency signal, a delayed phase difference is detected and output, and the feedback frequency signal is phased from the reference frequency signal. A phase comparison circuit that detects and outputs an advance phase difference when the phase is advanced, and counts up every cycle when the detected phase difference is a delayed phase difference, and conversely 1 when the detected phase difference is an advance phase A phase integration circuit that counts down every period and continues the count-up or count-down until the delayed phase difference or lead phase difference disappears, converts the counted value into an analog voltage signal, and outputs the converted analog voltage signal. A voltage-controlled oscillation circuit that controls the output frequency according to the output frequency, and divides the output frequency into a predetermined value and outputs it as a feedback frequency signal. The phase integration circuit is replaced with a phase proportional integration circuit, and the replaced phase proportional integration circuit includes the reference frequency signal detected by the phase comparison circuit and the feedback frequency signal. When the phase difference for each cycle is a lagging phase, the value is converted to a positive value, and when the phase difference is a leading phase, the value is converted to a negative value. Calculate the proportional value by multiplying the numerical value by a predetermined proportional gain coefficient, multiply the positive or negative numerical value of the phase difference for each period converted by the numerical value by a predetermined integral gain coefficient, and accumulate the multiplied value Calculating an integral value, adding the calculated proportional value and the integral value to calculate a proportional integral value, converting the calculated proportional integral value into an analog voltage signal, and outputting the analog voltage signal. PLL circuit   The proportional gain coefficient Kp of the proportional integration circuit is set by Kp = (20 to 35) / F [MHz], and the integral gain coefficient Ki is set by Ki = (5 to 15) / F [MHz]. The PLL circuit according to claim 1. A phase difference correction limiting circuit is provided between the phase proportional integration circuit and the voltage controlled oscillation circuit, and a predetermined proportional integral upper limit value and a proportional integral lower limit value are set in the phase difference correction limit circuit, and the proportional integral value When the proportional integral upper limit value exceeds the set proportional integral upper limit value, the proportional integral upper limit value is output as the proportional integral signal.When the proportional integral value is less than the set proportional integral lower limit value, the proportional integral lower limit value is output as the proportional integral lower limit value. 2. The output as a signal, and when the proportional integral value is less than the set proportional integral upper limit value and greater than or equal to the proportional integral lower limit value, the proportional integral value is outputted to the voltage controlled oscillation circuit. The PLL circuit according to claim 2.

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