JP2005210592A - D / A converter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress complication of wiring by multiplexing and an increase of a circuit area to a minimum. <P>SOLUTION: A D/A conversion circuit has resistor strings R<SB>M</SB>0-R<SB>M</SB>15 which divide reference voltages Vref 24, first semiconductor switches S<SB>U1</SB>0-S<SB>U1</SB>15 and S<SB>L1</SB>0-S<SB>L1</SB>3 for taking out voltage of each resistor end for a first D/A conversion, and second semiconductor switches S<SB>U2</SB>0-S<SB>U2</SB>15 and S<SB>L2</SB>0-S<SB>L2</SB>3 for taking out voltage of each resistor end for a second D/A conversion. The resistor strings R<SB>M</SB>0-R<SB>M</SB>15 are arranged in a matrix form along both directions of orthogonal axes (X and Y axes) of an integrated circuit surface, so that an upper bit decoder circuit 17 and a lower bit decoder circuit 18 for the first D/A conversion and an upper bit decoder circuit 19 and a lower bit decoder circuit 20 for the second D/A conversion are respectively laid out to opposite positions of the resistor strings R<SB>M</SB>0-R<SB>M</SB>15. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a digital / analog conversion circuit (hereinafter referred to as a D / A conversion circuit), and more particularly to a resistance string type D / A conversion circuit.

  In a conventional resistor string type D / A converter circuit, for example, as shown in FIG. 1, 16 resistors R0, R1,..., R15 are connected in series as a resistor string 1, and nodes between the resistors are connected. The switches S0, S1,..., S15 are connected one by one to the end of the resistor string 1 (connection point with Rref), and a reference voltage Vref4 is applied to the resistor string 1. Then, the switching of the switches S0 to S15 is controlled according to the output code of the decoder circuit 3, and an analog voltage obtained by dividing the reference voltage Vref by resistance is output from the output terminal DAOUT5.

  As a conventional D / A conversion circuit multiplexing technique, that is, a technique for sharing a single resistor string in a plurality of D / A conversions, for example, the one shown in FIG. 2 is known. 2 digitally controls the switches x0 to x15, y0 to y15, SWout10 to SWout17, and SWout20 to SWout27 in order to output two analog voltages DAOUT1 and DAOUT2 from one resistor string 6 (R0 to R15). It is a schematic block diagram of a multiplexing D / A conversion circuit.

  In FIG. 2, the end of the resistor string 6 and the node on the side not connected to the resistor string 6 in the first switch group (x0 to x15) connected one by one between the resistors R0 to R15 are 2n / 2. 2 (n = 4 in FIG. 2) are short-circuited to form 2n / 2 first node groups (x0 to x3, x4 to x7, x8 to x11, x12 to x15). Similarly, the resistor string 6 And the second switch group (y0 to y15) connected one by one between the resistors R0 to R15, the second node group (y0, y4, y8, y12, y1, y5, y9, y13, y2, y6, y10, y14 and y3, y7, y11, y15).

  Each of the first and second node groups is connected to a plurality of output terminals 8 and 9 (DAOUT1, DAOUT2) via output switches (SWout10 to SWout17, SWout20 to SWout27), and the first and second node groups are connected. The first switch group and the second switch group are controlled to be opened and closed so that the internal switch does not connect the resistor string 6 at two or more locations, that is, does not overlap the node group.

Thus, if the D / A conversion circuit is multiplexed and each switch is controlled to open and close, the number of control switches can be reduced compared to the case where a plurality of control switches connected to the resistor string 6 are simply provided. An increase in circuit area can be minimized (see, for example, Patent Document 1).
JP 2003-243987 (page 11, FIG. 4)

  However, although the above prior art can reduce the number of switches and reduce the circuit area, the wiring between switches for multiplexing the D / A conversion circuit is complicated, and the layout of the switches and wirings is reduced. There are circumstances that make it difficult. Also, depending on the multiplexed decoding value, it cannot be said that there is no case where the resistor string 6 is connected at two or more locations. Therefore, if the design is performed in consideration of the case, the number of switches is greatly reduced. It becomes difficult. In addition, the decoding method becomes complicated, the number of decoding circuits increases, and the number of control lines may increase.

  The present invention focuses on the layout method when multiplexing D / A conversion circuits, thereby minimizing the complexity of wiring and the increase in circuit area due to multiplexing. The purpose is to provide. It is another object of the present invention to provide a D / A conversion circuit suitable for increasing the speed by reducing the crosstalk between the decoder circuits by multiplexing and the wiring capacitance between the decoder circuit and the resistor string.

  A D / A conversion circuit according to the present invention controls a resistor string that divides a reference voltage, a first semiconductor switch that extracts a voltage of the resistor string for the first D / A conversion, and the first semiconductor switch. A first decoder circuit, a second semiconductor switch for extracting the voltage of the resistor string for the second D / A conversion, and a second decoder circuit for controlling the second semiconductor switch. An A conversion circuit, wherein the resistor string is arranged in both directions of an orthogonal axis on one surface, and includes upper and lower first and second decoder circuits, and first and second lower semiconductor switches. Are laid out at positions facing each other across the resistor string.

  According to the D / A conversion circuit of the present invention, the resistor string is arranged in both directions of the orthogonal axis on one surface, and the decoder circuit and the lower-level semiconductor switch are laid out at positions facing each other across the resistor string. Therefore, crosstalk in a plurality of D / A conversions can be reduced and operated independently, and wiring layout can be easily performed.

  One aspect of the D / A conversion circuit of the present invention is arranged along both directions of the orthogonal axis of the circuit mounting surface, and includes a resistor string that divides a reference voltage, and a resistor string for the first D / A conversion. A first semiconductor switch for extracting a divided voltage; a first decoder circuit for controlling the first semiconductor switch; and a second for extracting a divided voltage of the resistor string for a second D / A conversion. A semiconductor switch; and a second decoder circuit for controlling the second semiconductor switch. According to this configuration, since the resistor string that divides the reference voltage is arranged along both directions of the orthogonal axis of the circuit mounting surface, it is possible to minimize the complexity of wiring and the increase in circuit area due to multiplexing. .

  In the present invention, the first decoder circuit and the second decoder circuit are laid out at positions facing each other across the resistor string on the circuit mounting surface. According to this configuration, the first decoder circuit and the second decoder circuit are laid out at positions facing each other across the resistor string on the circuit mounting surface, thereby reducing crosstalk between the decoder circuits due to multiplexing. At the same time, the processing speed can be increased by reducing the wiring capacitance between the decoder circuit and the resistor string.

  In the present invention, the first decoder circuit includes a first upper bit decoder circuit and a first lower bit decoder circuit for the first D / A conversion, and the second decoder The circuit includes a second upper bit decoder circuit and a second lower bit decoder circuit for the second D / A conversion, wherein the first upper bit decoder circuit and the second upper bit decoder circuit An upper bit decoder circuit is laid out on the circuit mounting surface so as to face each other across the resistor string, and the first lower bit decoder circuit and the second lower bit decoder circuit are the circuit On the mounting surface, it is laid out at positions facing each other across the resistor string. According to this configuration, the first higher-order and lower-order bit decoder circuit and the second higher-order and lower-order bit decoder circuit are laid out at positions facing each other across the resistor string on the circuit mounting surface. Can reduce the crosstalk between the decoder circuits and reduce the wiring capacitance between the decoder circuit and the resistor string, thereby increasing the processing speed.

  In the present invention, the first semiconductor switch includes a first upper bit semiconductor switch and a first lower bit semiconductor switch for the first D / A conversion, and the second semiconductor The switch includes a second upper bit semiconductor switch and a second lower bit semiconductor switch for the second D / A conversion, wherein the first lower bit semiconductor switch and the second lower bit semiconductor switch The lower bit semiconductor switches are laid out at positions facing each other across the resistor string on the circuit mounting surface. According to this configuration, the first lower bit semiconductor switch and the second lower bit semiconductor switch are laid out at positions facing each other across the resistor string on the circuit mounting surface. And the processing speed can be increased by reducing the wiring capacitance between the decoder circuit and the resistor string.

  Furthermore, the present invention provides a first low-pass filter to which a voltage extracted by the first semiconductor switch is supplied, a first buffer amplifier that supplies an output of the first low-pass filter to an external circuit, A second low-pass filter to which the voltage extracted by the second semiconductor switch is supplied; and a second buffer amplifier that supplies an output of the second low-pass filter to an external circuit. According to this configuration, the first and second low-pass filters to which the voltages extracted by the first and second semiconductor switches are supplied, and the outputs of the first and second low-pass filters are supplied to the external circuit. Since the first and second buffer amplifiers are provided, it is possible to prevent the crosstalk frequency component from being output to the external circuit.

  The present invention also provides a first sample and hold circuit to which a voltage extracted by the first semiconductor switch is supplied, and a first buffer for supplying an output of the first sample and hold circuit to an external circuit. An amplifier, a second sample-and-hold circuit to which a voltage extracted by the second semiconductor switch is supplied, and a second buffer amplifier that supplies an output of the second sample-and-hold circuit to an external circuit Prepare. According to this configuration, the first and second sample and hold circuits to which the voltages extracted by the first and second semiconductor switches are supplied, and the outputs of the first and second sample and hold circuits are connected to the external circuit. Since the first and second buffer amplifiers supplied to the first and second buffer amplifiers are provided, it is possible to prevent the frequency component of the crosstalk from being output to the external circuit.

  In the present invention, the number of bits in the first D / A conversion and the second D / A conversion are preferably different. According to this configuration, even if the number of bits is different, based on the layout of the first D / A conversion unit with a large number of bits, the voltage extraction position of the second D / A conversion unit with a small number of bits and the resistor string As a result, it is possible to easily lay out the layout without making a large change compared to the case where the number of bits is the same.

  According to the present invention, since the first and second decoder circuits are laid out at positions facing each other across the resistor string, they can be operated independently with less interaction in a plurality of D / A conversions. .

  In addition, since the crosstalk between the first and second decoder circuits can be reduced and operated independently, the wiring layout can be easily performed and the wiring pitch can be minimized.

  Further, by sharing the resistor string in a plurality of D / A conversions, the current consumption of the resistor string portion in the system LSI that performs a plurality of D / A conversions can be suppressed, and the power consumption of the system LSI can be reduced.

(Embodiment 1)
FIG. 3 is an explanatory diagram showing a schematic configuration of a D / A conversion circuit for explaining the first embodiment of the present invention. In FIG. 3, a 4-bit D / A conversion circuit is described as an example, but it may be configured with a larger number of bits.

The D / A converter circuit of this embodiment includes a resistor string R _M 0 to R _M 15 that is connected to the termination resistor Rref and divides the reference voltage Vref15, and an upper bit that extracts the voltage at each resistor end for D / A conversion. and use the semiconductor switch S _U 0~S _U 15 and the lower bit semiconductor switch S _L 0~S _L 3, the upper bit decoder circuit 11 that controls the semiconductor for upper bit switch S _U 0~S _U 15, the lower bit and a lower-order bit decoder circuit 12 for controlling the use semiconductor switch S _L 0~S _L 3.

Resistor string R _M 0 to R _M 15 are arranged in a matrix along both orthogonal axes of the integrated circuit surface (x, y-axis), and upper bit decoder circuit 11, a decoder circuit 12 and the lower lower bit bit semiconductor switch 13 and (S _L 0~S _L 3), but are laid so as to be disposed at right angles across the resistor string R _M 0~R _M 15.

Resistor string R _M 0 to R _M 15, upper bit decoder circuit 11, the low-order bit decoder circuit 12 and the lower bit semiconductor switch 13, by laying as described above, to simplify the wiring system, lower bit The layout of the decoder circuit 12 and the lower bit semiconductor switch 13 can be easily performed.

Further, a resistor string R _M 0 to R _M 15 by arranging in a matrix, can be compared with the prior art reduce the number of wirings of the upper bits semiconductor switching S _U 0~S _U 15. The relationship between the number of upper bits (number of wires) and the number of lower bits (number of wires) of the resistance matrix is shown in the following equation.

2 ^ N _Up = 2 ^ N / (2 ^ N _Low ) ... Equation 1
However, the number of bits of the D / A conversion circuit is N, the number of upper bits (number of wires) is N _{Up, and the} number of lower bits (number of wires) is N _Low .

  As can be seen from the above equation, the number of control wirings for the upper bits can be greatly reduced according to the number of lower bits. For this reason, the number of wiring increases due to multiplexing is less in the resistance matrix configuration than in the simple string configuration as shown in FIG. Therefore, by multiplexing the D / A conversion circuit with the resistance matrix configuration, the area can be reduced and the layout can be facilitated.

(Embodiment 2)
FIG. 4 is an explanatory diagram showing a schematic configuration of a D / A conversion circuit for explaining a second embodiment of the present invention. In FIG. 4, the duplication of the 4-bit D / A conversion circuit is described as an example, but it is also possible to configure with a larger number of bits and the number of multiplexing.

The D / A conversion circuit of this embodiment includes a resistor string R _M 0 to R _M 15 that divides the reference voltage Vref24, and a first semiconductor switch that extracts the voltage at each resistance end for the first D / A conversion. S _U1 and _{0~S U1 15, S L1 0~S L1} 3, the first decoder circuit 17, 18 for controlling the first semiconductor switch, the second D / a voltages of the resistors ends for conversion comprises a second semiconductor switch _{S U2 0~S U2 15, S L2} 0~S L2 3 to take out, and a second decoder circuits 19 and 20 for controlling the second semiconductor switch circuit.

Resistor string R _M 0 to R _M 15 is an integrated circuit quadrature axis of the surface (x, y-axis) are arranged in a matrix along both directions, the first D / A converter upper bit decoder circuit for a 17 and a lower-order bit decoder circuit 18, a second D / a converter upper bit decoder circuit 19 and the low-order bit decoder circuit 20 for, respectively, face each other across a resistor string R _M 0 to R _M 15 Laid out in position.

Further, the lower bit semiconductor switch 21 (S _L1 0 to S _L1 3) for the first D / A conversion and the lower bit semiconductor switch 22 (S _L2 0 to S _L2 0 for the second D / A conversion). S _L2 3) is laid out at positions facing each other across the resistor strings R _M 0 to R _M 15.

  This layout simplifies the wiring between the gates of the semiconductor switch and the wiring from the drain of the semiconductor switch to be an analog output to the output terminal, and the layout of the lower bit decoder circuits 18 and 20 and the semiconductor switch is simple. Become.

Further, the first decoder circuit 17 and 18 second decoder circuits 19 and 20, due to the opposite position across the resistor string R _M 0 to R _M 15, the first decoder circuit 17 first The two decoder circuits 19 and 20 are not affected by each other and can be regarded as independent. This means that it is not necessary to consider mislatch due to crosstalk between decoder circuits, which is a problem when the first and second D / A conversions are operated asynchronously and at high speed. This facilitates the layout of the decoder circuit and minimizes the wiring pitch.

Further, the drain side outputs of the first lower bit semiconductor switch 21 and the second lower bit semiconductor switch 22 and the wiring between the output terminals 25 and 26 are opposite to each other via the resistor strings R _M 0 to R _M 15. It can be considered that it exists independently without being influenced by each other. Therefore, when the first and second D / A conversions are performed asynchronously, it is possible to prevent the glitch of the lower bit semiconductor switches 21 and 22 from flowing into the analog output and destabilizing the output.

(Embodiment 3)
FIG. 5 is an explanatory diagram showing a schematic configuration of a D / A conversion circuit for explaining a third embodiment of the present invention. In the present embodiment, the crosstalk of the D / A conversion circuit shown in FIG. 4 is further reduced.

In the D / A conversion circuit shown in FIG. 4, the analog output wires 27 to 34 of the upper bit semiconductor switches S _U1 0 to S _U1 15 and S _U2 0 to S _U2 15 are connected to the first and second D / A converters. They are wired adjacent to each other for A conversion, and there is crosstalk due to the capacitance between the wires. This is because the analog output wirings 27 to 34 run in parallel at a narrow pitch for a long distance.

Therefore, in the D / A conversion circuit of this embodiment, as shown in FIG. 5, the analog output wirings 45 to 48 of the upper bit semiconductor switches S _U1 0 to S _U1 15 for the first D / A conversion and The analog output wirings 49 to 52 of the upper bit semiconductor switches S _U2 0 to S _U2 15 for the second D / A conversion are separated.

  By laying out in this way, the inter-wiring capacitance in the first and second D / A conversions can be reduced. Therefore, when the first second D / A conversion is performed asynchronously, the glitch of the upper bit semiconductor switch wraps around each other's analog output, and the problem of crosstalk in which the output becomes unstable can be reduced. .

(Embodiment 4)
FIG. 6 is an explanatory diagram showing a schematic configuration of a D / A conversion circuit for explaining a fourth embodiment of the present invention. In the D / A conversion circuit of this embodiment, LPFs (low-pass filters) 63 and 65 and buffer amplifiers 64 and 66 are inserted in the paths of the analog outputs DAOUT1 and DAOUT2 of the D / A conversion circuit shown in FIG. It is characterized by doing.

The analog output of the D / A conversion circuit shown in FIG. 4 may not completely cancel the influence of crosstalk due to multiplexing of the D / A conversion circuit. Therefore, in the analog output path of each D / A converter, when the crosstalk frequency is F _n and the cutoff frequency of the LPFs 63 and 65 is F _c ,
F _c << F _n ... Formula 2
By adding the LPFs 63 and 65 having the relationship, it is possible to greatly attenuate the appearance of the crosstalk frequency component in the output. This is particularly effective when the D / A conversion circuit of this embodiment is used as a control D / A conversion circuit.

(Embodiment 5)
FIG. 7 is an explanatory diagram showing a schematic configuration of a D / A conversion circuit for explaining a fifth embodiment of the present invention. The D / A converter circuit of the present embodiment has strobe signals (S / S) of the first and second D / A converters on the paths of the analog outputs DAOUT1 and DAOUT2 of the D / A converter circuit shown in FIG. It is characterized in that sample and hold circuits 77 and 79 operating with an H control signal) and buffer amplifiers 78 and 80 are inserted.

The analog output of the D / A conversion circuit shown in FIG. 4 may not completely cancel the influence of crosstalk due to multiplexing of the D / A conversion circuit. Therefore, when the crosstalk frequency is F _n and the hold times of the sample and hold circuits 77 and 79 are T _{s in} the output path of each D / A converter,
T _s >> 1 / F _n Formula 3
The sample and hold circuits 77 and 79 having the above relationship are added, and the output terminals 75 and 76 and the resistor string portion are separated during the period in which the first and second D / A conversion operations are performed. As a result, it is possible to further suppress crosstalk that wraps around the output terminals 75 and 76.

(Embodiment 6)
FIG. 8 is an explanatory diagram showing a schematic configuration of a D / A conversion circuit for explaining a sixth embodiment of the present invention. The D / A conversion circuit of the present embodiment is the same as the D / A conversion circuit shown in FIG. 4 except that the first D / A conversion has 4 bits and the second D / A conversion has 3 bits. And D / A conversion with different number of bits is performed by multiplexing.

  In the D / A conversion circuit layout method of this embodiment, each D / A conversion unit is considered to be independent from each other with a resistor string interposed therebetween. Therefore, even when the number of bits is different, the first D / A conversion with many bits Based on the layout of the part, the second D / A converter with a small number of bits and the position of extracting the voltage of the resistor string are only determined, and there is no need to make a large change compared to the case where the number of bits is the same. Can be laid out.

  In addition, since the resistance division number inside the resistor string is determined by the number of bits of the first D / A converter on the high bit side, by designing to satisfy the accuracy on the high bit side, the D / There is no problem with the accuracy of the A converter.

  The D / A converter circuit of the present invention is laid out at a position where the first and second decoder circuits are opposed to each other across the resistor string, so that the D / A converter circuit operates independently with less interaction in a plurality of D / A conversions. This is useful as a resistor string type D / A conversion circuit.

Explanatory drawing which shows schematic structure of the D / A converter circuit by the conventional resistor string Explanatory drawing for multiplexing a D / A conversion circuit by a conventional resistor string Explanatory drawing which shows schematic structure of the D / A converter circuit of Example 1 of this invention. Explanatory drawing which shows schematic structure of the D / A converter circuit of Example 2 of this invention. Explanatory drawing which shows schematic structure of the D / A converter circuit of Example 3 of this invention. Explanatory drawing which shows schematic structure of the D / A converter circuit of Example 4 of this invention. Explanatory drawing which shows schematic structure of the D / A converter circuit of Example 5 of this invention. Explanatory drawing which shows schematic structure of the D / A converter circuit of Example 6 of this invention.

Explanation of symbols

1, 6 Resistor string 2, 7 Semiconductor switch 3 Decoder circuit 4, 10, 15, 24, 42, 60, 74, 88 Reference voltage Vref
5, 16 Output terminal 8 First D / A conversion output terminal 9 Second D / A conversion output terminal 11 Upper bit decoder circuit 12 Lower bit decoder circuit 13 Lower bit semiconductor switches 14 and 23 , 41, 59, 73, 87 Resistor string and upper bit semiconductor switches 17, 35, 53, 67, 81 First upper bit decoder circuits 18, 36, 54, 68, 82 for first D / A conversion Lower bit decoder circuits 19, 37, 55, 69, 83 for D / A conversion Second upper bit decoder circuits 20, 38, 56, 70, 84 for second D / A conversion Lower bit decoder circuit 21, 39, 57, 71, 85 First lower bit semiconductor switch for D / A conversion 22, 40, 58, 72, 86 Lower bit semiconductor switch for second D / A conversion 25, 43, 61, 75, 89 First D / A conversion output terminals 26, 44, 62, 76, 90 Second D / A conversion output terminals 27-30, 45-48 One D / A conversion upper bit analog output wiring 31 to 34, 49 to 52 Second D / A conversion upper bit analog output wiring 63 First D / A conversion LPF
65 Second LPF for D / A conversion
64, 78 First D / A conversion buffer amplifier 66, 80 Second D / A conversion buffer amplifier 77 First D / A conversion sample / hold circuit 78 Second D / A conversion sample Hold circuit

Claims (7)

A resistor string that is arranged along both directions of the orthogonal axis of the circuit mounting surface and divides the reference voltage;
A first semiconductor switch for extracting a divided voltage of the resistor string for a first D / A conversion;
A first decoder circuit for controlling the first semiconductor switch;
A second semiconductor switch for extracting a divided voltage of the resistor string for a second D / A conversion;
A second decoder circuit for controlling the second semiconductor switch;
A D / A conversion circuit comprising: A D / A converter circuit according to claim 1,
A D / A conversion circuit in which the first decoder circuit and the second decoder circuit are laid out at positions facing each other across the resistor string on the circuit mounting surface. A D / A converter circuit according to claim 1,
The first decoder circuit includes a first upper bit decoder circuit and a first lower bit decoder circuit for a first D / A conversion,
The second decoder circuit includes a second upper bit decoder circuit and a second lower bit decoder circuit for the second D / A conversion,
The first upper bit decoder circuit and the second upper bit decoder circuit are laid out at positions facing each other across the resistor string on the circuit mounting surface,
A D / A conversion circuit in which the first lower bit decoder circuit and the second lower bit decoder circuit are laid out at positions facing each other across the resistor string on the circuit mounting surface. A D / A converter circuit according to claim 1,
The first semiconductor switch includes a first upper bit semiconductor switch and a first lower bit semiconductor switch for the first D / A conversion,
The second semiconductor switch includes a second upper bit semiconductor switch and a second lower bit semiconductor switch for the second D / A conversion,
A D / A conversion circuit in which the first lower bit semiconductor switch and the second lower bit semiconductor switch are laid out at positions facing each other across the resistor string on the circuit mounting surface. A D / A converter circuit according to claim 1,
A first low-pass filter to which the voltage extracted by the first semiconductor switch is supplied;
A first buffer amplifier for supplying an output of the first low-pass filter to an external circuit;
A second low-pass filter to which the voltage extracted by the second semiconductor switch is supplied;
A D / A conversion circuit comprising: a second buffer amplifier that supplies an output of the second low-pass filter to an external circuit. A D / A converter circuit according to claim 1,
A first sample and hold circuit to which the voltage extracted by the first semiconductor switch is supplied;
A first buffer amplifier for supplying an output of the first sample and hold circuit to an external circuit;
A second sample and hold circuit to which the voltage extracted by the second semiconductor switch is supplied;
A D / A conversion circuit comprising: a second buffer amplifier that supplies an output of the second sample and hold circuit to an external circuit. A D / A converter circuit according to claim 1,
A D / A conversion circuit having a different number of bits in the first D / A conversion and the second D / A conversion.

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