JP2005218270A - Direct current to alternating current conversion apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a direct current to an alternating current conversion apparatus that is small in size, low in cost and capable of reducing easily and satisfactorily the electrical stress of a main switch and achieving easily protection at the occurrence of an abnormality. <P>SOLUTION: A series circuit of first and second voltage dividing capacitors Ca, Cb is connected between first and second DC terminals 1, 2. A first auxiliary switch Q1 is connected between the first DC terminal 1 and a relay terminal 4 for a soft switching purpose. One end of a series circuit of a second auxiliary switch Q2 and a resonance reactor Lr is connected to the relay terminal 4, and the other end thereof is connected to the mutual connecting point of the first and the second voltage-dividing capacitors Ca, Cb. An inverter circuit of V-connection is connected between the relay terminal 4 and the second DC terminal 2 and 3-phase AC terminals 3u, 3v and 3w. The first auxiliary switch Q1 is controlled to be turned off at the occurrence of the abnormality. First and second clamping capacitors C11, C12 are connected in parallel with the first auxiliary switch Q1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a DC-AC converter having a soft switching circuit.

A three-phase inverter having a three-phase switching circuit for obtaining a two-phase AC output in a switching DC-AC converter used in a power conditioner, uninterruptible power supply, motor drive inverter, battery charger, etc. Alternatively, an inverter having a V connection configuration is used. FIG. 1 shows a conventional three-phase voltage type inverter having a V-connection configuration. The inverter shown in FIG. 1 includes first and second DC terminals 1 and 2 to which a DC power source 50 composed of a solar cell, a boost chopper, a rectifier, an electrolytic capacitor, a battery, or the like is connected. The voltage dividing capacitors Ca and Cb, the first and second main switches S1 and S2 constituting the first phase (U phase) switching circuit, and the third and third constituting the third phase (W phase) switching circuit. 4 main switches S3 and S4, individual or parasitic (built-in) first to fourth main diodes D1 to D4 connected in parallel to the first to fourth main switches S1 to S4, and the first and first 2 reactors Lu and Lw, first and second filter capacitors Cf1 and Cf2, first, second and third phase AC terminals 3u, 3v and 3w, a voltage reference value generator 51, and a sawtooth wave Generator 52 and first and second comparators 53, 54 And a switch control signal forming circuit 55.
The first and second voltage dividing capacitors Ca and Cb are connected between the first and second DC terminals 1 and 2 and connected in series with each other. The second-phase AC terminal 3v is connected to an interconnection point between the first and second voltage dividing capacitors Ca and Cb.

The voltage reference value generator 51 generates a first phase voltage reference value Vru and a third phase voltage reference value Vrw composed of a sine wave shown in FIG. The first phase voltage reference value Vru and the third phase voltage reference value Vrw have a phase difference of 60 degrees. Although only one period Tac of the AC voltage is shown in FIG. 2, the voltage reference value generator 51 repeatedly generates the first and third phase voltage reference values Vru and Vrw of FIG.
The sawtooth generator 52 generates the sawtooth voltage Vt shown in FIG. 2A at a frequency sufficiently higher than the repetition frequency of the first and third phase voltage reference values Vru and Vrw of the sine wave.
The first and second comparators 53 and 54 compare the first and third phase voltage reference values Vru and Vrw with the sawtooth voltage Vt and compare the first and third comparators 53 and 54 shown in FIGS. The first and third control signals Vg1 and Vg3 for the main switches S1 and S3 are generated. The switch control signal forming circuit 55 sends the first and third switch control signals Vg1 and vg3 of FIGS. 2B and 2C to the control terminals (gates) of the first and third main switches S1 and S3. The second and fourth switch control signals Vg2 and Vg4, which are phase inversion signals of the first and third switch control signals Vg1 and Vg3, are formed and used as the control terminals of the second and fourth main switches S2 and S4. send.

  By the way, if the current is directly cut off by the first to fourth main switches S1 to S4 in FIG. 1, an electrical stress is applied to the main switches S1 to S4 at the time of turn-off, and switching surge, switching noise, and switching loss are caused. Arise. In addition, switching surge and switching loss become a problem even when the main switches S1 to S4 are turned on.

Patent Document 1 discloses that a switching switch is soft-switched in a three-phase full-bridge inverter to reduce switching surge, switching noise, and switching loss. However, the soft switching circuit of Patent Document 1 cannot be used as it is in the inverter having the V-connection configuration shown in FIG. Further, the three-phase full-bridge type inverter has a disadvantage that the number of main switches is larger than that of an inverter having a V-connection configuration, which inevitably increases in cost and size.
In Japanese Patent Application No. 2003-46219, the present applicant has proposed a soft switching circuit for the inverter having the V-connection configuration shown in FIG. However, there is no disclosure of means for protecting the inverter from an abnormality such as a short circuit of an arm composed of a pair of inverter pairs.
JP 2000-262066 A

  Therefore, the problem to be solved by the present invention is that it is possible to reduce the size and cost, and it is possible to easily and satisfactorily reduce the electrical stress of the main switch and easily achieve protection in case of abnormality. It is to provide a direct current to alternating current conversion device.

Next, the present invention will be described with reference to the reference numerals of the drawings. However, the claims and the reference numerals used here are for helping the understanding of the present invention, and do not limit the present invention.
The present invention includes first and second DC terminals (1, 2),
First, second and third phase AC terminals (3u, 3v, 3w);
A relay terminal (4);
A first voltage dividing capacitor (Ca) connected between the first DC terminal (1) and the second phase AC terminal (3v);
A second voltage dividing capacitor (Cb) connected between the second DC terminal (2) and the second phase AC terminal (3v);
A first main switch (S1) connected between the relay terminal (4) and the first phase AC terminal (3u);
A second main switch (S2) connected between the first phase AC terminal (3u) and the second DC terminal (2);
A third main switch (S3) connected between the relay terminal (4) and the third phase AC terminal (3w);
A fourth main switch (S4) connected between the third phase AC terminal (3w) and the second DC terminal (2);
First, second, third and fourth resonance capacitors or parasitic capacitances connected in parallel to the first, second, third and fourth main switches (S1, S2, S3, S4), respectively. C1, C2, C3, C4),
A first auxiliary switch (Q1) connected between the first DC terminal (1) and the relay terminal (4);
A first auxiliary diode or parasitic diode (Da) connected in reverse parallel to the first auxiliary switch (Q1);
A series circuit of a second auxiliary switch (Q2) and a resonant reactor (Lr) connected between the relay terminal (4) and the second phase AC terminal (3v);
A second auxiliary diode or parasitic diode (Db) connected in reverse parallel to the second auxiliary switch (Q2);
The first, second, third, and fourth so that a three-phase AC voltage (Vuv, Vvw, Vwu) can be obtained at the first, second, and third phase AC terminals (3u, 3v, 3w). A main switch control circuit (5) for controlling on / off of the main switches (S1, S2, S3, S4) at a repetition frequency higher than the frequency of the three-phase AC voltage;
The voltage of the first, second, third and fourth resonance capacitors or parasitic capacitances (C1, C2, C3, C4) is set to the first, second, third and fourth main switches (S1, S2). , S3, S4), and an auxiliary switch control circuit (6) for controlling on / off of the first and second auxiliary switches (Q1, Q2) so that they can be reduced to zero or almost zero by the time of turn-on. ,
An abnormality detecting means (70 or 70a and 72, or 72a) for detecting an abnormality of the first auxiliary switch (Q1) and a circuit on the output side from the first auxiliary switch (Q1);
DC-AC conversion characterized by having off control means (73 or 73a) for controlling the first auxiliary switch (Q1) to be turned off in response to an output indicating an abnormality of the abnormality detecting means. It relates to the device.

According to a second aspect of the present invention, it is desirable to further include a voltage clamp circuit connected in parallel to the first auxiliary switch (Q1).
Preferably, the voltage clamp circuit is composed of a series circuit of first and second clamping capacitors (C11, C12) having polarity and a backflow prevention diode (D11).
The DC-AC converter further includes a first transient surge absorbing capacitor connected in parallel to the first clamping capacitor (C11) and having one end connected to the first DC terminal (1). (C13) and a second transient surge absorbing capacitor connected in parallel to the second clamping capacitor (C12) and having one end connected to the other end of the first transient surge absorbing capacitor (C13) (C14) between the interconnection point of the first and second transient surge absorbing capacitors (C13, C14) and the interconnection point of the first and second voltage dividing capacitors (Ca, Cb) And a second resistor (R1) connected between the other end of the second transient surge absorbing capacitor (C14) and the second DC terminal (2). R2) is desirable.
In addition, the abnormality detecting means may be configured such that the voltage across the first auxiliary switch (Q1), the current flowing through the first auxiliary switch (Q1), or the first, second, third and second It is desirable to detect an abnormality in the control signals of the four main switches (S1, S2, S3, S4).
The DC-AC converter further includes a first filter reactor (Lu) connected between the first and second main switches (S1, S2) and the first phase AC terminal (3u). ) And a second filter reactor (Lw) connected between the third and fourth main switches (S3, S4) and the third-phase AC terminal (3w). Is desirable.
Further, the DC-AC converter further includes a first and a second connected in reverse parallel to the first, second, third and fourth main switches (S1, S2, S3, S4). It is desirable to have third and fourth main diodes or parasitic diodes (D1, D2, D3, D4).
The auxiliary switch control circuit (6) starts from a first time (t1) slightly before the turn-on time (t3) of at least one of the first to fourth main switches (S1 to S4). The first auxiliary switch (Q1) is controlled to be off and the second auxiliary switch (Q2) is controlled to be on until a second time (t6) slightly after the turn-on time (t3). The relay terminal (4) has a function, and the first time length (Ta) from the first time point (t1) to the turn-on time point (t3) is reduced to the turn-on time point by the action of the resonance reactor (Lr). ) And the second DC terminal (2) is set to a time length during which the voltage between the turn-on time (t3) and the second time point (t6) can be made zero. The time length (Tb) of the resonance reactor It is desirable that the time length is set so that the voltage of the first auxiliary switch (Q1) can be zero or almost zero by the second time point (t6) by the action of Torr (Lr).

According to the invention of each claim, the first and second auxiliary switches (Q1, Q2), the first and second auxiliary diodes (Da, Db), and the resonant reactor (Lr) are specified in the present invention. By connecting to, the electrical stress of the first to fourth main switches (S1 to S4) of the V connection configuration can be reduced, and switching surge, switching noise, and switching loss can be reduced.
Further, the abnormal current is interrupted by detecting the abnormality with the abnormality detecting means and controlling the first auxiliary switch (Q1) to be turned off. Therefore, the first auxiliary switch (Q1) functions for soft switching and also functions as a protective element such as a fuse. For this reason, it is possible to reduce the size and cost of a DC-AC converter having a soft switching function and a protection function, and the individual protection elements are not connected to the main current path. Further, the increase of the wiring impedance can be suppressed, and the increase of the surge voltage based on the on / off of the first to fourth main switches (Q1 to Q4) based on this can be suppressed.
According to the second and third aspects, the surge voltage generated when the first auxiliary switch (Q1) is turned off can be absorbed by providing the voltage clamp circuit.
According to the invention of claim 4, transient surges can be reduced by the first and second transient surge absorbing capacitors (C13, C14) and the first and second resistors (R1, R2). In addition, the breakdown voltage of the first and second clamping capacitors (C11, C12) can be reduced to the same level as the breakdown voltage of the first and second voltage dividing capacitors (Ca, Cb).

  Next, an embodiment of the present invention will be described with reference to FIGS.

  The DC-AC converter or inverter device of Example 1 shown in FIG. 3 is connected to a DC power source composed of a solar cell, a boost chopper, a rectifier, an electrolytic capacitor, a battery, or the like, similarly to the inverter of FIG. 1 and second DC terminals 1 and 2, first and second voltage dividing capacitors Ca and Cb, and first and second main switches S1 and S2 constituting a first phase (U phase) switching circuit. And the third and fourth main switches S3 and S4 constituting the third phase (W phase) switching circuit and the individual or parasitic (internal) connected in parallel to the first to fourth main switches S1 to S4 First to fourth main diodes D1 to D4 made of diodes, first and second reactors Lu and Lw, first and second filter capacitors Cf1 and Cf2, and first, second and third Phase AC terminals 3u, 3v, 3w and The first, second, third and fourth resonance capacitors C1, C2, C3, C4 and the first and second capacitors connected in parallel to the first to fourth main switches S1 to S4 are provided. Auxiliary switches Q1, Q2, first and second auxiliary diodes Da, Db, resonant reactor Lr, main switch control circuit 5, auxiliary switch control circuit 6, and first and second current detectors CTu. , CTw, first and second clamping capacitors C11, C12, first and second transient surge absorbing capacitors C13, C14, first and second resistors R1, R2, and a voltage detection circuit 70 And have. Next, the structure of each part is demonstrated in detail.

  In FIG. 3, the first to fourth main switches S1 to S4 and the first and second auxiliary switches Q1 and Q2 are shown as IGBTs (Insulated Gate Bipolar Transistors). These are NPN type or PNP type. Another controllable semiconductor switch, such as a transistor, a field effect transistor, or the like can be used.

  The first to fourth main diodes D1 to D4 connected in reverse parallel to the first to fourth main switches S1 to S4 may be individual diodes, or the first to fourth main switches S1 to S4. It may be a known parasitic or built-in diode formed in the semiconductor substrate of S4. The first and second auxiliary diodes Da and Db connected in reverse parallel to the first and second auxiliary switches Q1 and Q2 may be individual diodes, or the first and second auxiliary switches. It may be a known parasitic or built-in diode formed in the semiconductor substrate of Q1 and Q2. The first to fourth main diodes D1 to D4 have a direction to regenerate the power of the load connected to the first, second and third phase AC terminals 3u, 3v and 3w to the DC side. The first and second auxiliary diodes Da and Db have a direction that is reverse-biased by the voltage between the first and second DC terminals 1 and 2.

  The first to fourth resonance capacitors C1 to C4, which can also be called snubber capacitors, may be individual capacitors, or between the main terminals of the first to fourth main switches S1 to S4 (between collector and emitter). May be a parasitic capacitance. In FIG. 3, the sum of the capacitance of the individual capacitors and the parasitic capacitance is shown as first to fourth resonance capacitors C1 to C4.

  The first and second voltage dividing capacitors Ca and Cb made of electrolytic capacitors are connected between the first and second DC terminals 1 and 2 and are connected in series with each other. The second-phase AC terminal 3v is connected to an interconnection point between the first and second voltage dividing capacitors Ca and Cb.

  The inverter device of FIG. 3 has a relay terminal 4. The relay terminal 4 here means a connecting conductor, a part of an electric circuit, or a boundary point between a soft switching circuit and an inverter circuit.

  The first auxiliary switch Q1 is connected between the first DC terminal 1 and the relay terminal 4 so as to flow current from the first DC terminal 1 toward the relay terminal 4.

The series circuit of the second auxiliary switch Q2 and the resonant reactor Lr is connected to the junction point of the relay terminal 4, the second phase AC terminal 3v, and the first and second voltage dividing capacitors Ca and Cb. The second auxiliary switch Q2 has a direction of flowing current from the relay terminal 4 to the second voltage dividing capacitor Cb.
The resonance reactor Lr as an inductor resonates with the first to fourth resonance capacitors C1 to C4 and can also be called a commutation reactor.

  The first, second, and third phase AC terminals 3u, 3v, 3w output the first, second, and third line voltages Vuv, Vvw, Vwu having a phase difference of 120 degrees from each other. When the first to fourth main switches S1 to S4 are operating as inverters, they function as first, second and third phase output AC terminals.

  The first main switch S1 of the inverter circuit is connected between the relay terminal 4 and the first phase AC terminal 3u via a first reactor Lu. The second main switch S2 is connected between the first phase AC terminal 3u and the second DC terminal 2 via the first reactor Lu. The third main switch S3 is connected between the relay terminal 4 and the third phase AC terminal 3w via a second reactor Lw. The fourth main switch S4 is connected between the third-phase AC terminal 3w and the second DC terminal 2 via the second reactor Lw. Accordingly, the first and second main switches S1 and S2 constitute a first-phase (U-phase) half-bridge conversion circuit, and the third and fourth main switches S3 and S4 are third-phase (W-phase) half-bridges. A conversion circuit is configured.

The first reactor Lu is connected in series between the interconnection point of the first and second main switches S1, S2 and the first phase AC terminal 3u. The second reactor Lw is connected in series between the interconnection point of the third and fourth main switches S3 and S4 and the third phase AC terminal 3w. The first and second reactors Lu and Lw function as filters that remove high-frequency components due to on / off of the first to fourth main switches S1 to S4.
The first filter capacitor Cf1 is connected between the first and second phase AC terminals 3u, 3v. The second filter capacitor Cf2 is connected between the second and third phase AC terminals 3v and 3w. The first and second filter capacitors Cf1 and Cf2 are for removing high-frequency components due to on / off of the first to fourth main switches S1 to S4.
The capacities of the first to fourth resonance capacitors C1 to C4 and the capacities of the first and second filter capacitors Cf1 and Cf2 are much larger than the capacities of the first and second voltage dividing capacitors Ca and Cb. Small.

  First and second clamping capacitors C11 and C12 for constituting a voltage clamping circuit are connected in parallel to the first auxiliary switch Q1 via a backflow prevention diode D11. That is, one end of the first clamping capacitor C11 is connected to an interconnection point between the first auxiliary switch Q1 and the first voltage dividing capacitor Ca. One end of the second clamping capacitor C12 is connected to the other end of the first clamping capacitor C11. The reverse current blocking diode D11 is connected between the other end of the second clamping capacitor C12 and the emitter of the first auxiliary switch Q1. The first and second clamping capacitors C11 and C12 are polar capacitors such as electrolytic capacitors, for example, and are relatively large capable of absorbing the current flowing immediately before the first auxiliary switch Q1 is turned off. The first auxiliary switch Q1 has a capacity and is charged so that one end side of the first auxiliary switch Q1 has a positive potential. Since the electrolytic capacitor has a relatively large capacity despite being relatively small, it is suitable as the first and second clamping capacitors C11 and C12.

  The first and second transient surge absorbing capacitors C13 and C14 are nonpolar capacitors such as film capacitors having a smaller capacity than the first and second clamping capacitors C11 and C12. The clamp capacitors C11 and C12 are respectively connected in parallel. That is, one end of each of the first and second transient surge absorbing capacitors C13 and C14 is connected to one end of each of the first and second clamp capacitors C11 and C12, and the first and second transient surge absorbing capacitors C13. , C14 is connected to the other ends of the first and second clamping capacitors C11, C12, respectively. In order to reduce the withstand voltage of the first and second clamping capacitors C11 and C12, the first clamping capacitor C11 is connected in parallel to the first voltage dividing capacitor Ca through the first resistor R1, The second clamping capacitor C12 is connected in parallel to the second voltage dividing capacitor Cb via the second resistor R2. That is, the interconnection point between the first and second transient surge absorbing capacitors C13 and C14 is connected to the interconnection point between the first and second voltage dividing capacitors Ca and Cb via the first resistor R1. The other end of the second transient surge absorbing capacitor C14 is connected to the second DC terminal 2 via the second resistor R2.

  In order to form the first to fourth main switch control signals Vg1, Vg2, Vg3, Vg4 for the first to fourth main switches S1 to S4, first and second current detectors CTu, CTw and A main switch control circuit 5 is provided. Further, an auxiliary switch control circuit 6 is provided to form control signals Vq1 and Vq2 for the first and second auxiliary switches Q1 and Q2. The first and second current detectors CTu and CTw detect the currents Iu and Iw flowing through the first and second reactors Lu and Lw, and the main switch control circuit 5 and the auxiliary switch control circuit 6 are detected by lines 7 and 8, respectively. Send to. The main switch control circuit 5 has first, second, third and fourth output lines 9, 10, 11 and 12 for the first, second, third and fourth main switches S1, S2, S3 and S4. The control terminal (gate) is connected via a drive circuit (not shown). The main switch control circuit 5 has a first to a fourth main switch control signals Vg1 to Vg1 in a well-known manner so that a three-phase AC voltage can be obtained at the first, second and third phase AC terminals 3u, 3v and 3w. Vg4 is formed.

The auxiliary switch control circuit 6 is connected to the lines 7 and 8 for detecting the currents Iu and Iw, and is connected to the main switch control circuit 5 by the line 15, and when the first to fourth main switches S1 to S4 are turned on. The first and second for previously setting the voltage of the first to fourth resonance capacitors C1 to C4 and the voltage between the relay terminal 4 and the second DC terminal 2 to zero or almost zero lower than the power supply voltage. Two auxiliary switch control signals Vq1 and Vq2 are formed and sent to lines 13 and 14, respectively. The lines 13 and 14 are connected to control terminals (gates) of the first and second auxiliary switches Q1 and Q2 through a drive circuit (not shown).
The auxiliary switch control circuit 6 is connected to a voltage detection circuit 70 as a part of the abnormality detection means by a line 71, and has a function of turning off the first auxiliary switch Q1 when an abnormality occurs. The voltage detection circuit 70 detects the voltage between the main terminals of the first auxiliary switch Q1, that is, the collector-emitter voltage Vce, and sends the detected value to the auxiliary switch control circuit 6 via the line 71. In place of the voltage detection circuit 70, a current detector 70a such as a CT (current transformer) is provided on a line through which a current passes through the first auxiliary switch Q1 as shown by a dotted line in FIG. The current through the switch Q1 can be detected and this detected value can be sent to the auxiliary switch control circuit 6 via the line 71. Further, instead of providing the individual current detector 70a, the current detecting means can be provided integrally with the first auxiliary switch Q1 made of IGBT or the like. Further, for abnormality detection, a gate voltage drop can be detected by a so-called RTC circuit incorporated in the first auxiliary switch Q1 made of IGBT, and this can be used for abnormality detection.

  FIG. 4 is a circuit diagram showing in detail the main switch control circuit 5 and the auxiliary switch control circuit 6 of FIG. The main switch control circuit 5 includes a voltage reference value generator 51, a sawtooth generator 52, first and second comparators 53 and 54, which are formed in the same manner as the conventional inverter control circuit of FIG. In addition to the signal forming circuit 55, a U-phase correction circuit 56 as a first correction circuit and a W-phase correction circuit 57 as a second correction circuit are provided.

  The voltage reference value generator 51 repeatedly generates the first and second voltage reference values Vru and Vrw shown in FIGS. 5B and 5C with a period Tac. The first voltage reference value Vru is the same sine wave as the line voltage Vuv between the first phase, that is, the U phase and the second phase, ie, the V phase, of the three-phase sine wave AC voltage, and the second voltage reference value. Vrw is the same sine wave as the negative phase line voltage Vwv having a phase difference of 180 degrees with respect to the line voltage Vvw between the second phase, ie, the V phase and the third phase, ie, the W phase. Accordingly, as shown in FIGS. 5B and 5C, the first and second voltage reference values Vru and Vrw have a phase difference of 60 degrees, and the second voltage reference value Vrw is the first voltage reference value Vrw. It is 60 degrees ahead of the voltage reference value Vru. Note that the first and second voltage reference values Vru and Vrw in FIGS. 5B and 5C are the same as the first and second voltage reference values Vru and Vrw shown in FIG. When the first voltage reference value Vru is used as a reference, the second voltage reference value Vrw is delayed by 300 degrees from the first voltage reference value Vru.

  The sawtooth generator 52 generates the sawtooth voltage Vt shown in FIG. 5A at a frequency (for example, 20 kHz) sufficiently higher than the frequency (for example, 50 Hz) of the first and second voltage reference values Vru and Vrw. The sawtooth voltage Vt rises at an inclination and then falls vertically. Of course, a sawtooth voltage having a slope opposite to that of the sawtooth voltage Vt in FIG. The U-phase and W-phase correction circuits 56 and 57 are connected between the sawtooth generator 52 and the first and second comparators 53 and 54, and output lines of the first and second current detectors CTu and CTw. The phase of the sawtooth voltage Vt is controlled in response to the signals 7 and 8. That is, as shown in FIG. 5B, the U-phase correction circuit 56 performs the saw operation shown in FIG. 5A during the period t0 to t3 when the U-phase load current Iu shown in FIG. The same phase sawtooth voltage as the wave voltage Vt is output, and the sawtooth voltage Vt of the phase opposite to that of the sawtooth voltage Vt in FIG. 5A is output during the period t3 to t6 when the U phase load current Iu is negative half wave. Output. A first corrected sawtooth voltage Vtu, which is a combination of the positive phase sawtooth voltage and the negative phase sawtooth voltage shown in FIG. 5B, is input to the first comparator 53.

  As shown in FIG. 5 (C), the W-phase correction circuit 57 is shown in FIG. 5 (A) in the periods to to t1 and t4 to t6 in which the W-phase load current Iw shown in FIG. A positive-phase sawtooth voltage equal to the sawtooth voltage Vt is output, and a negative-phase sawtooth voltage is output during a period t1 to t4 in which the W-phase load current Iw is negative half-wave. A second sawtooth voltage Vtw that is a combination of the positive-phase sawtooth voltage and the negative-phase sawtooth voltage shown in FIG. 5C is input to the second comparator 54. As is apparent from FIGS. 5B and 5C, the intermediate position between the positive and negative peaks of the first and second voltage reference values Vru and Vrw and the first and second corrected sawtooth voltages Vtu, The respective levels are set so that the intermediate positions of the positive and negative peaks of Vtw coincide with each other.

  The first and second comparators 53 and 54 connected to the voltage reference value generator 51, the U-phase and W-phase correction circuits 56 and 57, and the main switch control signal forming circuit 55 are shown in FIG. ), The first and second voltage reference values Vru, Vrw are compared with the first and second corrected sawtooth voltages Vtu, Vtw, and the first and second voltage reference values Vru, Vtw shown in FIGS. 3 main switch control signals Vg1 and Vg3 are formed and sent to the main switch control signal forming circuit 55. The first and second comparators 53 and 54 have a high level, that is, a logic level when the first and second voltage reference values Vru and Vrw are larger than the first and second corrected sawtooth voltages Vtu and Vtw. 1 is output, and other than this, low level, that is, logic 0 is output.

  The main switch control signal forming circuit 55 receives the first and third main switch control signals Vg1 and Vg3 formed by the first and second comparators 53 and 54 via the lines 9 and 11 and the first switch shown in FIG. And second and fourth main switch control signals Vg2 and Vg4, which are made of opposite phase signals of the first and third main switch control signals Vg1 and Vg3, and are sent to the control terminals of the third main switches S1 and S3. Then, the signals are sent to the control terminals of the second and fourth main switches S2 and S4 in FIG. The main switch control signal forming circuit 55 includes a known dead time giving means. This dead time providing means prevents the first and second main switches S1, S2 from being turned on at the same time, and prevents the third and fourth main switches S3, S4 from being turned on at the same time. A period is provided.

  The auxiliary switch control circuit 6 shown in FIG. 4 has a function for controlling on / off of the first and second auxiliary switches Q1, Q2 so that the first to fourth main switches S1-S4 can be soft-switched, and a first function. A Vta setting circuit 58 for setting the first voltage level Vta in order to obtain a function of protecting the circuit by turning off the first auxiliary switch Q1 when the auxiliary switch Q1 and the circuit on the output side thereof are abnormal. A Vtb setting circuit 59 for setting the second voltage level Vtb, third and fourth comparators 60 and 61, an exclusive OR circuit 62, a NOT circuit 63, an abnormality detection circuit 72, and an off control switch 73. Have. Note that the sawtooth generator 52 can be included in the auxiliary switch control circuit 6.

The Vta setting circuit 58 sets the first voltage level Vta shown on the upper side of FIG. 6A and supplies it to the third comparator 60. The Vtb setting circuit 59 sets a second voltage level Vtb shown on the lower side of FIG. 6A and supplies it to the fourth comparator 61. The Vta setting circuit 58 and the Vtb setting circuit 59 include calculation means, and are based on the U-phase and W-phase load currents Iu and Iw of the lines 7 and 8 and the constants of the respective parts in FIG. The first and second voltage levels Vta and Vtb are determined so that the .about.t3 period Ta and the t3 to t6 period Tb have the optimum time length. At this time, the first and second voltage levels Vta and Vtb are determined in consideration of the amplitude of the sawtooth voltage Vt.
Since the first and second voltage levels Vta and Vtb determine the on / off timings of the first and second auxiliary switches Q1 and Q2, they can also be referred to as first and second timing signal command values. The first and second voltage levels Vta and Vtb can be set to constant values across the sawtooth voltage Vt. In this embodiment, the U-phase load current Iu and the W-phase load current Iw are changed. Switching is performed accordingly. For this purpose, the Vta setting circuit 58 and the Vtb setting circuit 59 are connected to the detection lines 7 and 8 for the U-phase and W-phase load currents Iu and Iw.

An example of an arithmetic expression for setting the first and second voltage levels Vta and Vtb by the Vta setting circuit 58 and the Vtb setting circuit 59 is shown below.
When Iu <0, Iw <0,
Vta = Vt.times. [1-{(2.times.Lr.times. (Iu '+ Iw')) / Vdc + .pi..sqroot. (Lr.times.C)} / T]
Vtb = Vt × [2 × Lr x {(Iu ′ + Iw ′)} / Vdc + π√ (Lr × C)] / T
When Iu <0, Iw> 0,
Vta = Vt * [1-{(2xLr x (Iu ')) / Vdc + π√ (Lr xC)} / T]
Vtb = Vt × [2 × Lr x {(Iu ′ + Iw ′)} / Vdc + π√ (Lr × C)] / T
When Iu> 0, Iw <0,
Vta = Vt * [1-{(2xLr x (Iw ')) / Vdc + π√ (Lr xC)} / T]
Vtb = Vt × [2 × Lr x {(Iw ′ + Iu ′)} / Vdc + π√ (Lr × C)] / T
When Iu> 0 and Iw> 0,
Vta = Vt × [1- {π√ (Lr × C)} / T]
Vtb = Vt × [2 × Lr x {(Iw ′ + Iu ′)} / Vdc + π√ (Lr × C)] / T
Where Vt is the sawtooth voltage in FIG.
Vdc is the maximum amplitude of the sawtooth voltage Vt,
T is the period of the sawtooth voltage Vt,
Lr is the inductor value of the resonant reactor Lr in FIG.
C is a capacity between the relay terminal 4 and the second DC terminal 2, that is, C1 + C4 or C2 + C3 or C1 + C3 or C2 + C4,
Iu 'and Iw' are absolute values of U-phase and W-phase load currents Iu and Iw.

  The third comparator 60 is connected to the Vta setting circuit 58 and the line 15, and compares the sawtooth voltage Vt of the line 15 connected to the sawtooth generator 52 with the first voltage level Vta. When the sawtooth voltage Vt is higher than the first voltage level Vta, the signal Pta shown in FIG. The first voltage level Vta is set to a value slightly lower than the maximum value of the sawtooth voltage Vt.

  The fourth comparator 61 is connected to the Vtb setting circuit 59 and the line 15, compares the sawtooth voltage Vt of the line 15 with the second voltage level Vtb, and the second voltage level Vtb is the sawtooth voltage Vt. When it is higher than that, the signal Ptb of FIG.

The exclusive OR circuit 62 is connected to the third and fourth comparators 60 and 61, and is high when the signals Pta and Ptb output from the third and fourth comparators 60 and 61 are at different voltage levels. A level signal is generated as shown in FIG. The output of the exclusive OR circuit 62 becomes a first auxiliary switch control signal Vq1 for controlling the first auxiliary switch Q1. A NOT circuit 63 connected to the exclusive OR circuit 62 inverts the phase of the output of the exclusive OR circuit 62, and a second auxiliary switch control signal for controlling the second auxiliary switch Q2 shown in FIG. 6D. Vq2 is output. The first and second auxiliary switch control signals Vq1 and Vq2 are sent to the control terminals of the first and second auxiliary switches Q1 and Q2 of FIG.
The third comparator 60 is modified so that the output of the third comparator 60 becomes a low level, that is, a logic 0 when the sawtooth voltage Vt is higher than the first voltage level Vta, and the exclusive OR is performed. The circuit 62 can be transformed into an AND gate. Further, another logic circuit equivalent to the exclusive OR circuit 62 can be provided.

  An off control switch 73 serving as an off control means is connected in series to the line 13 leading to the gate of the first auxiliary switch Q1. The off control switch 73 is always kept on when normal, and is controlled off when abnormal.

  The abnormality detection circuit 72 for constituting the abnormality detection means with the voltage detection circuit 70 or the current detector 70a includes a comparator 74, a reference voltage source 75, and a holding circuit 76. One input terminal of the comparator 74 is connected to the line 71, and the other input terminal is connected to the reference voltage source 75. The output terminal of the comparator 74 is connected to a holding circuit 76 composed of, for example, an RS flip-flop or a timer. The holding circuit 76 is connected to the control terminal of the off control switch 73. Therefore, when the level of the signal obtained from the voltage detection circuit 70 or the current detector 70a in FIG. 3 becomes higher than the reference value indicating the abnormality of the reference voltage source 75, the output of the comparator 74 is changed from a low level to a high level, for example. Then, the abnormality is detected, the output indicating the abnormality of the comparator 74 is held by the holding circuit 76, and the off control switch 73 is turned off by the output of the holding circuit 76.

Next, operations of the inverter circuit and the soft switching circuit of FIG. 3 will be described with reference to the waveform diagram of FIG. 7 and the current path diagrams of FIGS. In the following description, the current path may be indicated only by reference numerals of circuit elements.
7, 8 and 9 show the states of the respective parts at the timing when the U-phase load current Iu is larger than zero, the V-phase load current Iv is zero, and the W-phase load current Iw is smaller than zero. Further, the time points t1, t3, and t6 in FIG. 7 indicate the same time points as the time points t1, t3, and t6 in FIG. 7 is a time sufficiently shorter than the period T of the sawtooth voltage Vt (for example, T / 20 to T / 10). Further, the current I _Lr in FIG. 7E indicates the current of the resonant reactor Lr. Further, the DC link voltage Vlink of FIG. 7 (F) is the series circuit of the first and second main switches S1, S2 or the series of the third and fourth main switches S3, S4 as shown in FIG. 8 (A). Indicates the voltage across the circuit. In FIG. 7G, Vs1 indicates a voltage between both terminals of the first main switch S1, and Is1 indicates a current flowing through the first main switch S1 and the first main diode D1. Vs1 is referred to as a first main switch voltage, and Is1 is referred to as a first main switch current.
8 and 9, a current path through which a current flows is indicated by a thick line, and a portion where the current does not substantially flow is indicated by a thin line. Further, the first and second DC terminals 1 and 2 are omitted in FIGS. Further, arrows indicating current directions and values indicating relative levels of current values are attached to the U-phase, V-phase, and W-phase AC terminals 3u, 3v, and 3w.

(Before t1)
Before the time t1 in FIG. 7, the first and fourth main switches S1 and S4 are turned off, the second and third main switches S2 and S3 are turned on, and the first auxiliary switch Q1 is turned on. The second auxiliary switch Q2 is off-controlled. Since the first and fourth main switches S1 and S4 are on during the period before the time t0 in FIG. 6, a positive U-phase load current Iu flows through the first reactor Lu, and the second reactor Lw. W-phase load current Iw flows in the negative direction, energy is accumulated in the first and second reactors Lu and Lw, and the first and second reactors are turned off during the off period of the first and fourth main switches S1 and S4. The stored energy of Lu and Lw is released, and a current flows through the path of Lu-3u-3w-Lw-D3-Da-Ca-Cb-D2. At this time, the voltage Vs1 between both terminals of the first main switch S1 is kept substantially at the power supply voltage Vdc as shown in FIG. The power supply voltage Vdc corresponds to the sum of the voltage between the first and second DC terminals 1 and 2 and the voltage of the first and second voltage dividing capacitors Ca and Cb. At this time, the DC link voltage Vlink in FIG. 7F is substantially the same as the power supply voltage Vdc.

(T1 to t2)
When the first auxiliary switch Q1 is turned off and the second auxiliary switch Q2 is turned on at time t1 in FIG. 7, in addition to the current path of FIG. 8A, Lu-3u-3w-Lw- D3 -Q2 -lR the path of -Cb -D2 current I _Lr in the resonant reactor Lr shown in FIG. 7 (E) starts to flow. This current I _Lr increases with time. That is, a part of the current flowing through the first auxiliary diode Da in FIG. 8A is commutated to the resonant reactor Lr, and the current of the first auxiliary diode Da is gradually decreased, and conversely, the current of the resonant reactor Lr. I _Lr gradually increases. Therefore, the turn-off of the first auxiliary switch Q1 is zero voltage switching (ZVS), and the turn-on of the second auxiliary switch Q2 is zero current switching (ZCS).

(T2 to t3)
When the current passing through the first auxiliary diode Da becomes zero at time t2 in FIG. 7, the current in the path of Lu-3u-3w-Lw-D3-Q2-Lr-Cb-D2 is the same as in FIG. In addition, a resonance current in the path C1-Q2-Lr-Cb-D2 and a resonance current in the path C4-D3-Q2-Lr-Cb flow, and the voltages of the first and fourth resonance capacitors C1, C4 The DC link voltage Vlink shown in FIG. 7 (F), the voltage Vs1 between both terminals of the first main switch S1 shown in FIG. 7 (G), and both terminals of the fourth main switch S4 not shown are gradually decreased. The voltage in between decreases gradually and becomes almost zero before time t3. The current I _Lr flowing through the resonant reactor Lr gradually decreases after a slight overshoot at time t2 in FIG.

(T3 to t4)
At time t3, the first and fourth main switches S1 and S4 are simultaneously turned on. As shown in FIGS. 5B and 5C, the first and fourth main switches S1 and S4 are simultaneously turned on and the second and third main switches S2 and S3 are simultaneously turned on. This is achieved by forming the second corrected sawtooth voltages Vtu and Vtw. The turn-on of the first and fourth main switches S1 and S4 at time t3 in FIG. 7 is zero voltage switching (ZVS). In addition, since the currents of the first and fourth main switches S1 and S4 increase with a slope from the time point t3, these turn-ons also become zero current switching (ZCS). When the first and fourth main switches S1 and S4 are turned on at time t3, the current of the path Lu-3u-3w-Lw-D3-S1, the current of the path Lu-3u-3w-Lw-S4-D2 flow, current I _Lr path Lu -3u-3w-Lw -D3 -Q2 -Lr -Cb -D2 decreases toward zero as shown in FIG. 7 (E).

(T4 to t5)
After the current I _Lr in the resonant reactor Lr becomes zero at the time t4 shown in FIG. 7 (E), the current I _Lr flows in the opposite direction. That is, the t4 t5 period, as shown in FIG. 8 (E), the current I _Lr path Lu -3u-3w-Lw -S4 -Cb -Lr -Db -S1, Lu -3u-3w- The current in the path Lw-D3-S1 and the current in the path Lu-3u-3w-Lw-S4-D2 flow. While the current I _Lr flowing in the reverse direction through the resonant reactor Lr is smaller than the current flowing through the third main diode D3, charging of the second and third resonance capacitors C2 and C3 does not start, and FIG. The DC link voltage Vlink is maintained at zero or almost zero.

(T5 to t6)
When the current I _Lr in the resonant reactor Lr in time t5 of FIG. 7 is greater than the current of the second and third main diodes D2, D3, now the second and third main diodes D2, D3 are turned off, Fig. 9 The second resonance capacitor C2 is charged through the path Lr-Db-S1-C2-Cb shown in FIG. 5A, and at the same time the third resonance capacitor C3 is charged through the path Lr-Db-C3-S4-Cb. Then, the DC link voltage Vlink in FIG. 7F gradually increases and becomes the power supply voltage Vdc before time t6.

(T6-t7)
Since the DC link voltage Vlink is the same or substantially the same as the power supply voltage Vdc at time t6 in FIG. 7, the voltage between both terminals of the first auxiliary switch Q1 is zero or almost zero. Therefore, when the first auxiliary switch Q1 is turned on at time t6 as shown in FIG. 7C, zero voltage switching (ZVS) is achieved. In this embodiment, the second auxiliary switch Q2 is turned off at time t6 in order to easily form the control signals Vq1 and Vq2 of the first and second auxiliary switches Q1 and Q2. However, since no current flows through the second auxiliary switch Q2 from the time point t4, the turn-off control can be performed at the time point t4 or later. The turn-off control of the second auxiliary switch Q2 is preferably performed during the period from t4 to t7 during which the second auxiliary diode Db flows for zero voltage switching (ZVS).
During the period from t6 to t7, a current flows through the path of Cb-Ca-Q1-S1-Lu-3u-3w-Lw-S4, and Lr-Db-S1-Lu-3u-3w-Lw-Sw-S4-Cb A current flows through the path, and the remaining energy of the resonant reactor Lr is regenerated to the load side.

(After t7)
When the release of the energy stored in the resonant reactor Lr is completed at time t7, the second auxiliary diode Db is in a reverse bias state, and Cb-Ca-Q1-S1-Lu-3u-3w-Lw- shown in FIG. Current flows through the path of S4.

After t7 in FIG. 7, the same operation as that in FIGS. 7 to 9 is performed before and after the third main switch S3 is turned on and the fourth main switch S4 is turned off. Occurs.
Further, even when the U-phase, V-phase, and W-phase load currents Iu, Iv, and Iw are different in magnitude from the states shown in FIGS. 7 to 9, substantially the same operations as in FIGS. 7 to 9 occur.

Next, the operation at the time of abnormality of the first auxiliary switch Q1 and the output side circuit will be described with reference to FIG.
For example, for some reason, both ends of the arm of the inverter, that is, between the relay terminal 4 and the second DC terminal 2 are short-circuited, and the first auxiliary switch Q1 is turned on from time t0 as shown in FIG. When the passing current increases and this current reaches a predetermined level (for example, 2000 A) at time t1, the voltage Vce between the collector and the emitter of the first auxiliary switch Q1 made of IGBT also increases, and the output of the voltage detection circuit 70 is The reference voltage source 75 in FIG. 4 becomes higher than the reference voltage, and a high level output indicating abnormality is generated from the comparator 74, and this is held by the holding circuit 76. Accordingly, the off control switch 73 is off-controlled by the output of the holding circuit 76, the supply of the control signal Vq1 of the first auxiliary switch Q1 is cut off, and the first auxiliary switch Q1 is turned off. The current flowing through the first auxiliary switch Q1 is commutated to the first and second clamping capacitors C11 and C12 and absorbed therein. The currents of the first and second clamping capacitors C11 and C12 flow through a path of Ca-C11-C12-D11-S1, S3-S2, or S4-Cb.
Since the capacities of the first and second clamping capacitors C11 and C12 are large, the terminal voltage Vx of the first and second clamping capacitors C11 and C12 is the first auxiliary switch as shown in FIG. It only rises slightly after the turn-off time t1 of Q1, and can be suppressed to 400V or less, for example. The first and second transient surge absorbing capacitors C13 and C14 are capable of responding to a higher frequency than the first and second clamping capacitors C11 and C12, and generate transients when the first auxiliary switch Q1 is turned off. Absorbs surge. The maximum value of the terminal voltage Vy of the first and second transient surge absorbing capacitors C13 and C14 is about 480 V, for example, and this terminal voltage Vy oscillates at a period of about 2 μsec, for example, as shown in FIG. . The first clamp capacitor C11 and the first transient surge absorbing capacitor C13 are connected in parallel to the first clamp capacitor Ca via the first resistor R1, and the second clamp capacitor C12 and the second clamp capacitor C12 are connected to the first clamp capacitor Ca. The transient surge absorbing capacitor C14 is connected in parallel to the second voltage dividing capacitor Cb via the second resistor R2. Accordingly, the terminal voltage Vx of the first and second clamping capacitors C11 and C12 and the voltage Vy of the first and second transient surge absorbing capacitors C13 and C14 are limited to be excessive.

According to the first embodiment, the following effects can be obtained.
(1) Soft switching of the first to fourth main switches S1 to S4 can be achieved with a relatively simple circuit, and surge, noise, and switching loss can be reduced.
(2) Soft switching of the first and second auxiliary switches Q1, Q2 is also achieved.
(3) Since the inverter circuit has a V-connection configuration, the number of main switches can be reduced as compared with the power converter of Patent Document 1, and the power converter can be reduced in size and cost. .
(4) By detecting an abnormality with the abnormality detection circuit 72 and controlling the first auxiliary switch Q1 to be off, the abnormal current is interrupted. Therefore, the first auxiliary switch Q1 functions as soft switching and also functions as a protective element such as a fuse. For this reason, it is possible to reduce the size and cost of a DC-AC converter having a soft switching function and a protection function.
(5) Since the individual protection elements are not connected to the main current path, the power loss can be reduced here, and further, the first to fourth main switches Q1 to Q1 based on this can be suppressed by suppressing the increase of the wiring impedance. Increase in surge voltage due to on / off of Q4 can be suppressed.
(6) By providing the first and second clamping capacitors C11 and C12, the surge voltage generated when the first auxiliary switch Q1 is turned off can be absorbed.
(7) By providing the first and second transient surge absorbing capacitors (C13, C14) and the first and second resistors (R1, R2), the transient surge can be reduced and the first and second The breakdown voltage of the second clamping capacitors (C11, C12) can be made as low as the breakdown voltage of the first and second voltage dividing capacitors (Ca, Cb).

The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.
(1) The abnormality detection circuit 72 of FIG. 4 can be modified to the abnormality detection circuit 72a of FIG. The abnormality detection circuit 72a shown in FIG. 11 includes first and second AND circuits 77 and 78, an OR circuit 79, and a holding circuit 76 that is the same as that shown in FIG. The input lines 9a and 10a of the first AND circuit 77 are connected to the lines 9 and 10 in FIG. 3, and the input lines 11a and 12a of the second AND circuit 78 are connected to the lines 11 and 12 in FIG. Therefore, when the control signals Vg1 and Vg2 of the first and second main switches S1 and S2 are simultaneously at a high level due to an abnormality of the main switch control circuit 5 or for some reason, the output of the first AND circuit 77 shows an abnormality. This becomes high level, and this is sent to the control terminal of the off control switch 73 via the OR circuit 79 and the holding circuit 76, and the off control switch 73 is controlled to be off. Similarly, when the control signals Vg3 and Vg4 of the third and fourth main switches S3 and S4 simultaneously become high level, the output of the second AND circuit 78 becomes high level, and this is output via the OR circuit 76. The control signal is sent to the control terminal of the off control switch 73, and the off control switch 73 is turned off. According to the abnormality detection circuit 72a of FIG. 11, the voltage detection circuit 70 or the current detector 70a of FIG. 3 becomes unnecessary.
(2) The first and second storage batteries having the same voltage can be connected in place of the first and second voltage dividing capacitors Ca and Cb having the same capacity.
(3) When the load connected to the first phase, second phase, and third phase AC terminals 3u, 3v, 3w has a filter action, the first and second reactors Lu, Lw and the first and second Any one or both of the filter capacitors Cf1, Cf2 can be omitted.
(4) The first to fourth main switch control signals Vg1 to Vg4 for the first to fourth main switches S1 to S4 can be formed as shown in FIGS.
(5) The off control switch 73 can be modified to an off control means 73a comprising a logic circuit shown in FIG. 12 includes a NOT circuit 81 and an AND circuit 82. The NOT circuit 81 is connected to the output terminal of the holding circuit 76 shown in FIG. One input terminal of the AND circuit 82 is connected to the NOT circuit 81, and the other input terminal is connected to, for example, the exclusive OR circuit 62 of FIG. The output terminal of the AND circuit 82 is connected by a line 13 to the control terminal of the first auxiliary switch Q1. When an abnormality is detected, the output of the AND circuit 82 controls the first auxiliary switch Q1 to be turned off.

  The present invention is applicable to a DC-AC converter, that is, an inverter device.

It is a circuit diagram which shows the conventional DC-AC converter. It is a wave form diagram which shows the state of each part of FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram illustrating a DC-AC converter according to Embodiment 1 of the present invention. FIG. 4 is a block diagram illustrating a main switch control circuit and an auxiliary switch control circuit of FIG. 3. FIG. 5 is a waveform diagram schematically showing the state of each part in FIGS. 3 and 4. It is a wave form diagram which shows the state of each part of FIG. 4 in detail. It is a wave form diagram which shows the state of each part of FIG. 3 in the time of the turn-on of a 1st main switch, and its vicinity. FIG. 8 is a circuit diagram showing current paths in a plurality of divided sections in FIG. 7. FIG. 8 is a circuit diagram showing a current path in another divided section of FIG. 7. It is a wave form diagram which shows the state of each part of FIG. 3 when a 1st auxiliary switch is turned off. It is a circuit diagram which shows the deform | transformed abnormality detection circuit. It is a circuit diagram which shows the OFF control means of a modification.

Explanation of symbols

1, 2 1st and 2nd DC terminal 3u, 3v, 3w 1st, 2nd and 3rd phase AC terminal 4 Relay terminal 5 Main switch control circuit 6 Auxiliary switch control circuit 72, 72a Abnormality detection circuit S1-S4 1st 1st to 4th main switches Q1 and Q2 1st and 2nd auxiliary switches C1 to C4 1st to 4th resonance capacitors Lr Resonance reactors C11 and C12 1st and 2nd clamp capacitors C13 and C14 1st And second transient surge absorbing capacitor D11 reverse current blocking diodes R1, R2 first and second resistors

Claims (8)

First and second DC terminals (1, 2);
First, second and third phase AC terminals (3u, 3v, 3w);
A relay terminal (4);
A first voltage dividing capacitor (Ca) connected between the first DC terminal (1) and the second phase AC terminal (3v);
A second voltage dividing capacitor (Cb) connected between the second DC terminal (2) and the second phase AC terminal (3v);
A first main switch (S1) connected between the relay terminal (4) and the first phase AC terminal (3u);
A second main switch (S2) connected between the first phase AC terminal (3u) and the second DC terminal (2);
A third main switch (S3) connected between the relay terminal (4) and the third phase AC terminal (3w);
A fourth main switch (S4) connected between the third phase AC terminal (3w) and the second DC terminal (2);
First, second, third and fourth resonance capacitors or parasitic capacitances connected in parallel to the first, second, third and fourth main switches (S1, S2, S3, S4), respectively. C1, C2, C3, C4),
A first auxiliary switch (Q1) connected between the first DC terminal (1) and the relay terminal (4);
A first auxiliary diode or parasitic diode (Da) connected in reverse parallel to the first auxiliary switch (Q1);
A series circuit of a second auxiliary switch (Q2) and a resonant reactor (Lr) connected between the relay terminal (4) and the second phase AC terminal (3v);
A second auxiliary diode or parasitic diode (Db) connected in reverse parallel to the second auxiliary switch (Q2);
The first, second, third, and fourth so that a three-phase AC voltage (Vuv, Vvw, Vwu) can be obtained at the first, second, and third phase AC terminals (3u, 3v, 3w). A main switch control circuit (5) for controlling on / off of the main switches (S1, S2, S3, S4) at a repetition frequency higher than the frequency of the three-phase AC voltage;
The voltage of the first, second, third and fourth resonance capacitors or parasitic capacitances (C1, C2, C3, C4) is set to the first, second, third and fourth main switches (S1, S2). , S3, S4), and an auxiliary switch control circuit (6) for controlling on / off of the first and second auxiliary switches (Q1, Q2) so that they can be reduced to zero or almost zero by the time of turn-on. ,
An abnormality detecting means (70 or 70a and 72, or 72a) for detecting an abnormality of the first auxiliary switch (Q1) and a circuit on the output side from the first auxiliary switch (Q1);
DC-AC conversion characterized by having off control means (73 or 73a) for controlling the first auxiliary switch (Q1) to be turned off in response to an output indicating an abnormality of the abnormality detecting means. apparatus.   2. The DC-AC converter according to claim 1, further comprising a voltage clamp circuit connected in parallel to the first auxiliary switch (Q1).   3. The DC-AC circuit according to claim 2, wherein the voltage clamping circuit comprises a series circuit of first and second clamping capacitors (C11, C12) having polarity and a reverse current blocking diode (D11). Conversion device. A first transient surge absorbing capacitor (C13) connected in parallel to the first clamping capacitor (C11) and having one end connected to the first DC terminal (1);
A second transient surge absorbing capacitor (C14) connected in parallel to the second clamp capacitor (C12) and having one end connected to the other end of the first transient surge absorbing capacitor (C13);
The first and second transient surge absorbing capacitors (C13, C14) are connected between the interconnection point and the first and second voltage dividing capacitors (Ca, Cb). 1 resistance (R1),
And a second resistor (R2) connected between the other end of the second transient surge absorbing capacitor (C14) and the second DC terminal (2). The DC-AC converter according to claim 3.   The abnormality detection means includes a voltage between terminals of the first auxiliary switch (Q1), a current flowing through the first auxiliary switch (Q1), or the first, second, third, and fourth. 5. The DC-AC converter according to claim 1, wherein an abnormality of a control signal of the main switch (S1, S2, S3, S4) is detected.   Furthermore, a first filter reactor (Lu) connected between the first and second main switches (S1, S2) and the first phase AC terminal (3u), the third and fourth 6. A second filter reactor (Lw) connected between the main switch (S3, S4) and the third-phase AC terminal (3w). The DC-AC converter according to any one of the above.   Further, first, second, third and fourth main diodes connected in reverse parallel to the first, second, third and fourth main switches (S1, S2, S3, S4). 7. The DC-AC converter according to claim 1, further comprising a parasitic diode (D1, D2, D3, D4).   The auxiliary switch control circuit (6) is turned on from a first time (t1) slightly before a turn-on time (t3) of at least one of the first to fourth main switches (S1 to S4). The function of controlling the first auxiliary switch (Q1) to the off state and controlling the second auxiliary switch (Q2) to the on state until a second time point (t6) slightly after the time point (t3). A first time length (Ta) from the first time point (t1) to the turn-on time point (t3) by the action of the resonance reactor (Lr) until the turn-on time point (t3). 4) and a time length during which the voltage between the second DC terminal (2) and the second DC terminal (2) can be made zero or almost zero, and the time from the turn-on time (t3) to the second time (t6) The time length (Tb) of 2 is the resonance rear A time length that allows the voltage of the first auxiliary switch (Q1) to be zero or almost zero by the second time point (t6) by the action of Torr (Lr) is set. Item 8. The DC-AC converter according to any one of Items 1 to 7.

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