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JP2005222992A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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Publication number
JP2005222992A
JP2005222992A JP2004026587A JP2004026587A JP2005222992A JP 2005222992 A JP2005222992 A JP 2005222992A JP 2004026587 A JP2004026587 A JP 2004026587A JP 2004026587 A JP2004026587 A JP 2004026587A JP 2005222992 A JP2005222992 A JP 2005222992A
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Prior art keywords
semiconductor integrated
integrated circuit
organic substrate
circuit device
ball
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Japanese (ja)
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Kenji Ueda
賢治 植田
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2004026587A priority Critical patent/JP2005222992A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

【課題】半導体集積回路をフリップチップ方式で、インターポーザである有機基板に接続させるタイプのボールグリッドアレイパッケージの半導体集積回路装置における放熱性を向上させる。
【解決手段】インターポーザとしての有機基板２に半導体集積回路１をフリップチップ方式によって接続してなるボールグリッドアレイパッケージにおいて、半導体集積回路１と有機基板２の間に、半導体集積回路１の回路素子形成部と同等、もしくはわずかに小さいサイズのＣｕまたはＡｌからなる金属板５を挟み込むことにより、半導体集積回路１の熱を、金属板５を介して放熱させる。
【選択図】図１An object of the present invention is to improve heat dissipation in a semiconductor integrated circuit device of a ball grid array package of a type in which a semiconductor integrated circuit is connected to an organic substrate as an interposer by a flip chip method.
In a ball grid array package in which a semiconductor integrated circuit 1 is connected to an organic substrate 2 as an interposer by a flip chip method, circuit elements of the semiconductor integrated circuit 1 are formed between the semiconductor integrated circuit 1 and the organic substrate 2. The heat of the semiconductor integrated circuit 1 is dissipated through the metal plate 5 by sandwiching a metal plate 5 made of Cu or Al having a size equal to or slightly smaller than the portion.
[Selection] Figure 1

Description

本発明は、有機基板をインターポーザとして用い、かつ半導体集積回路の電極端子と有機基板とをフリップチップ接続工法にて接続させたボールグリッドアレイパッケージタイプの半導体集積回路装置に関する。   The present invention relates to a ball grid array package type semiconductor integrated circuit device in which an organic substrate is used as an interposer, and an electrode terminal of a semiconductor integrated circuit and an organic substrate are connected by a flip chip connection method.

図３は従来の半導体集積回路装置を示す断面図である。   FIG. 3 is a cross-sectional view showing a conventional semiconductor integrated circuit device.

半導体集積回路１をフリップチップ方式で、インターポーザである有機基板２に接続させるタイプのボールグリッドアレイパッケージでは、半導体集積回路１と有機基板２との導通を得るためにＡｕバンプ３やはんだなどで接続されている。そして、半導体集積回路１と有機基板２との間には、アンダーフィルと呼ばれるエポキシ系の液状封止樹脂４が注入され、その接続信頼性を向上させている。   In a ball grid array package in which the semiconductor integrated circuit 1 is connected to the organic substrate 2 as an interposer by a flip chip method, the semiconductor integrated circuit 1 and the organic substrate 2 are connected by Au bumps 3 or solder in order to obtain electrical continuity. Has been. An epoxy-based liquid sealing resin 4 called underfill is injected between the semiconductor integrated circuit 1 and the organic substrate 2 to improve the connection reliability.

ところで、半導体集積回路１においては放熱対策が重要であり、半導体集積回路１の熱が放熱されなければ、半導体集積回路１の電気的な特性を悪化させるだけでなく、半導体集積回路装置の破壊をも引き起こすこともある。一般的に半導体集積回路１から生じる熱は、フリップチップ方式でのボールグリッドアレイパッケージでは、半導体集積回路１の裏面から大気中に放射される熱と、液状封止樹脂４、有機基板２、はんだボール７へと熱が伝わって放熱されるものがある。   By the way, heat dissipation measures are important in the semiconductor integrated circuit 1. If the heat of the semiconductor integrated circuit 1 is not dissipated, not only the electrical characteristics of the semiconductor integrated circuit 1 are deteriorated but also the semiconductor integrated circuit device is destroyed. Can also cause. Generally, heat generated from the semiconductor integrated circuit 1 is radiated from the back surface of the semiconductor integrated circuit 1 to the atmosphere, liquid sealing resin 4, organic substrate 2, solder in a flip-chip ball grid array package. Some balls are dissipated by transferring heat to the balls 7.

一般的に、このようなフリップチップ接続工法にてインターポーザと接続されたパッケージにおいては、半導体集積回路１の裏面にＣｕやアルミなどで形成された放熱フィンを貼り付けるなどして、放熱性を良くしているものもある。
特開２０００−３１３３０号公報 In general, in a package connected to an interposer by such a flip chip connection method, heat radiation is improved by attaching a heat radiation fin formed of Cu, aluminum or the like to the back surface of the semiconductor integrated circuit 1. Some are doing it.
JP 2000-31330 A

半導体集積回路は、年々、拡散プロセスの微細化が進むことにより、半導体集積回路の素子の密度も高密度化、高速化してきている。それに伴い、半導体集積回路から生じる熱も増加傾向となってきている。その反面、半導体集積回路装置自身は小型化しており、半導体集積回路から生じる熱が放熱されにくくなってきている。この半導体集積回路から生じる熱を放熱しなければ、半導体集積回路の電気特性の変動を導くだけではなく、半導体集積回路装置自身においても、半導体集積回路、アンダーフィル樹脂、有機基板などの熱膨張係数の相違により、半導体集積回路装置自身の破壊という危険性も考えられる。   In semiconductor integrated circuits, the density of elements of semiconductor integrated circuits has been increased and speeded up as the diffusion process has been miniaturized year by year. Along with this, the heat generated from the semiconductor integrated circuit is also increasing. On the other hand, the semiconductor integrated circuit device itself is miniaturized, and heat generated from the semiconductor integrated circuit is hardly radiated. If the heat generated from the semiconductor integrated circuit is not dissipated, not only will the electrical characteristics of the semiconductor integrated circuit fluctuate, but the semiconductor integrated circuit device itself also has a thermal expansion coefficient of the semiconductor integrated circuit, underfill resin, organic substrate, etc. Due to this difference, there is a risk of destruction of the semiconductor integrated circuit device itself.

また、アンダーフィル樹脂としてエポキシ系の樹脂を用いた場合、エポキシ系の樹脂の熱伝導率は、０．３〜０．９Ｗ／ｍ・Ｋと低いため、アンダーフィル樹脂４、有機基板２、はんだボール７を介しての放熱性は良好なものとは言えない。   When an epoxy resin is used as the underfill resin, the thermal conductivity of the epoxy resin is as low as 0.3 to 0.9 W / m · K. Therefore, the underfill resin 4, the organic substrate 2, and the solder It cannot be said that the heat dissipation through the balls 7 is good.

本発明は、このような問題点を解決し、小型でかつ放熱性に優れた半導体集積回路装置を提供することを目的とする。   An object of the present invention is to solve such problems and to provide a semiconductor integrated circuit device that is small in size and excellent in heat dissipation.

前記目的を達成するため、請求項１に係る発明は、インターポーザとしての有機基板に半導体集積回路をフリップチップ方式によって接続してなるボールグリッドアレイパッケージにおいて、前記半導体集積回路と前記有機基板の間に、前記半導体集積回路の回路素子形成部と同等もしくはわずかに小さいサイズでかつ２３０〜４１０Ｗ／ｍ・Ｋの熱伝導率が良好な金属板を挟み込むことを特徴とする。   In order to achieve the above object, an invention according to claim 1 is a ball grid array package in which a semiconductor integrated circuit is connected to an organic substrate as an interposer by a flip chip method, and the semiconductor integrated circuit is interposed between the organic substrate and the organic substrate. A metal plate having a thermal conductivity of 230 to 410 W / m · K that is equal to or slightly smaller than that of the circuit element forming portion of the semiconductor integrated circuit and having a good thermal conductivity is sandwiched.

請求項２に係る発明は、インターポーザとしての有機基板に半導体集積回路をフリップチップ方式によって接続してなるボールグリッドアレイパッケージにおいて、前記半導体集積回路と前記有機基板の間における前記半導体集積回路の回路素子形成部と同等もしくはわずかに小さい範囲に、２３０〜４１０Ｗ／ｍ・Ｋの熱伝導率が良好な金属粒子を混入させた樹脂を挟み込むことを特徴とする。   According to a second aspect of the present invention, there is provided a ball grid array package in which a semiconductor integrated circuit is connected to an organic substrate as an interposer by a flip chip method, and the circuit element of the semiconductor integrated circuit between the semiconductor integrated circuit and the organic substrate. A resin mixed with metal particles having a good thermal conductivity of 230 to 410 W / m · K is sandwiched in a range equivalent to or slightly smaller than the forming portion.

請求項３に係る発明は、請求項１または２に係る発明において、前記金属粒子として、ＣｕまたはＡｌを用いたことを特徴とする。   The invention according to claim 3 is characterized in that, in the invention according to claim 1 or 2, Cu or Al is used as the metal particles.

請求項４に係る発明は、請求項１または２に係る発明において、前記有機基板の裏面に搭載するボールをはんだボールより熱伝導率が良好なボールによって形成したことを特徴とする。   The invention according to claim 4 is characterized in that, in the invention according to claim 1 or 2, the ball mounted on the back surface of the organic substrate is formed of a ball having a thermal conductivity better than that of the solder ball.

請求項５に係る発明は、請求項４に係る発明において、前記有機基板の裏面に搭載するボールをＣｕボールとしたことを特徴とする。   The invention according to claim 5 is characterized in that, in the invention according to claim 4, the ball mounted on the back surface of the organic substrate is a Cu ball.

以上のように本発明の半導体集積回路装置は、半導体集積回路と有機基板の間に、半導体集積回路の回路素子形成部と同等、もしくはわずかに小さいサイズで、Ｃｕ、またはアルミなど２３０〜４１０Ｗ／ｍ・Ｋの熱伝導率が良好な金属板あるいは金属粒子を挟み込むことにより、放熱性を向上させることができる。   As described above, the semiconductor integrated circuit device of the present invention has a size equal to or slightly smaller than that of the circuit element forming portion of the semiconductor integrated circuit between the semiconductor integrated circuit and the organic substrate. Heat dissipation can be improved by sandwiching a metal plate or metal particles having good thermal conductivity of m · K.

以下、本発明の実施の形態について、図１を参照しながら説明する。   Hereinafter, an embodiment of the present invention will be described with reference to FIG.

図１は、半導体集積回路をフリップチップ方式で、インターポーザである有機基板に接続させるタイプの、ボールグリッドアレイパッケージの半導体集積回路装置の概略を示す断面図である。   FIG. 1 is a cross-sectional view schematically showing a semiconductor integrated circuit device of a ball grid array package of a type in which a semiconductor integrated circuit is connected to an organic substrate as an interposer by a flip chip method.

まず、インターポーザである有機基板２の半導体集積回路１を搭載する面（以下、表面と称する。また、反対面を裏面と称する）に、半導体集積回路１の回路素子形成部と同等、もしくはわずかに小さなサイズでかつ熱伝導の良い金属板５を取り付ける。この金属板５は、熱伝導率４０３Ｗ／ｍ・Ｋ（＠０℃）のＣｕ、または熱伝導率２３６Ｗ／ｍ・Ｋ（＠０℃）のアルミが望ましいが、少なくともこの２つの金属を含む熱伝導率の範囲、例えば、２３０〜４１０Ｗ／ｍ・Ｋの範囲の金属であれば適用可能である。   First, the surface on which the semiconductor integrated circuit 1 of the organic substrate 2 that is an interposer is mounted (hereinafter referred to as the front surface, and the opposite surface is referred to as the back surface) is equivalent to or slightly smaller than the circuit element forming portion of the semiconductor integrated circuit 1. A metal plate 5 having a small size and good thermal conductivity is attached. The metal plate 5 is preferably Cu having a thermal conductivity of 403 W / m · K (@ 0 ° C.) or aluminum having a thermal conductivity of 236 W / m · K (@ 0 ° C.). Any metal having a conductivity range, for example, 230 to 410 W / m · K is applicable.

またこの金属板５は半導体集積回路１と有機基板２とをフリップチップ方式で接続させた時の半導体集積回路１と有機基板２との隙間に適合する所望の厚みを有する。なお、金属板５は、Ｃｕめっきなどで所望の厚みまで積み上げて形成する方法でも良い。   The metal plate 5 has a desired thickness that fits into the gap between the semiconductor integrated circuit 1 and the organic substrate 2 when the semiconductor integrated circuit 1 and the organic substrate 2 are connected by a flip chip method. The metal plate 5 may be formed by stacking to a desired thickness by Cu plating or the like.

有機基板２の裏面には、はんだボール７、Ｃｕボール８が形成されており、有機基板２の内部ははんだボール７が有機基板２の表面に実装される半導体集積回路１の端子と電気的に接続されるように構成されている。また、有機基板２においては金属板５を取り付ける部分にはスルーホール６が形成されている。このスルーホール６には良好な熱伝導率を有する部材が充填されており、有機基板２裏側のスルーホール６上にＣｕボール８が形成されており、有機基板２の裏側へ熱を伝わりやすくし、二次実装するマザーボード基板へも熱が伝導されやすいような構造になっている。   Solder balls 7 and Cu balls 8 are formed on the back surface of the organic substrate 2, and the interior of the organic substrate 2 is electrically connected to terminals of the semiconductor integrated circuit 1 on which the solder balls 7 are mounted on the surface of the organic substrate 2. Configured to be connected. In the organic substrate 2, a through hole 6 is formed in a portion where the metal plate 5 is attached. The through-hole 6 is filled with a member having a good thermal conductivity, and Cu balls 8 are formed on the through-hole 6 on the back side of the organic substrate 2 so that heat can be easily transferred to the back side of the organic substrate 2. The structure is such that heat is easily conducted to the mother board to be mounted secondarily.

次に、この熱伝導率の良い金属板５に半導体集積回路１の最も発熱する回路素子形成部を接触させ、フリップチップ方式で有機基板２と半導体集積回路１とを接続させる。このときの接合させる方式は、Ａｕバンプ３での接合や導電性ペースト、はんだ接合など特に方式は問わない。ただし、接続時に圧力や超音波エネルギを用いる場合は、半導体集積回路１の回路素子形成部にポリイミドなどの保護膜を形成して有機基板との接続工程において、半導体集積回路１の回路素子部と金属板５との接触により回路素子が破壊されないようにする。   Next, the most heat-generating circuit element forming portion of the semiconductor integrated circuit 1 is brought into contact with the metal plate 5 having good thermal conductivity, and the organic substrate 2 and the semiconductor integrated circuit 1 are connected by a flip chip method. The bonding method at this time is not particularly limited, such as bonding with Au bumps 3, conductive paste, or solder bonding. However, when pressure or ultrasonic energy is used at the time of connection, a protective film such as polyimide is formed on the circuit element forming portion of the semiconductor integrated circuit 1 and in the step of connecting to the organic substrate, the circuit element portion of the semiconductor integrated circuit 1 The circuit element is prevented from being destroyed by contact with the metal plate 5.

その後、半導体集積回路１と有機基板２との接続箇所の信頼性を向上させるために、接続箇所部に液状封止樹脂４をキャピラリアクションにて塗布し、恒温炉などで液状封止樹脂４を硬化させる。   Thereafter, in order to improve the reliability of the connection portion between the semiconductor integrated circuit 1 and the organic substrate 2, the liquid sealing resin 4 is applied to the connection portion by a capillary action, and the liquid sealing resin 4 is applied in a constant temperature furnace or the like. Harden.

このように構成したことにより、有機基板２の裏側からの放熱性を向上させることが可能になり、小型でかつ信頼性が高い半導体集積回路装置を得ることができる。また、金属板５と接触している有機基板２のスルーホール６に繋がっている裏面のランドに、はんだより熱伝導の良いＣｕボール８を用いることにより、熱をマザーボード基板側に逃がすことが容易となる。   With this configuration, the heat dissipation from the back side of the organic substrate 2 can be improved, and a small and highly reliable semiconductor integrated circuit device can be obtained. In addition, by using Cu balls 8 having better thermal conductivity than solder for the land on the back surface connected to the through hole 6 of the organic substrate 2 that is in contact with the metal plate 5, heat can be easily released to the motherboard substrate side. It becomes.

また、図２のように、熱伝導の良い金属板５の代わりにＣｕやアルミなど、例えば、２３０〜４１０Ｗ／ｍ・Ｋの範囲の熱伝導率の良い金属粒子を混入させた樹脂１１を用いても良い。この場合においても、金属粒子を入れた樹脂１１の供給範囲は、金属板５と同様に、半導体集積回路１の回路素子形成部と同等、もしくはわずかに小さなサイズとする。   Further, as shown in FIG. 2, instead of the metal plate 5 having good heat conductivity, a resin 11 mixed with metal particles having good heat conductivity in the range of 230 to 410 W / m · K, such as Cu or aluminum, is used. May be. Also in this case, the supply range of the resin 11 containing the metal particles is the same as or slightly smaller than the circuit element forming portion of the semiconductor integrated circuit 1, similarly to the metal plate 5.

さらに、Ｃｕボール８には、マザーボード基板への二次実装を容易にするために、はんだめっきがされていることが望ましい。また、本実施形態によればスルーホール６にＣｕボール８を接続したが、それに限らず熱伝導の良い金属であれば適用可能である。   Furthermore, it is desirable that the Cu balls 8 be plated with solder in order to facilitate secondary mounting on the mother board. Further, according to the present embodiment, the Cu ball 8 is connected to the through hole 6, but the present invention is not limited to this, and any metal having good heat conduction is applicable.

本発明は、放熱性を向上させることが可能であるという作用効果を有するようになり、有機基板をインターポーザとして用い、かつ半導体集積回路の電極端子と有機基板とをフリップチップ接続工法にて接続させたボールグリッドアレイパッケージタイプの半導体集積回路装置の分野に利用可能である。   The present invention has an effect that it is possible to improve heat dissipation, uses an organic substrate as an interposer, and connects the electrode terminal of the semiconductor integrated circuit and the organic substrate by a flip chip connection method. The present invention can be used in the field of ball grid array package type semiconductor integrated circuit devices.

本発明の一実施形態の半導体集積回路装置を示す断面図Sectional drawing which shows the semiconductor integrated circuit device of one Embodiment of this invention 本発明の他の実施形態の半導体集積回路装置を示す断面図Sectional drawing which shows the semiconductor integrated circuit device of other embodiment of this invention. 従来の半導体集積回路装置を示す断面図Sectional drawing which shows the conventional semiconductor integrated circuit device

符号の説明Explanation of symbols

１ 半導体集積回路
２ 有機基板
３ Ａｕバンプ
４ 液状封止樹脂
５ 金属板
６ スルーホール
７ はんだボール
８ Ｃｕボール
１１ 樹脂 DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 Organic substrate 3 Au bump 4 Liquid sealing resin 5 Metal plate 6 Through hole 7 Solder ball 8 Cu ball 11 Resin

Claims (5)

インターポーザとしての有機基板に半導体集積回路をフリップチップ方式によって接続してなるボールグリッドアレイパッケージにおいて、前記半導体集積回路と前記有機基板の間に、前記半導体集積回路の回路素子形成部と同等もしくはわずかに小さいサイズでかつ２３０〜４１０Ｗ／ｍ・Ｋの熱伝導率が良好な金属板を挟み込むことを特徴とする半導体集積回路装置。   In a ball grid array package in which a semiconductor integrated circuit is connected to an organic substrate as an interposer by a flip chip method, a circuit element forming portion of the semiconductor integrated circuit is equivalent to or slightly between the semiconductor integrated circuit and the organic substrate. A semiconductor integrated circuit device characterized by sandwiching a metal plate having a small size and good thermal conductivity of 230 to 410 W / m · K. インターポーザとしての有機基板に半導体集積回路をフリップチップ方式によって接続してなるボールグリッドアレイパッケージにおいて、前記半導体集積回路と前記有機基板の間における前記半導体集積回路の回路素子形成部と同等もしくはわずかに小さい範囲に、２３０〜４１０Ｗ／ｍ・Ｋの熱伝導率が良好な金属粒子を混入させた樹脂を挟み込むことを特徴とする半導体集積回路装置。   In a ball grid array package in which a semiconductor integrated circuit is connected to an organic substrate as an interposer by a flip chip method, it is equal to or slightly smaller than a circuit element forming portion of the semiconductor integrated circuit between the semiconductor integrated circuit and the organic substrate. A semiconductor integrated circuit device characterized by sandwiching a resin mixed with metal particles having good thermal conductivity of 230 to 410 W / m · K in a range. 前記金属粒子として、ＣｕまたはＡｌを用いたことを特徴とする請求項１または２記載の半導体集積回路装置。   3. The semiconductor integrated circuit device according to claim 1, wherein Cu or Al is used as the metal particles. 前記有機基板の裏面に搭載するボールをはんだボールより熱伝導率が良好なボールによって形成したことを特徴とする請求項１または２記載の半導体集積回路装置。   3. The semiconductor integrated circuit device according to claim 1, wherein the ball mounted on the back surface of the organic substrate is formed of a ball having a thermal conductivity better than that of the solder ball. 前記有機基板の裏面に搭載するボールをＣｕボールとしたことを特徴とする請求項４記載の半導体集積回路装置。   5. The semiconductor integrated circuit device according to claim 4, wherein a ball mounted on the back surface of the organic substrate is a Cu ball.
JP2004026587A 2004-02-03 2004-02-03 Semiconductor integrated circuit device Pending JP2005222992A (en)

Priority Applications (1)

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JP2004026587A JP2005222992A (en) 2004-02-03 2004-02-03 Semiconductor integrated circuit device

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Application Number Priority Date Filing Date Title
JP2004026587A JP2005222992A (en) 2004-02-03 2004-02-03 Semiconductor integrated circuit device

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