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JP2005228929A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2005228929A
JP2005228929A JP2004036441A JP2004036441A JP2005228929A JP 2005228929 A JP2005228929 A JP 2005228929A JP 2004036441 A JP2004036441 A JP 2004036441A JP 2004036441 A JP2004036441 A JP 2004036441A JP 2005228929 A JP2005228929 A JP 2005228929A
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metal body
semiconductor element
region
semiconductor
bonding material
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JP3823974B2 (en
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Tetsuji Kondo
徹次 近藤
Yoshimi Nakase
好美 中瀬
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Denso Corp
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can suppress the occurrence of the malfunction of a semiconductor element caused by the free movement of a third metallic body at the time of performing the final joining and can be suppressed in the fall of its service life, and to provide a method of manufacturing the device. <P>SOLUTION: In the semiconductor device, the third metallic body 6 having not only a first region 11 facing semiconductor elements 1a and 1b, but also a second region 12 not facing the elements 1a and 1b is used. Then a first metallic body 3, a first bonding material 8, the semiconductor elements 1, a second bonding material 9, the third metallic body 6, a third bonding material 10, and a second metallic body 5 are set in a laminated state. At this time, a first holding jig (spacer) 21 is arranged between the first and third metallic bodies 3 and 6 so as to hold the second region 12 of the third metallic body 6. Then the metallic bodies 3, 6, and 5 and bonding materials 8, 9, and 10 are finally joined to each other by heating the bodies 3, 6, and 5 and materials 8, 9, and 10, and applying a pressure to the bodies 3, 6, and 5 and materials 8, 9, and 10 in a state where the first holding jig (spacer) 21 is arranged. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体素子の両側を一対の金属体で挟んでなり、装置のほぼ全体が樹脂でモールドされてなる半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device in which both sides of a semiconductor element are sandwiched between a pair of metal bodies, and almost the entire device is molded with resin, and a method for manufacturing the same.

図１３に従来における半導体装置の一例を示す。図１３では、半導体装置の側面を透過して見たときにおける半導体装置の内部構造を示している。図１３に示すように、従来より、半導体素子１と、半導体素子１の裏面２側に設けられ電極と放熱体とを兼ねる第１の金属体３と、半導体素子１の表面４側に設けられ電極と放熱体とを兼ねる第２の金属体５と、半導体素子１の表面４と第２の金属体５との間に設けられた第３の金属体６と、半導体素子１、第１の金属体３および第２の金属体５を包み込むように封止するモールド樹脂７とを備えた半導体装置が提案されている（例えば、特許文献１参照）。   FIG. 13 shows an example of a conventional semiconductor device. FIG. 13 shows the internal structure of the semiconductor device as seen through the side surface of the semiconductor device. As shown in FIG. 13, conventionally, the semiconductor element 1, the first metal body 3 that is provided on the back surface 2 side of the semiconductor element 1 and serves as an electrode and a radiator, and the front surface 4 side of the semiconductor element 1 are provided. A second metal body 5 that also serves as an electrode and a radiator, a third metal body 6 provided between the surface 4 of the semiconductor element 1 and the second metal body 5, the semiconductor element 1, and the first There has been proposed a semiconductor device including a mold resin 7 that seals the metal body 3 and the second metal body 5 (see, for example, Patent Document 1).

なお、図中の半導体装置は、２つの半導体素子１ａ、１ｂと２つの第３の金属体６ａ、６ｂとを有している。   The semiconductor device in the figure has two semiconductor elements 1a and 1b and two third metal bodies 6a and 6b.

第１の金属体３と半導体素子１は第１の接合材８により接合され、半導体素子１と第３の金属体６は第２の接合材９により接合され、第３の金属体６と第２の金属体５は第３の接合材１０により接合されている。また、第１〜第３の接合材８〜１０としては、例えば、半田が用いられている。   The first metal body 3 and the semiconductor element 1 are bonded by the first bonding material 8, the semiconductor element 1 and the third metal body 6 are bonded by the second bonding material 9, and the third metal body 6 and the first metal material 6 are bonded. The second metal body 5 is joined by a third joining material 10. In addition, as the first to third bonding materials 8 to 10, for example, solder is used.

半導体素子１は、図示しないが、表面４の周辺部にボンディングパッドが設けられており、表面４の中央部に、ボンディングパッドとは異なる電極である主電極が設けられている。そして、ボンディングパッドは、図示しない端子とワイヤボンディングされ、主電極は、第３の金属体６を介して、第２の金属体５と電気的に接続されている。   Although not shown, the semiconductor element 1 is provided with a bonding pad at the periphery of the surface 4, and a main electrode which is an electrode different from the bonding pad is provided at the center of the surface 4. The bonding pad is wire-bonded to a terminal (not shown), and the main electrode is electrically connected to the second metal body 5 via the third metal body 6.

第３の金属体６は、主電極と第２の金属体５とを電気的に導通させ、半導体素子１で発生した熱を第２の金属体５に放熱させるためのものである。このため、第３の金属体６は、一般に、半導体素子１の表面４に対して垂直な方向から見たときの大きさが、半導体素子１の主電極と同等もしくはそれよりも小さい。   The third metal body 6 is for electrically connecting the main electrode and the second metal body 5 to dissipate heat generated in the semiconductor element 1 to the second metal body 5. For this reason, the size of the third metal body 6 is generally equal to or smaller than that of the main electrode of the semiconductor element 1 when viewed from a direction perpendicular to the surface 4 of the semiconductor element 1.

また、半導体素子１の表面４に配置された第２の接合材９も、主電極からはみ出さないように、半導体素子１の表面４に対して垂直な方向から見たときの大きさが、半導体素子１の主電極と同等もしくはそれよりも小さくなっている。
特開２００１−１５６２２５号公報 Further, the second bonding material 9 disposed on the surface 4 of the semiconductor element 1 also has a size when viewed from a direction perpendicular to the surface 4 of the semiconductor element 1 so as not to protrude from the main electrode. It is equal to or smaller than the main electrode of the semiconductor element 1.
JP 2001-156225 A

上記した構造の半導体装置は、例えば、以下の方法により製造される。   The semiconductor device having the above-described structure is manufactured by, for example, the following method.

まず、第１の金属体３と半導体素子１と第３の金属体６とを接合する工程を行う。すなわち、第１の金属体３の上に、半田箔（第１の接合材８）と、半導体素子１と、半田箔（第２の接合材９）と、第３の金属体６とを積層する（図１３参照）。その後、加熱装置（リフロー装置）によって、上記半田箔を溶融させることで、第１の金属体３と半導体素子１、半導体素子１と第３の金属体６を接合する。   First, a step of bonding the first metal body 3, the semiconductor element 1, and the third metal body 6 is performed. That is, a solder foil (first bonding material 8), a semiconductor element 1, a solder foil (second bonding material 9), and a third metal body 6 are laminated on the first metal body 3. (See FIG. 13). Then, the first metal body 3 and the semiconductor element 1 and the semiconductor element 1 and the third metal body 6 are joined by melting the solder foil by a heating device (reflow device).

そして、半導体素子１の図示しないボンディングパッドと端子とをワイヤボンディングする工程を行う。   Then, a step of wire bonding a bonding pad (not shown) and a terminal of the semiconductor element 1 is performed.

次に、第３の金属体６に第２の金属体５を積層する工程を行う。すなわち、第３の金属体６の上に、半田箔（第３の接合材１０）と、第２の金属体５とを積層する。また、第１の金属体３と第２の金属体５との間であって、半導体素子１および第３の金属体６が配置されていない領域に保持治具（スペーサ）を配置する。   Next, a step of laminating the second metal body 5 on the third metal body 6 is performed. That is, the solder foil (third bonding material 10) and the second metal body 5 are laminated on the third metal body 6. Further, a holding jig (spacer) is disposed in a region between the first metal body 3 and the second metal body 5 where the semiconductor element 1 and the third metal body 6 are not disposed.

その後、第３の金属体６と第２の金属体５を接合する工程（最終的な全体の接合をする工程）を行う。すなわち、積層された第１の金属体３、半導体素子１、第３の金属体６、第２の金属体５を、加熱装置（リフロー装置）で加熱することで、全体の温度を半田の融点以上の温度とし、上記半田箔を溶融させる。このとき、第１の金属体３と第２の金属体５を押し合わせるように、第１の金属体３と第２の金属体５に対して、応力を加える。   Thereafter, a step of joining the third metal body 6 and the second metal body 5 (final overall joining step) is performed. That is, by heating the laminated first metal body 3, semiconductor element 1, third metal body 6, and second metal body 5 with a heating device (reflow device), the overall temperature is reduced to the melting point of the solder. The solder foil is melted at the above temperature. At this time, stress is applied to the first metal body 3 and the second metal body 5 so as to press the first metal body 3 and the second metal body 5 together.

そして、全体の温度を半田の融点以下の温度とすることで、第１の金属体３、半導体素子１、第３の金属体６、第２の金属体５を接合する。その後、スペーサを取り外す。   And the 1st metal body 3, the semiconductor element 1, the 3rd metal body 6, and the 2nd metal body 5 are joined by making the whole temperature into the temperature below melting | fusing point of solder. Thereafter, the spacer is removed.

続いて、接合された第１の金属体３、半導体素子１、第３の金属体６、第２の金属体５をモールド樹脂７により封止する工程を行う。以上の方法により、上記した構造の半導体装置が製造される。   Then, the process of sealing the joined 1st metal body 3, the semiconductor element 1, the 3rd metal body 6, and the 2nd metal body 5 with the mold resin 7 is performed. With the above method, the semiconductor device having the above-described structure is manufactured.

しかし、上記した製造方法では、半導体素子１の表面４に配置された半田９が、半導体素子１の主電極からはみ出ることで、半導体素子１の表面４と裏面２が短絡し、半導体素子１が動作不良となる場合が生じるという問題がある。また、上記した方法により製造された半導体装置では、製品寿命が短いものが存在するという問題がある。   However, in the manufacturing method described above, the solder 9 disposed on the front surface 4 of the semiconductor element 1 protrudes from the main electrode of the semiconductor element 1, so that the front surface 4 and the back surface 2 of the semiconductor element 1 are short-circuited. There is a problem that an operation failure may occur. In addition, there is a problem that some semiconductor devices manufactured by the above method have a short product life.

そこで、本発明者らがこれらの問題を解決するために、原因を検討したところ、以下のことが原因であると推測される。   Then, when the present inventors examined the cause in order to solve these problems, it is estimated that the following is the cause.

第３の金属体６の上に、半田箔と、第２の金属体５とを積層して、半田箔を溶融させることで、最終的に、第１の金属体３、半導体素子１、第３の金属体６、第２の金属体５を接合する工程では、第１の金属体３と第２の金属体５との間に、スペーサを配置した状態で、それらを接合している。このため、第１の金属体３と第２の金属体５との間隔は、設定の大きさとなる。   By laminating the solder foil and the second metal body 5 on the third metal body 6 and melting the solder foil, the first metal body 3, the semiconductor element 1, the first In the step of joining the third metal body 6 and the second metal body 5, they are joined together with a spacer disposed between the first metal body 3 and the second metal body 5. For this reason, the distance between the first metal body 3 and the second metal body 5 is a set size.

しかし、第１の金属体３と第３の金属体６との間には、このようなスペーサが配置されていないため、第３の金属体６が自由に動いてしまう。すなわち、第３の金属体６が第１、第２の金属体５に対して垂直な方向に移動したり、第３の金属体６が第１の金属体３に対して傾いたりしてしまう。   However, since such a spacer is not disposed between the first metal body 3 and the third metal body 6, the third metal body 6 moves freely. That is, the third metal body 6 moves in a direction perpendicular to the first and second metal bodies 5, or the third metal body 6 is inclined with respect to the first metal body 3. .

ここで、図１４に接合時に第３の金属体６が動いた場合の第１の金属体３と第２の金属体５との間の様子を示す。   Here, FIG. 14 shows a state between the first metal body 3 and the second metal body 5 when the third metal body 6 moves during bonding.

図１４の右側に示すように、第３の金属体６が第１の金属体３側に移動した場合、第３の金属体６と第１の金属体３との間隔３１が、図１３に示される設定間隔３２よりも小さくなる。この場合、半導体素子１と第３の金属体６との間の半田（第２の接合材）９が半導体素子１の主電極からはみ出す。そして、このはみ出した半田９がボンディングパッドまで到達すると、主電極とボンディングパッドとの間が短絡したり、隣り合うボンディングパッド同士間が短絡したりしてしまう。さらに、はみ出した半田が第１の金属体３まで到達すると、半導体素子１の表面４と裏面２とが短絡してしまう。このため、半導体素子１が動作不良となってしまう。   As shown on the right side of FIG. 14, when the third metal body 6 moves to the first metal body 3 side, an interval 31 between the third metal body 6 and the first metal body 3 is shown in FIG. It becomes smaller than the set interval 32 shown. In this case, the solder (second bonding material) 9 between the semiconductor element 1 and the third metal body 6 protrudes from the main electrode of the semiconductor element 1. When the protruding solder 9 reaches the bonding pad, the main electrode and the bonding pad are short-circuited or adjacent bonding pads are short-circuited. Further, when the protruding solder reaches the first metal body 3, the front surface 4 and the back surface 2 of the semiconductor element 1 are short-circuited. For this reason, the semiconductor element 1 will malfunction.

また、図１４の左側に示すように、第３の金属体６が第１の金属体３に対して、角度θ１で傾いた場合、第３の金属体６の傾きθ１が半導体素子１の第１の金属体３に対する傾きθ２と異なっていると、半田（第２の接合材）９の一端側の厚さ３３が、設定厚さ３２よりも薄くなり、他端側の厚さ３４が設定厚さ３２よりも厚くなってしまう。すなわち、半田（第２の接合材）９の一端側の厚さ３３と、他端側の厚さ３４とに差が生じてしまう。 Further, as shown on the left side of FIG. 14, when the third metal body 6 is inclined with respect to the first metal body 3 at an angle θ 1 , the inclination θ 1 of the third metal body 6 is If it is different from the inclination θ 2 with respect to the first metal body 3, the thickness 33 on one end side of the solder (second bonding material) 9 becomes thinner than the set thickness 32 and the thickness 34 on the other end side. Becomes thicker than the set thickness 32. That is, there is a difference between the thickness 33 on one end side of the solder (second bonding material) 9 and the thickness 34 on the other end side.

ここで、一般に、半田は応力緩和層としての機能を有すると考えられている。このため、半田が薄い部分では、半田の量が少なく、例えば、第３の金属体６と半導体素子１との間での熱膨張係数の差によって生じる応力が緩和され難く、応力が集中すると推測される。   Here, it is generally considered that solder has a function as a stress relaxation layer. For this reason, in the portion where the solder is thin, the amount of solder is small. For example, the stress caused by the difference in the thermal expansion coefficient between the third metal body 6 and the semiconductor element 1 is not easily relieved, and it is assumed that the stress is concentrated. Is done.

したがって、図１４の左側に示すように、半田（第２の接合材）９の一端側の薄い部分では、他端側の厚い部分と比較して、半導体素子１の主電極（積層）の中、主電極と半田との接合面、もしくは半田の中にクラックが発生しやすく、クラックの進行が加速しやすい。また、半導体素子１の主電極内や、主電極と半田との間で剥離が生じやすく、剥離の進行が加速しやすい。   Therefore, as shown on the left side of FIG. 14, in the thin part on one end side of the solder (second bonding material) 9, compared to the thick part on the other end side, in the main electrode (lamination) of the semiconductor element 1. Cracks are likely to occur in the joint surface of the main electrode and the solder or in the solder, and the progress of the cracks is likely to be accelerated. Further, peeling is likely to occur in the main electrode of the semiconductor element 1 or between the main electrode and the solder, and the progress of peeling is likely to be accelerated.

なお、図１４の右側に示すように、第３の金属体６が第１の金属体３側に移動し、第３の金属体６と第１の金属体３との間隔が設定間隔よりも小さくなって、半田（第２の接合材）９の全体が薄くなった場合においても、同様である。   As shown on the right side of FIG. 14, the third metal body 6 moves to the first metal body 3 side, and the distance between the third metal body 6 and the first metal body 3 is larger than the set interval. The same applies to the case where the entire solder (second bonding material) 9 is thinned as it becomes smaller.

このため、半田（第２の接合材）９が、全体もしくは一部で、設定の厚さ３２よりも薄くなってしまった場合では、半導体装置の寿命が短くなってしまう。   For this reason, when the solder (second bonding material) 9 is entirely or partially thinner than the set thickness 32, the life of the semiconductor device is shortened.

本発明は、上記点に鑑み、最終的な接合時に第３の金属体６が自由に動くことに起因する半導体素子１の動作不良の発生と、半導体装置の寿命の低下を抑制することができる半導体装置およびその製造方法を提供することを目的とする。   In view of the above points, the present invention can suppress the occurrence of malfunction of the semiconductor element 1 due to the free movement of the third metal body 6 at the time of final bonding and the reduction of the lifetime of the semiconductor device. An object of the present invention is to provide a semiconductor device and a manufacturing method thereof.

上記目的を達成するため、請求項１に記載の発明では、第１の金属体（３）、第１の接合材（８）、半導体素子（１）、第２の接合材（９）、第３の金属体（６）、第３の接合材（１０）および第２の金属体（５）を用意する工程と、第１の金属体（３）、第１の接合材（８）、半導体素子（１）、第２の接合材（９）、第３の金属体（６）、第３の接合材（１０）および第２の金属体（５）を順に積層した状態とし、かつ、第１の金属体（３）と第２の金属体（５）との間であって、半導体素子（１）が配置された領域を除く領域に、第１の金属体（３）と第３の金属体（６）とを保持する保持治具（２１）を配置する工程とを有し、第３の金属体（６）を用意する工程では、半導体素子（１）と接合される接合予定領域と異なる領域に、保持治具（２１）によって保持される被保持部（１２、１２ａ、１４）を備える第３の金属体（６）を用意することを特徴としている。   In order to achieve the above object, according to the first aspect of the present invention, the first metal body (3), the first bonding material (8), the semiconductor element (1), the second bonding material (9), 3 metal body (6), third bonding material (10) and second metal body (5), first metal body (3), first bonding material (8), semiconductor The element (1), the second bonding material (9), the third metal body (6), the third bonding material (10), and the second metal body (5) are sequentially stacked, and the first Between the first metal body (3) and the second metal body (5), except in the region where the semiconductor element (1) is disposed, the first metal body (3) and the third metal body (3) And a step of disposing a holding jig (21) for holding the metal body (6), and in the step of preparing the third metal body (6), a bonding scheduled region to be bonded to the semiconductor element (1) And in a different area, The held portion is held by Jichigu (21) (12, 12a, 14) is characterized by providing a third metal body comprising (6).

本発明によれば、第１の金属体、半導体素子、第３の金属体、第２の金属体の最終的な接合時において、第３の金属体が自由に動くのを抑制することができる。そして、第３の金属体と第１の金属体との間隔が所定の大きさとなるように、かつ、これらの対向する面同士が平行となるように、保持治具を配置することで、第１の金属体と第３の金属体とを平行に保ち、第１の金属体と第３の金属体との間隔を所定の大きさに保つことができる。   According to the present invention, it is possible to prevent the third metal body from freely moving during the final joining of the first metal body, the semiconductor element, the third metal body, and the second metal body. . Then, by arranging the holding jig so that the distance between the third metal body and the first metal body is a predetermined size and the opposing surfaces are parallel to each other, The first metal body and the third metal body can be kept in parallel, and the distance between the first metal body and the third metal body can be kept at a predetermined size.

これにより、この保持治具を用いない半導体装置の製造方法と比較して、最終的な接合時に第３の金属体が自由に動くことに起因する半導体素子の動作不良の発生と、半導体装置の寿命の低下を抑制することができる。   As a result, compared with the method of manufacturing a semiconductor device that does not use this holding jig, the occurrence of malfunction of the semiconductor element due to the third metal body freely moving at the time of final bonding, It is possible to suppress a decrease in life.

第３の金属体としては、例えば、請求項２に示すように、半導体素子（１）と接合される接合予定領域（１１）と異なる領域に、接合予定領域（１１）よりも薄い部分（１２）を備える第３の金属体（６）を用いることができる。なお、ここでいう薄いとは、第３の金属体の半導体素子と接合する面に対して垂直な方向での厚さが薄いことをいう。   As the third metal body, for example, as shown in claim 2, a portion (12) thinner than the planned joining region (11) in a region different from the planned joining region (11) joined to the semiconductor element (1). ) Can be used. Here, the term “thin” means that the thickness in the direction perpendicular to the surface of the third metal body that is bonded to the semiconductor element is small.

請求項２の発明において、例えば、第３の金属体の外周部に、半導体素子と接合される領域よりも薄い鍔形状の部分が設けられており、その鍔形状の部分の第２の金属側の面が、第３の金属体の半導体素子と接合される領域における第２の金属体と接合する面と、一致している第３の金属体を用いることができる。言い換えると、半導体素子と接合される接合予定領域と、その領域の外周に配置された半導体素子と接合されない領域とを有し、半導体素子と接合される領域のみが、半導体素子側に向かって突出している形状である第３の金属体を用いることができる。   In the invention of claim 2, for example, an outer peripheral portion of the third metal body is provided with a hook-shaped portion thinner than a region bonded to the semiconductor element, and the second metal side of the hook-shaped portion. It is possible to use a third metal body whose surface coincides with a surface to be joined to the second metal body in a region joined to the semiconductor element of the third metal body. In other words, a region to be bonded to the semiconductor element has a region to be bonded and a region not bonded to the semiconductor element arranged on the outer periphery of the region, and only the region bonded to the semiconductor element protrudes toward the semiconductor element side. A third metal body having a shape can be used.

最終的な接合をする工程で加熱をした際に、第２の接合材（例えば、半田）が、他の接合材よりも先に溶融された場合、第１の金属体と第２の金属体とに加えられる応力によって、半導体素子の上に配置された第２の接合材が、半導体素子から外側にはみ出すおそれがある。第２の接合材がはみ出して、第１の金属体まで到達すると、半導体素子の表裏面等が短絡してしまう。   When the second bonding material (for example, solder) is melted before other bonding materials when heated in the final bonding step, the first metal body and the second metal body The second bonding material disposed on the semiconductor element may protrude outward from the semiconductor element due to the stress applied to the semiconductor element. When the second bonding material protrudes and reaches the first metal body, the front and back surfaces of the semiconductor element and the like are short-circuited.

そこで、上記したような鍔形状部を有する第３の金属体を用いることで、第２の接合材がはみ出すようなことがあっても、第２の接合材は、第３の金属体における半導体素子との接続面に隣接する側面と、鍔形状部とに沿って流れ、その側面と鍔形状部に留められる（付着する）。このため、半導体素子の表裏面等の短絡を防止することができる。   Therefore, by using the third metal body having the hook-shaped portion as described above, the second bonding material is a semiconductor in the third metal body even if the second bonding material protrudes. It flows along the side surface adjacent to the connection surface with the element and the hook-shaped portion, and is fastened (attached) to the side surface and the hook-shaped portion. For this reason, it is possible to prevent a short circuit on the front and back surfaces of the semiconductor element.

第３の金属体としては、例えば、請求項３に示すように、半導体素子（１）と接合される接合予定領域（１１）の外周部の一部に、接合予定領域（１１）よりも薄い部分（１２ａ）を備える第３の金属体（６）を用いることもできる。つまり、薄い部分が、第３の金属体の外周部全域ではなく、外周部のうち、保持治具による保持が必要な部位にだけ設けられた第３の金属体を用いることもできる。   As the third metal body, for example, as shown in claim 3, a part of the outer periphery of the planned joining region (11) joined to the semiconductor element (1) is thinner than the planned joining region (11). A third metal body (6) having a portion (12a) can also be used. That is, the third metal body provided with a thin portion only in a portion of the outer peripheral portion that needs to be held by the holding jig can be used instead of the entire outer peripheral portion of the third metal body.

また、請求項４に示すように、第３の金属体（６）として、半導体素子（１）と接合される面（６ｃ）に隣接する側面（６ｅ）と、側面（６ｅ）に設けられた凹部（１４）とを備える第３の金属体（６）を用い、第３の金属体（６）の凹部（１４）を、保持治具（２１）で保持させることもできる。   Moreover, as shown in Claim 4, it provided in the side surface (6e) adjacent to the surface (6c) joined to a semiconductor element (1) as a 3rd metal body (6), and the side surface (6e). The third metal body (6) provided with the recess (14) can be used to hold the recess (14) of the third metal body (6) with the holding jig (21).

また、請求項５に示すように、１つの第１の金属体（３）と１つの第３の金属体（６）との間に複数の半導体素子（１ａ、１ｂ）を配置させることもできる。すなわち、１つの第３の金属体を、複数の半導体素子と接合させることもできる。   Further, as shown in claim 5, a plurality of semiconductor elements (1a, 1b) can be arranged between one first metal body (3) and one third metal body (6). . That is, one third metal body can be bonded to a plurality of semiconductor elements.

請求項６に記載の発明では、第３の金属体（６）は、第３の金属体（６）を半導体素子（１）の表面（４）に対して略垂直な方向から見たときに、半導体素子（１）と対向している第１の領域（１１）と、半導体素子（１）からはみ出ている第２の領域（１２）とを有することを特徴としている。   In the invention described in claim 6, the third metal body (6) is obtained when the third metal body (6) is viewed from a direction substantially perpendicular to the surface (4) of the semiconductor element (1). The semiconductor device has a first region (11) facing the semiconductor element (1) and a second region (12) protruding from the semiconductor element (1).

また、請求項９に記載の発明では、第３の金属体（６）は、第２の金属体（５）と接合される面（６ｄ）に隣接する側面（６ｅ）と、側面（６ｅ）に設けられた凹部（１４）とを有することを特徴としている。   In the invention according to claim 9, the third metal body (6) includes a side surface (6e) adjacent to a surface (6d) to be joined to the second metal body (5), and a side surface (6e). It has the recessed part (14) provided in this, It is characterized by the above-mentioned.

第３の金属体をこのような形状とすることで、第２の領域（１２）や、側面の凹部（１４）を、請求項１に記載の製造方法における被保持部として、請求項１に記載の製造方法を実現することができる。   By making the third metal body into such a shape, the second region (12) and the concave portion (14) on the side surface can be used as a held portion in the manufacturing method according to claim 1. The described manufacturing method can be realized.

第３の金属体としては、例えば、請求項７に示すように、第３の金属体（６）における第２の領域（１２）の厚さが、第１の領域（１１）の厚さよりも薄いものを用いることができる。   As the third metal body, for example, as shown in claim 7, the thickness of the second region (12) in the third metal body (6) is larger than the thickness of the first region (11). A thin one can be used.

また、請求項８に示すように、第２の領域（１２）が第３の金属体（６）の外周の一部に設けられている第３の金属体を用いることもできる。   Moreover, as shown in Claim 8, the 3rd metal body in which the 2nd area | region (12) is provided in a part of outer periphery of the 3rd metal body (6) can also be used.

また、請求項１０に示すように、１つの第１の金属体（３）と１つの第３の金属体（６）との間に複数の半導体素子（１ａ、１ｂ）を配置することもできる。   Further, as shown in claim 10, a plurality of semiconductor elements (1a, 1b) can be arranged between one first metal body (3) and one third metal body (6). .

なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示す一例である。   In addition, the code | symbol in the bracket | parenthesis of each said means is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

（第１実施形態）
図１に、本発明の第１実施形態における半導体装置を側面方向から内部を透過して見たときの内部構成を示す。また、図２に、図１の半導体装置を矢印方向で見たときの図を示す。図２では、第２の金属体５、第３の接合材１０、モールド樹脂７を省略している。なお、図１は、半導体装置を図２中の矢印方向から見たときの図である。 (First embodiment)
FIG. 1 shows an internal configuration when the semiconductor device according to the first embodiment of the present invention is viewed from the side direction through the inside. FIG. 2 shows a view of the semiconductor device of FIG. 1 as viewed in the direction of the arrow. In FIG. 2, the second metal body 5, the third bonding material 10, and the mold resin 7 are omitted. FIG. 1 is a diagram of the semiconductor device as viewed from the direction of the arrow in FIG.

本実施形態の半導体装置は、第３の金属体６の形状が、図１３に示した従来の半導体装置と異なるものであり、他の構造部は、図１３の半導体装置と同じである。したがって、図１、２において、図１３中の構造部と同様の構造部に、図１３中の構造部と同一の符号を付すことで、以下では、図１３中の構造部と同様の構造部についての詳細な説明を省略する。   In the semiconductor device of this embodiment, the shape of the third metal body 6 is different from that of the conventional semiconductor device shown in FIG. 13, and the other structural portions are the same as those of the semiconductor device of FIG. Accordingly, in FIGS. 1 and 2, the same structural parts as those in FIG. 13 are denoted by the same reference numerals as those in FIG. The detailed description about is omitted.

この半導体装置は、図１、２に示すように、２つの半導体素子１を備えている。半導体素子１は、板状であり、その主表面の形状は、例えば、略四角形形状（図２では、正方形）であり、２つの半導体素子１のうち、一方の半導体素子１ａは、他方の半導体素子１ｂよりもチップ面積が大きくなっている。半導体素子１は、例えば、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）やサイリスタ等のパワー半導体素子である。   The semiconductor device includes two semiconductor elements 1 as shown in FIGS. The semiconductor element 1 is plate-shaped, and the shape of the main surface thereof is, for example, a substantially square shape (square in FIG. 2), and one of the two semiconductor elements 1 is the semiconductor element 1a. The chip area is larger than that of the element 1b. The semiconductor element 1 is a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) or a thyristor, for example.

第３の金属体６は、図１、２に示すように、板状であり、その主表面の形状は略四角形（図２では、長方形）である。第３の金属体６は、図１、２に示すように、２つの半導体素子１ａ、１ｂを跨ぐ構造となっている。本実施形態では、第３の金属体６は１つであり、１つの第３の金属体６によって、２つの半導体素子１ａ、１ｂが覆われている。   As shown in FIGS. 1 and 2, the third metal body 6 has a plate shape, and its main surface has a substantially quadrangular shape (a rectangle in FIG. 2). As shown in FIGS. 1 and 2, the third metal body 6 has a structure straddling two semiconductor elements 1 a and 1 b. In the present embodiment, there is one third metal body 6, and the two semiconductor elements 1 a and 1 b are covered by one third metal body 6.

また、第３の金属体６は、２つの半導体素子１ａ、１ｂと対向している第１の領域１１と、２つの半導体素子１ａ、１ｂと対向していない第２の領域１２とを有している。この第２の領域１２は、第３の金属体６の半導体素子１に対向する面６ｃに対して垂直な方向から半導体素子１と第３の金属体３とを見たとき、半導体素子１と対向しておらず、半導体素子１からはみ出ている領域である。なお、この第２の領域１２が本発明の被保持部に相当する。   The third metal body 6 includes a first region 11 that faces the two semiconductor elements 1a and 1b, and a second region 12 that does not face the two semiconductor elements 1a and 1b. ing. The second region 12 is formed when the semiconductor element 1 and the third metal body 3 are viewed from a direction perpendicular to the surface 6c of the third metal body 6 facing the semiconductor element 1. This is a region that is not opposed and protrudes from the semiconductor element 1. The second region 12 corresponds to the held portion of the present invention.

また、第３の金属体６は、半導体素子１に対向する面６ｃのうち、図１に示すように、２つの半導体素子１ａ、１ｂと接合されている領域が、半導体素子１に向かって突出している。   Further, in the third metal body 6, a region of the surface 6 c facing the semiconductor element 1 that is joined to the two semiconductor elements 1 a and 1 b protrudes toward the semiconductor element 1 as shown in FIG. 1. ing.

言い換えると、第１の金属体３は、半導体素子１と第２の接合材９を介して接合されている第１の領域（図２中で破線が斜めに引かれている領域）１１と、第１の領域１１を除く、半導体素子１と接合されていない第２の領域（図２中で実線のみ斜めに引かれている領域）１２とを有しており、第２の領域１２は、第１の領域１１よりも薄くなっている。なお、この薄いとは、半導体素子１の裏面２や表面４に対して垂直な方向（図１中の上下方向）において薄いことをいう。   In other words, the first metal body 3 includes a first region (region in which a broken line is drawn obliquely in FIG. 2) 11 bonded to the semiconductor element 1 via the second bonding material 9, 2 has a second region 12 that is not joined to the semiconductor element 1 except for the first region 11 (a region that is drawn obliquely only in the solid line in FIG. 2). It is thinner than the first region 11. In addition, this thin means that it is thin in the direction (vertical direction in FIG. 1) perpendicular to the back surface 2 and the front surface 4 of the semiconductor element 1.

第３の金属体６の第１の領域１１における半導体素子１に対向する面６ｃは、第２の接合材９を介して、半導体素子１ａや、半導体素子１ｂと接合されている。また、第３の金属体６の第２の金属体５に対向する面６ｄの全ては、第３の接合材１０を介して、第２の金属体５と接合されている。   A surface 6 c of the third metal body 6 facing the semiconductor element 1 in the first region 11 is bonded to the semiconductor element 1 a and the semiconductor element 1 b through the second bonding material 9. Further, the entire surface 6 d of the third metal body 6 facing the second metal body 5 is joined to the second metal body 5 via the third joining material 10.

なお、第３の金属体６は、一般的な材料により構成されており、例えば、金メッキが施された銅により構成されている。また、第１の金属体３、第２の金属体５も、一般的な材料により構成されている。   In addition, the 3rd metal body 6 is comprised with the general material, for example, is comprised with the copper by which gold plating was given. The first metal body 3 and the second metal body 5 are also made of a general material.

次に、以上説明した構造の半導体装置の製造方法について説明する。図３に、本実施形態における半導体装置の製造工程の一部を示す。なお、図３は、図１に対応する図である。また、本実施形態の半導体装置の製造方法は、上記発明が解決しようとする課題の欄で説明した製造方法と、基本的に同じであり、以下では、この製造方法と異なる点についてのみ説明する。   Next, a method for manufacturing the semiconductor device having the above-described structure will be described. FIG. 3 shows a part of the manufacturing process of the semiconductor device in this embodiment. FIG. 3 corresponds to FIG. In addition, the manufacturing method of the semiconductor device of the present embodiment is basically the same as the manufacturing method described in the column of the problem to be solved by the invention, and only differences from the manufacturing method will be described below. .

まず、第１の金属体３、半導体素子１、第３の金属体６、第１の接合材８、第２の接合材９を用意する。   First, a first metal body 3, a semiconductor element 1, a third metal body 6, a first bonding material 8, and a second bonding material 9 are prepared.

そして、第１の金属体３と半導体素子１と第３の金属体６とを接合する工程では、第１の金属体３の上に、半田箔８と、半導体素子１と、半田箔９と、第３の金属体６とを積層する際に、第１の金属体３と第３の金属体６の間に第１の保持治具（スペーサ）２１を配置する。   In the step of joining the first metal body 3, the semiconductor element 1, and the third metal body 6, the solder foil 8, the semiconductor element 1, the solder foil 9, When the third metal body 6 is laminated, a first holding jig (spacer) 21 is disposed between the first metal body 3 and the third metal body 6.

このとき、第３の金属体６の第２の領域１２を、第１の保持治具２１で保持させるように、第１の保持治具２１を配置する。言い換えると、第３の金属体６のうち、大きな半導体素子１ａと接合される予定の第１の領域１１と、小さな半導体素子１ｂと接合される予定の第１の領域１１とを繋ぐ部分１２を保持するように、第１の保持治具２１を１つ配置する。本実施形態における第１の領域１１と、第２の領域１２が、それぞれ、本発明における第３の金属体の半導体素子と接合される接合予定領域と、接合予定領域と異なる領域に相当する。   At this time, the first holding jig 21 is arranged so that the second region 12 of the third metal body 6 is held by the first holding jig 21. In other words, a portion 12 of the third metal body 6 that connects the first region 11 that is to be bonded to the large semiconductor element 1a and the first region 11 that is to be bonded to the small semiconductor element 1b. One first holding jig 21 is arranged so as to hold it. The first region 11 and the second region 12 in the present embodiment correspond to a region to be bonded to the third metal body semiconductor element in the present invention and a region different from the region to be bonded, respectively.

なお、この第１の保持治具２１は、第１の金属体３に対向する面２１ａと、第３の金属体６に対向する面２１ｂとが平行であり、図１中の上下方向における高さ２１ｃが、完成された半導体装置における第１の金属体３と第３の金属体６との所定間隔３２（図１３参照）と同じ大きさとなっている。   In the first holding jig 21, the surface 21a facing the first metal body 3 and the surface 21b facing the third metal body 6 are parallel, and the height in the vertical direction in FIG. 21c is the same size as the predetermined distance 32 (see FIG. 13) between the first metal body 3 and the third metal body 6 in the completed semiconductor device.

続いて、このように第１の保持治具２１が配置された状態で、第１の金属体３と半導体素子１、半導体素子１と第３の金属体６を接合する。   Subsequently, the first metal body 3 and the semiconductor element 1 and the semiconductor element 1 and the third metal body 6 are joined in a state where the first holding jig 21 is arranged in this way.

また、第３の金属体６に第２の金属体５を積層する工程では、第１の保持治具２１が配置された状態で、第３の金属体６の上に、半田箔１０と、第２の金属体５とを積層する。これにより、第１の金属体３、第１の接合材８、半導体素子１、第２の接合材９、第３の金属体６、第３の接合材１０、第２の金属体５が順に積層された状態となる。   Further, in the step of laminating the second metal body 5 on the third metal body 6, the solder foil 10 is placed on the third metal body 6 with the first holding jig 21 disposed. The second metal body 5 is laminated. Accordingly, the first metal body 3, the first bonding material 8, the semiconductor element 1, the second bonding material 9, the third metal body 6, the third bonding material 10, and the second metal body 5 are sequentially formed. It will be in the laminated state.

このとき、第１の金属体３と第２の金属体５との間に、図示しない第２の保持治具を配置する。この第２の保持治具は、上記発明が解決しようとする課題の欄で説明した保持治具（スペーサ）である。なお、第３の金属体６に第２の金属体５を積層する工程が、本発明の第１の金属体３、第１の接合材８、半導体素子１等を積層した状態とし、かつ、保持治具を配置する工程に相当する。   At this time, a second holding jig (not shown) is disposed between the first metal body 3 and the second metal body 5. This 2nd holding jig is the holding jig (spacer) demonstrated in the column of the problem which the said invention is going to solve. The step of laminating the second metal body 5 on the third metal body 6 is a state in which the first metal body 3, the first bonding material 8, the semiconductor element 1 and the like of the present invention are laminated, and This corresponds to the step of arranging the holding jig.

第３の金属体６と第２の金属体５を接合する工程（最終的な全体の接合をする工程）では、第１の保持治具２１と第２の保持治具とが配置された状態で、接合を行う。これにより、第１の金属体３、半導体素子１、第３の金属体６、第２の金属体５が接合される。その後、第１の保持治具２１と第２の保持治具とを取り外す。   In the step of joining the third metal body 6 and the second metal body 5 (final overall joining step), the first holding jig 21 and the second holding jig are arranged. Then, joining is performed. Thereby, the 1st metal body 3, the semiconductor element 1, the 3rd metal body 6, and the 2nd metal body 5 are joined. Thereafter, the first holding jig 21 and the second holding jig are removed.

次に、全体をモールド樹脂７により封止する工程を行う。このようにして、図１に示す半導体装置が完成する。   Next, the whole is sealed with the mold resin 7. In this way, the semiconductor device shown in FIG. 1 is completed.

以上説明したように、本実施形態では、第２の領域１２を有する第３の金属体６を用いている。また、第１の金属体３と第３の金属体６の間であって、第３の金属体６の第２の領域１２を保持するように、第１の保持治具（スペーサ）２１を配置している。そして、第１の保持治具が配置された状態で、積層された第１の金属体３、半導体素子１、第３の金属体６、第２の金属体５を加熱し、圧力を加えることで、これら全体の最終的な接合を行っている。   As described above, in the present embodiment, the third metal body 6 having the second region 12 is used. Further, the first holding jig (spacer) 21 is provided between the first metal body 3 and the third metal body 6 so as to hold the second region 12 of the third metal body 6. It is arranged. Then, in a state where the first holding jig is arranged, the stacked first metal body 3, semiconductor element 1, third metal body 6, and second metal body 5 are heated and pressure is applied. The final joining of these whole is performed.

これにより、第１の金属体３の半導体素子１と対向する面３ａと、第３の金属体６の半導体素子１に対向する面６ｃとを平行に保ち、第１の金属体３と第３の金属体６との間隔を所定の間隔３２に保ちながら、最終的な接合を行うことができる。   As a result, the surface 3a of the first metal body 3 facing the semiconductor element 1 and the surface 6c of the third metal body 6 facing the semiconductor element 1 are kept in parallel, and the first metal body 3 and the third metal body 3 The final bonding can be performed while maintaining the predetermined distance 32 to the metal body 6.

この結果、本実施形態によれば、この第１の保持治具２１を用いない半導体装置の製造方法と比較して、最終的な接合時に第３の金属体６が自由に動くことに起因する半導体素子１の動作不良の発生と、半導体装置の寿命の低下を抑制することができる。   As a result, according to the present embodiment, the third metal body 6 moves freely at the time of final bonding as compared with the method of manufacturing the semiconductor device that does not use the first holding jig 21. It is possible to suppress the occurrence of malfunction of the semiconductor element 1 and the decrease in the lifetime of the semiconductor device.

なお、上記発明が解決しようとする課題の欄で説明した半導体装置の製造方法では、第３の金属体６が移動することで、さらに、半導体素子１に応力が加わり、半導体素子１も移動したり、半導体素子１が傾いたりしていたと考えられる。このことも、第１の接合材８が薄くなる要因であり、半導体素子１の動作不良の発生と、半導体装置の寿命の低下を引き起こしていたと考えられる。   In the method of manufacturing a semiconductor device described in the section of the problem to be solved by the present invention, the third metal body 6 moves, so that stress is further applied to the semiconductor element 1 and the semiconductor element 1 also moves. It is considered that the semiconductor element 1 is tilted. This is also a factor that makes the first bonding material 8 thin, and it is considered that the operation failure of the semiconductor element 1 occurred and the life of the semiconductor device was reduced.

これに対して、本実施形態によれば、第３の金属体６と第１の金属体３とを平行とし、これらの間隔を一定に保つことができるので、上記発明が解決しようとする課題の欄で説明した半導体装置の製造方法と比較して、半導体素子１の移動や傾きを抑制することができる。このことからも、本実施形態によれば、上記発明が解決しようとする課題の欄で説明した半導体装置の製造方法と比較して、半導体素子１の動作不良の発生と、半導体装置の寿命の低下を抑制することができると言える。   On the other hand, according to the present embodiment, the third metal body 6 and the first metal body 3 can be parallel and the distance between them can be kept constant. Compared with the manufacturing method of the semiconductor device described in the column, the movement and inclination of the semiconductor element 1 can be suppressed. Also from this, according to the present embodiment, compared with the method of manufacturing a semiconductor device described in the column of problems to be solved by the invention, the occurrence of malfunction of the semiconductor element 1 and the lifetime of the semiconductor device are reduced. It can be said that the decrease can be suppressed.

また、本実施形態では、１つの第１の金属体３と１つの第３の金属体６との間に、２つの半導体素子１ａ、１ｂを配置させている。すなわち、本実施形態では、２つの半導体素子１ａ、１ｂの両方を覆うことができる大きさの第３の金属体６を１つ用意し、この１つの第３の金属体６に２つの半導体素子１ａ、１ｂと接合させている。   In the present embodiment, two semiconductor elements 1 a and 1 b are arranged between one first metal body 3 and one third metal body 6. That is, in the present embodiment, one third metal body 6 having a size capable of covering both of the two semiconductor elements 1a and 1b is prepared, and two semiconductor elements are provided on the third metal body 6. It is joined to 1a and 1b.

図１３に示す半導体装置では、１つの半導体素子１に対して、１つの第３の金属体６が配置されていた。この場合、半導体装置の製造時において、第１の金属体３、半導体素子１、第３の金属体６を接合する工程や、最終的に全体を接合する工程では、第３の金属体６と半導体素子１との間で、ズレが生じないように、それぞれの第３の金属体６を、適切な位置に保持する必要があった。第３の金属体６を複数用いた場合では、そのうちの１つでも、位置ズレが生じてしまうと、半導体装置としては不良品として扱われるため、全てが第１の金属体３に対して、位置ズレが発生しないようにする必要があった。   In the semiconductor device shown in FIG. 13, one third metal body 6 is arranged for one semiconductor element 1. In this case, at the time of manufacturing the semiconductor device, in the step of bonding the first metal body 3, the semiconductor element 1, and the third metal body 6, or the step of finally bonding the whole, It is necessary to hold each third metal body 6 at an appropriate position so that no deviation occurs between the semiconductor element 1 and the semiconductor element 1. In the case where a plurality of third metal bodies 6 are used, if even one of them is misaligned, it is treated as a defective product as a semiconductor device. It was necessary to prevent misalignment.

これに対して、本実施形態では、２つの半導体素子１ａ、１ｂに対して、１つの第３の金属体６を接合しているため、１つの第３の金属体６のみを、適切な位置に保持すれば良い。また、第３の金属体６が１つであるため、第３の金属体６を２つ用いていた図１３に示す半導体装置と比較して、第３の金属体６の位置ズレが生じる要因を減らすことができるので、半導体装置の不良品の発生率を減少させることができる。   In contrast, in the present embodiment, since one third metal body 6 is bonded to two semiconductor elements 1a and 1b, only one third metal body 6 is placed at an appropriate position. Just hold it. In addition, since there is one third metal body 6, the third metal body 6 may be misaligned as compared to the semiconductor device illustrated in FIG. 13 in which two third metal bodies 6 are used. Therefore, the occurrence rate of defective products of the semiconductor device can be reduced.

また、複数の第３の金属体６を用いた場合では、第３実施形態で説明するように、それぞれの第３の金属体６を保持するための第１の保持治具２１が必要である。これに対して、本実施形態では、１つの第３の金属体６のみを用いているので、必要な第１の保持治具２１の数を、複数の第３の金属体６を用いた場合と比較して、少なくすることができる。   Further, in the case where a plurality of third metal bodies 6 are used, as described in the third embodiment, the first holding jig 21 for holding each third metal body 6 is necessary. . On the other hand, in this embodiment, since only one third metal body 6 is used, the number of necessary first holding jigs 21 is the same as when a plurality of third metal bodies 6 are used. Compared to, it can be reduced.

また、本実施形態の第３の金属体６は、半導体素子１と接合されている第１の領域１１だけでなく、半導体素子１と接合されていない第２の領域１２を有しており、図１３に示す第３の金属体６よりも体積が大きい。このため、本実施形態の半導体装置では、図１３に示す半導体装置と比較して、半導体素子１で発生した熱の放熱性が高くなっている。   Further, the third metal body 6 of the present embodiment has not only the first region 11 joined to the semiconductor element 1 but also the second region 12 not joined to the semiconductor element 1. The volume is larger than that of the third metal body 6 shown in FIG. For this reason, in the semiconductor device of this embodiment, the heat dissipation of the heat generated in the semiconductor element 1 is higher than that of the semiconductor device shown in FIG.

（第２実施形態）
図４、５に、本発明の第２実施形態における半導体装置を示す。図４、５は、図１、２にそれぞれ対応している。本実施形態は、第３の金属体６の外周に被保持部が設けられている点が、第１実施形態と異なっている。以下では、第１実施形態と異なる点のみ説明し、第１実施形態と同様の構造部については、図４、５において、図１、２と同一の符号を付すことで説明を省略する。 (Second Embodiment)
4 and 5 show a semiconductor device according to the second embodiment of the present invention. 4 and 5 correspond to FIGS. 1 and 2, respectively. This embodiment is different from the first embodiment in that a held portion is provided on the outer periphery of the third metal body 6. Below, only a different point from 1st Embodiment is demonstrated, and about the structure part similar to 1st Embodiment, description is abbreviate | omitted by attaching | subjecting the code | symbol same as FIG.

本実施形態では、図４、５に示すように、第３の金属体６は、外周の一部（図中の左右両端側）に鍔形状をした鍔形状部１２ａが設けられている。すなわち、第３の金属体６は、外周にも、第２の領域１２、１２ａ（図５中実線のみが斜めに引かれている領域）を有しており、この外周の第２の領域１２ａも、第１の領域１１よりも薄くなっている。なお、外周の第２の領域１２ａは、図４に示すように、第２の金属体５と対向する面６ｄが、第１の領域１１における第２の金属体５と対向する面６ｄと同じ高さとなっている。   In the present embodiment, as shown in FIGS. 4 and 5, the third metal body 6 is provided with a hook-shaped portion 12 a having a hook shape on a part of the outer periphery (on the left and right ends in the drawing). That is, the third metal body 6 has second regions 12 and 12a (regions in which only the solid line in FIG. 5 is diagonally drawn) on the outer periphery, and the second region 12a on the outer periphery. Is thinner than the first region 11. As shown in FIG. 4, the outer peripheral second region 12 a has the same surface 6 d facing the second metal body 5 as the surface 6 d facing the second metal body 5 in the first region 11. It is height.

さらに言い換えると、第１の金属体３の主表面は、図５に示すように、２つの半導体素子１ａ、１ｂの主表面よりも大きな面積であって、第１の金属体３の外周部は、半導体素子１と対向していない。そして、第３の金属体は、２つの半導体素子１ａ、１ｂと接合する第１の領域１１のみが、半導体素子１ａ、１ｂに向かって突出している形状となっている。   In other words, the main surface of the first metal body 3 has a larger area than the main surfaces of the two semiconductor elements 1a and 1b as shown in FIG. The semiconductor element 1 is not opposed. The third metal body has a shape in which only the first region 11 joined to the two semiconductor elements 1a and 1b protrudes toward the semiconductor elements 1a and 1b.

鍔形状部１２ａは、主表面の形状が四角形である第３の金属体６のうち、図５に示すように、対向する二組の辺のうち、一組の辺（図５中の左右両側の辺）に設けられている。   As shown in FIG. 5, among the third metal body 6 whose main surface has a quadrangular shape, the flange-shaped portion 12a has one set of sides (on the left and right sides in FIG. 5). Side).

図６に、上記した構造の半導体装置の製造工程の一部を示す。本実施形態では、第３の金属体６に設けられている鍔形状部１２ａを、第１の保持治具２１で保持させる。このような状態で、最終的な全体の接合を行うこともできる。   FIG. 6 shows a part of the manufacturing process of the semiconductor device having the above structure. In the present embodiment, the hook-shaped portion 12 a provided on the third metal body 6 is held by the first holding jig 21. In such a state, the final entire joining can be performed.

本実施形態のように、第３の金属体６の外周部に鍔形状部１２ａを設けた場合においても第１実施形態と同様の効果を有しており、さらに以下の効果を有している。   Even in the case where the flange-shaped portion 12a is provided on the outer peripheral portion of the third metal body 6 as in the present embodiment, the same effect as that of the first embodiment is obtained, and the following effect is further obtained. .

最終的な接合をする工程で加熱をした際に、第２の接合材（半田）９が、他の接合材８、１０よりも先に溶融された場合、第１の金属体３と第２の金属体５とに加えられた応力によって、この第２の接合材９が、半導体素子１と第３の金属体６との接合部から、はみ出すおそれがある。この場合、第２の接合材９がはみ出して、第１の金属体３まで到達すると、半導体素子１の表裏面等が短絡してしまう。   When the second bonding material (solder) 9 is melted before the other bonding materials 8 and 10 when heated in the final bonding step, the first metal body 3 and the second metal Due to the stress applied to the metal body 5, the second bonding material 9 may protrude from the bonding portion between the semiconductor element 1 and the third metal body 6. In this case, when the second bonding material 9 protrudes and reaches the first metal body 3, the front and back surfaces of the semiconductor element 1 are short-circuited.

そこで、上記したような鍔形状部１２ａを有する第３の金属体６を用いることで、第２の接合材９がはみ出すようなことがあっても、第２の接合材９は、第３の金属体６の第１の領域１１における半導体素子１との接続面１１ａに隣接する側面１１ｂと、鍔形状部１２ａとに沿って流れ、その側面１１ｂと鍔形状部１２ａとに付着し、留められる。このため、本実施形態によれば、半導体素子１の表裏面等の短絡を防止することができる。   Therefore, by using the third metal body 6 having the hook-shaped portion 12a as described above, even if the second bonding material 9 may protrude, the second bonding material 9 is It flows along the side surface 11b adjacent to the connection surface 11a with the semiconductor element 1 in the first region 11 of the metal body 6 and the hook-shaped portion 12a, and adheres to the side surface 11b and the hook-shaped portion 12a and is fastened. . For this reason, according to this embodiment, it is possible to prevent a short circuit on the front and back surfaces of the semiconductor element 1.

なお、本実施形態では、鍔形状部１２ａを第３の金属体６の外周部のうち、一組の辺に相当する部位に設ける場合を例として説明したが、鍔形状部１２ａは、この部位に限らず、外周部の他の部位に設けたり、鍔形状部１２ａの数を適宜変更したりすることもできる。また、第３の金属体６の外周部の全域に鍔形状部１２ａを設けることもできる。すなわち、第３の金属体６の外周部のうち、少なくとも第１の保持治具２１を配置するのに必要な部位に、鍔形状部１２ａを設ければ良い。   In the present embodiment, the case where the hook-shaped portion 12a is provided in a portion corresponding to a set of sides in the outer peripheral portion of the third metal body 6 has been described as an example. Not limited to this, it may be provided in other parts of the outer peripheral portion, or the number of the hook-shaped portions 12a may be changed as appropriate. Moreover, the hook-shaped part 12a can also be provided in the whole outer peripheral part of the 3rd metal body 6. FIG. That is, it is only necessary to provide the hook-shaped portion 12 a in a portion necessary for arranging the first holding jig 21 in the outer peripheral portion of the third metal body 6.

図７に、本実施形態の変形例を示す。図７に示すように、第１の保持治具２１の形状を、例えば、第３の金属体６を保持する面と、第２の金属体５を保持する面とを有する形状とすることもできる。これにより、第１の金属体３と第２の金属体５との間隔と、第１の金属体３と第３の金属体６との間隔とを１つの第１の保持治具２１で設定することができる。   FIG. 7 shows a modification of the present embodiment. As shown in FIG. 7, the shape of the first holding jig 21 may be, for example, a shape having a surface that holds the third metal body 6 and a surface that holds the second metal body 5. it can. Thereby, the space | interval of the 1st metal body 3 and the 2nd metal body 5, and the space | interval of the 1st metal body 3 and the 3rd metal body 6 are set with one 1st holding jig 21. can do.

（第３実施形態）
図８、９に、本発明の第３実施形態における半導体装置を示す。図８、９は、図４、５にそれぞれ対応している。なお、図８、９では、図４、５と同様の構造部については、図４、５と同一の符号を付している。 (Third embodiment)
8 and 9 show a semiconductor device according to the third embodiment of the present invention. 8 and 9 correspond to FIGS. 4 and 5, respectively. In FIGS. 8 and 9, the same reference numerals as those in FIGS.

本実施形態では、２つの半導体素子１ａ、１ｂに、それぞれ対応するように、２つの第３の金属体６を用いている。そして、それぞれの第３の金属体６は、第２実施形態と同様に、外周部に鍔形状部１２ａが設けられている。   In the present embodiment, two third metal bodies 6 are used so as to correspond to the two semiconductor elements 1a and 1b, respectively. And each 3rd metal body 6 is provided with the collar-shaped part 12a in the outer peripheral part similarly to 2nd Embodiment.

図１０に、上記した構造の半導体装置の製造工程の一部を示す。本実施形態においても、第３の金属体６の鍔形状部１２ａを、第１の保持治具２１で保持した状態で、最終的な全体の接合を行う。なお、本実施形態の場合、それぞれの第３の金属体６と第１の金属体３との間隔を一定に保つ必要があるため、第２実施形態と比較して、必要な第１の保持治具２１の数が多い。   FIG. 10 shows a part of the manufacturing process of the semiconductor device having the above structure. Also in the present embodiment, final overall bonding is performed in a state where the hook-shaped portion 12 a of the third metal body 6 is held by the first holding jig 21. In the case of this embodiment, it is necessary to keep the distance between each third metal body 6 and the first metal body 3 constant, so that the necessary first holding is required as compared with the second embodiment. The number of jigs 21 is large.

このように、２つの半導体素子１ａ、１ｂに、それぞれ１対１で対応するように、２つの第３の金属体６を用いた場合においても、本発明を適用できる。なお、本実施形態では、２つの半導体素子１ａ、１ｂに対して、２つの第３の金属体６を配置する場合を例として、説明したが、第３の金属体６の数は、用いられる半導体素子１の数に合わせて、適宜変更可能である。   Thus, the present invention can also be applied to the case where two third metal bodies 6 are used so as to correspond to the two semiconductor elements 1a and 1b on a one-to-one basis. In the present embodiment, the case where the two third metal bodies 6 are arranged with respect to the two semiconductor elements 1a and 1b has been described as an example. However, the number of the third metal bodies 6 is used. The number can be changed as appropriate according to the number of the semiconductor elements 1.

（第４実施形態）
図１１に、本発明の第４実施形態における半導体装置を示す。図１１は、図３に対応している。なお、図１１では、図３と同様の構造部については、図３と同一の符号を付している。 (Fourth embodiment)
FIG. 11 shows a semiconductor device according to the fourth embodiment of the present invention. FIG. 11 corresponds to FIG. In FIG. 11, the same reference numerals as those in FIG. 3 are assigned to the structural parts similar to those in FIG. 3.

第２、第３実施形態では、第３の金属体６の外周部に第２の領域１２（鍔形状部１２ａ）が設けられ、その外周部の第２の領域１２ａが、第１の領域１１よりも薄い第３の金属体６を用いていたが、本実施形態のように、外周部の第２の領域１２ａが、第１の領域１１と同じ厚さである第３の金属体６を用いることもできる。   In the second and third embodiments, the second region 12 (the ridge-shaped portion 12 a) is provided on the outer peripheral portion of the third metal body 6, and the second region 12 a on the outer peripheral portion is the first region 11. The thinner third metal body 6 is used. However, as in the present embodiment, the second region 12a in the outer peripheral portion has the same thickness as that of the first region 11. It can also be used.

ただし、単に、外周部の第２の領域１２ａを第１の領域１１と同じ厚さとした場合、接合時において、半田が第３の金属体６に沿って流れ、半田が半導体素子１上から外側に向かって広がってしまうおそれがある。   However, when the second region 12a in the outer peripheral portion is made to have the same thickness as the first region 11, the solder flows along the third metal body 6 at the time of joining, and the solder flows from the semiconductor element 1 to the outside. There is a risk of spreading toward.

そこで、図１１に示すように、第１の領域１１と第２の領域１２との境界近傍に、溝１３を設けておく。これにより、かりに、半田が第３の金属体６に沿って流れたとしても、溝１３に半田が溜まるので、半田の広がりを抑制することができる。   Therefore, as shown in FIG. 11, a groove 13 is provided in the vicinity of the boundary between the first region 11 and the second region 12. Thereby, even if the solder flows along the third metal body 6, the solder accumulates in the groove 13, so that the spread of the solder can be suppressed.

（第５実施形態）
図１２に、本発明の第５実施形態における半導体装置を示す。図１２は、図３に対応している。なお、図１２では、図３と同様の構造部については、図３と同一の符号を付している。 (Fifth embodiment)
FIG. 12 shows a semiconductor device according to the fifth embodiment of the present invention. FIG. 12 corresponds to FIG. In FIG. 12, the same reference numerals as those in FIG.

第１〜第４実施形態では、第１の保持治具２１を、第１の金属体３と第３の金属体６との間に配置し、第１の金属体３と第３の金属体６とを第１の保持治具２１で保持させる場合を例として説明したが、本実施形態のように、第１の金属体３と第３の金属体６との間に、第１の保持治具２１を配置せずに、第１の金属体３と第３の金属体６との間隔を所定間隔３２に保持することができる。   In 1st-4th embodiment, the 1st holding jig 21 is arrange | positioned between the 1st metal body 3 and the 3rd metal body 6, and the 1st metal body 3 and the 3rd metal body As an example, the first holding jig 21 holds the first holding jig 21. However, as in the present embodiment, between the first metal body 3 and the third metal body 6, the first holding The interval between the first metal body 3 and the third metal body 6 can be maintained at the predetermined interval 32 without arranging the jig 21.

本実施形態では、図１２に示すように、第１の金属体３として、第１の領域１１で半導体素子１と対向する（接合される）面６ｃと、その面６ｃに隣接する第１の領域１１の側面６ｅと、側面６ｅに設けられた凹部１４とを有する第３の金属体６を用いる。   In the present embodiment, as shown in FIG. 12, as the first metal body 3, a surface 6 c facing (bonded) to the semiconductor element 1 in the first region 11, and a first surface adjacent to the surface 6 c. The 3rd metal body 6 which has the side surface 6e of the area | region 11 and the recessed part 14 provided in the side surface 6e is used.

また、第１の保持治具２１としては、凸部２４を有するものを用いる。そして、第１の保持治具２１の凸部２４を第３の金属体６の凹部１４にはめ、第１の金属体３と平行な面２１ａで第１の金属体３を保持する。このように、第１の保持治具２１を第１の金属体３と第２の金属体５との間に配置した状態で、最終的な全体の接合を行うこともできる。   Further, as the first holding jig 21, one having a convex portion 24 is used. Then, the convex portion 24 of the first holding jig 21 is fitted into the concave portion 14 of the third metal body 6, and the first metal body 3 is held by the surface 21 a parallel to the first metal body 3. As described above, the final entire joining can be performed in a state where the first holding jig 21 is disposed between the first metal body 3 and the second metal body 5.

（他の実施形態）
第１、第２、第４、第５実施形態では、２つの半導体素子１ａ、１ｂを用いる場合を例として説明したが、半導体素子１の数は２つに限らず、１つ、３つ、４つ等他の数でも良い。また、半導体素子１を３つ以上用いる場合では、全ての半導体素子１を１つの第３の金属体６に接合させたり、全ての半導体素子ではないが、複数の半導体素子１を１つの第１の金属体３に接合させたりすることができる。 (Other embodiments)
In the first, second, fourth, and fifth embodiments, the case where two semiconductor elements 1a and 1b are used has been described as an example. However, the number of semiconductor elements 1 is not limited to two, and one, three, Other numbers such as four may be used. When three or more semiconductor elements 1 are used, all the semiconductor elements 1 are joined to one third metal body 6, or not all semiconductor elements 1, but a plurality of semiconductor elements 1 are combined into one first element. The metal body 3 can be joined.

後者の例としては、半導体素子１を３つ用いる場合、２つの半導体素子１を１つの第３の金属体６と接合させ、残りの１つの半導体素子１を他の第３の金属体６と接合させることもできる。すなわち、３つの半導体素子１に対して、２つの第３の金属体６を用いることもできる。   As an example of the latter, when three semiconductor elements 1 are used, two semiconductor elements 1 are joined to one third metal body 6 and the remaining one semiconductor element 1 is joined to another third metal body 6. It can also be joined. That is, two third metal bodies 6 can be used for the three semiconductor elements 1.

また、半導体素子１を４つ用いる場合では、２つの第３の金属体６を用い、それぞれの第３の金属体６に対して接合される半導体素子１の数の比を、２：２や、３：１とすることもできる。   When four semiconductor elements 1 are used, the two third metal bodies 6 are used, and the ratio of the number of semiconductor elements 1 bonded to each third metal body 6 is set to 2: 2 or Or 3: 1.

本発明の第１実施形態における半導体装置を側面方向から内部を透過して見たときの内部構成を示す図である。It is a figure which shows an internal structure when the semiconductor device in 1st Embodiment of this invention is seen through the inside from the side surface direction. 図１の半導体装置を図中の矢印方向で見たときの図である。It is a figure when the semiconductor device of FIG. 1 is seen in the arrow direction in a figure. 図１の半導体装置の製造工程を説明するための図である。FIG. 2 is a diagram for explaining a manufacturing process of the semiconductor device of FIG. 1. 本発明の第２実施形態の第１の例における半導体装置を側面方向から内部を透過して見たときの内部構成を示す図である。It is a figure which shows an internal structure when the semiconductor device in the 1st example of 2nd Embodiment of this invention is seen through the inside from the side surface direction. 図４の半導体装置を図中の矢印方向で見たときの図である。It is a figure when the semiconductor device of FIG. 4 is seen in the arrow direction in the figure. 図４の半導体装置の製造工程を説明するための図である。FIG. 5 is a diagram for explaining a manufacturing process of the semiconductor device of FIG. 4. 本発明の第２実施形態の第２の例における半導体装置を側面方向から内部を透過して見たときの内部構成を示す図である。It is a figure which shows an internal structure when the semiconductor device in the 2nd example of 2nd Embodiment of this invention is seen through the inside from the side surface direction. 本発明の第３実施形態における半導体装置を側面方向から内部を透過して見たときの内部構成を示す図である。It is a figure which shows an internal structure when the semiconductor device in 3rd Embodiment of this invention is seen through the inside from the side surface direction. 図８の半導体装置を図中の矢印方向で見たときの図である。It is a figure when the semiconductor device of FIG. 8 is seen in the direction of the arrow in the figure. 図１０の半導体装置の製造工程を説明するための図である。FIG. 11 is a diagram for explaining a manufacturing process for the semiconductor device of FIG. 10; 本発明の第４実施形態における半導体装置を側面方向から内部を透過して見たときの内部構成を示す図である。It is a figure which shows an internal structure when the inside is seen through the inside from the side surface direction of the semiconductor device in 4th Embodiment of this invention. 本発明の第５実施形態における半導体装置を側面方向から内部を透過して見たときの内部構成を示す図である。It is a figure which shows an internal structure when the semiconductor device in 5th Embodiment of this invention is seen through the inside from the side surface direction. 従来における半導体装置を側面方向から内部を透過して見たときの内部構成を示す図である。It is a figure which shows an internal structure when the semiconductor device in the past is seen through the inside from the side surface direction. 本発明が解決しようとする課題を説明するための図であり、図１３中の第３の金属体６等を示す図である。It is a figure for demonstrating the subject which this invention tends to solve, and is a figure which shows the 3rd metal body 6 grade | etc., In FIG.

符号の説明Explanation of symbols

１…半導体素子、３…第１の金属体、５…第２の金属体、６…第３の金属体、
７…モールド樹脂、８…第１の接合材、９…第２の接合材、１０…第３の接合材、
１１…第１の領域、１２…第２の領域、１２ａ…鍔形状部、１４…凹部、
２１…第１の保持治具、２４…凸部。 DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 3 ... 1st metal body, 5 ... 2nd metal body, 6 ... 3rd metal body,
7 ... Mold resin, 8 ... First bonding material, 9 ... Second bonding material, 10 ... Third bonding material,
DESCRIPTION OF SYMBOLS 11 ... 1st area | region, 12 ... 2nd area | region, 12a ... ridge-shaped part, 14 ... recessed part,
21 ... 1st holding jig, 24 ... Convex part.

Claims (10)

半導体素子（１）と、前記半導体素子（１）の裏面（２）側に設けられ電極と放熱体とを兼ねる第１の金属体（３）と、前記半導体素子（１）の表面（４）側に設けられ電極と放熱体とを兼ねる第２の金属体（５）と、前記半導体素子（１）の表面（４）と前記第２の金属体（５）との間に設けられた第３の金属体（６）と、前記半導体素子（１）、前記第１の金属体（３）、前記第２の金属体（５）、前記第３の金属体（６）を封止するモールド樹脂（７）とを備えた半導体装置の製造方法において、
前記第１の金属体（３）、第１の接合材（８）、前記半導体素子（１）、第２の接合材（９）、前記第３の金属体（６）、第３の接合材（１０）および前記第２の金属体（５）を用意する工程と、
前記第１の金属体（３）、第１の接合材（８）、前記半導体素子（１）、第２の接合材（９）、前記第３の金属体（６）、第３の接合材（１０）および前記第２の金属体（５）を順に積層した状態とし、かつ、前記第１の金属体（３）と前記第２の金属体（５）との間であって、前記半導体素子（１）が配置された領域を除く領域に、前記第１の金属体（３）と前記第３の金属体（６）とを保持する保持治具（２１）を配置する工程と、
前記保持治具（２１）を配置した状態で、前記積層された状態の前記第１の金属体（３）、前記第１の接合材（８）、前記半導体素子（１）、前記第２の接合材（９）、前記第３の金属体（６）、前記第３の接合材（１０）および前記第２の金属体（５）に対して、加熱処理を施すことにより、前記第１の金属体（３）と前記半導体素子（１）、前記半導体素子（１）と前記第３の金属体（６）、前記第３の金属体（６）と前記第２の金属体（５）を、それぞれ接合する工程と、
前記半導体素子（１）、前記第１の金属体（３）、前記第２の金属体（５）、前記第３の金属体（６）をモールド樹脂（７）で封止する工程とを有し、
前記第３の金属体（６）を用意する工程では、前記半導体素子（１）と接合される接合予定領域（１１）と異なる領域（１２、１２ａ、１４）に、前記保持治具（２１）によって保持される被保持部（１２、１２ａ、１４）を備える前記第３の金属体（６）を用意することを特徴とする半導体装置の製造方法。 A semiconductor element (1), a first metal body (3) provided on the back surface (2) side of the semiconductor element (1) and serving as an electrode and a radiator, and a surface (4) of the semiconductor element (1) A second metal body (5) provided on the side and serving as both an electrode and a radiator, and a second metal body (5) provided between the surface (4) of the semiconductor element (1) and the second metal body (5). 3 metal body (6), mold for sealing the semiconductor element (1), the first metal body (3), the second metal body (5), and the third metal body (6) In a method for manufacturing a semiconductor device comprising a resin (7),
The first metal body (3), the first bonding material (8), the semiconductor element (1), the second bonding material (9), the third metal body (6), and the third bonding material. (10) and a step of preparing the second metal body (5);
The first metal body (3), the first bonding material (8), the semiconductor element (1), the second bonding material (9), the third metal body (6), and the third bonding material. (10) and the second metal body (5) are sequentially stacked, and between the first metal body (3) and the second metal body (5), the semiconductor Disposing a holding jig (21) for holding the first metal body (3) and the third metal body (6) in a region excluding the region where the element (1) is disposed;
With the holding jig (21) disposed, the first metal body (3), the first bonding material (8), the semiconductor element (1), and the second layer in the stacked state are disposed. By applying heat treatment to the bonding material (9), the third metal body (6), the third bonding material (10), and the second metal body (5), The metal body (3) and the semiconductor element (1), the semiconductor element (1) and the third metal body (6), the third metal body (6) and the second metal body (5). Each of the steps of joining,
Sealing the semiconductor element (1), the first metal body (3), the second metal body (5), and the third metal body (6) with a mold resin (7). And
In the step of preparing the third metal body (6), the holding jig (21) is placed in a region (12, 12a, 14) different from the planned joining region (11) to be joined to the semiconductor element (1). The third metal body (6) including the held parts (12, 12a, 14) held by the step is prepared. 前記第３の金属体（６）を用意する工程では、前記半導体素子（１）と接合される接合予定領域（１１）と異なる領域に、前記接合予定領域（１１）よりも薄い部分（１２）を備える前記第３の金属体（６）を用意し、
前記保持治具（２１）を配置する工程では、前記第３の金属体（６）の前記薄い部分（１２、１２ａ）を、前記保持治具（２１）で保持させるように、前記保持治具（２１）を配置することを特徴とする請求項１に記載の半導体装置の製造方法。 In the step of preparing the third metal body (6), a portion (12) thinner than the planned junction region (11) in a region different from the planned junction region (11) to be joined to the semiconductor element (1). Preparing the third metal body (6) comprising:
In the step of arranging the holding jig (21), the holding jig (21) is configured to hold the thin portions (12, 12a) of the third metal body (6) with the holding jig (21). The method of manufacturing a semiconductor device according to claim 1, wherein (21) is arranged. 前記第３の金属体（６）を用意する工程では、前記半導体素子（１）と接合される接合予定領域（１１）の外周部の一部に、前記接合予定領域（１１）よりも薄い部分（１２ａ）を備える前記第３の金属体（６）を用意することを特徴とする請求項１または２に記載の半導体装置の製造方法。 In the step of preparing the third metal body (6), a portion thinner than the planned joining region (11) is formed in a part of the outer peripheral portion of the planned joining region (11) joined to the semiconductor element (1). The method for manufacturing a semiconductor device according to claim 1, wherein the third metal body (6) including (12 a) is prepared. 前記第３の金属体（６）を用意する工程では、前記半導体素子（１）と接合される面（６ｃ）に隣接する側面（６ｅ）と、前記側面（６ｅ）に設けられた凹部（１４）とを備える前記第３の金属体（６）を用意し、
前記保持治具（２１）を配置する工程では、前記第３の金属体（６）の前記凹部（１４）を、前記保持治具（２１）で保持させるように、前記保持治具（２１）を配置することを特徴とする請求項１に記載の半導体装置の製造方法。 In the step of preparing the third metal body (6), the side surface (6e) adjacent to the surface (6c) to be joined to the semiconductor element (1), and the concave portion (14 provided on the side surface (6e)) A third metal body (6) comprising:
In the step of arranging the holding jig (21), the holding jig (21) is configured to hold the concave portion (14) of the third metal body (6) by the holding jig (21). The method of manufacturing a semiconductor device according to claim 1, wherein: 前記第１の金属体（３）、第１の接合材（８）、前記半導体素子（１）、第２の接合材（９）、前記第３の金属体（６）、第３の接合材（１０）および前記第２の金属体（５）を順に積層した状態とする工程では、
１つの前記第１の金属体（３）と１つの前記第３の金属体（６）との間に複数の前記半導体素子（１ａ、１ｂ）を配置することを特徴とする請求項１ないし４のいずれか１つに記載の半導体装置の製造方法。 The first metal body (3), the first bonding material (8), the semiconductor element (1), the second bonding material (9), the third metal body (6), and the third bonding material. In the step of laminating (10) and the second metal body (5) in order,
A plurality of the semiconductor elements (1a, 1b) are arranged between one of the first metal bodies (3) and one of the third metal bodies (6). The manufacturing method of the semiconductor device as described in any one of these. 半導体素子（１）と、前記半導体素子（１）の裏面（２）側に設けられ電極と放熱体とを兼ねる第１の金属体（３）と、前記半導体素子（１）の表面（４）側に設けられ電極と放熱体とを兼ねる第２の金属体（５）と、前記半導体素子（１）の表面（４）と前記第２の金属体（５）との間に設けられた第３の金属体（６）と、前記半導体素子（１）、前記第１の金属体（３）、前記第２の金属体（５）、前記第３の金属体（６）を封止するモールド樹脂（７）とを備えた半導体装置において、
前記第３の金属体（６）は、前記第３の金属体（６）を前記半導体素子（１）の前記表面（４）に対して略垂直な方向から見たときに、前記半導体素子（１）と対向している第１の領域（１１）と、前記半導体素子（１）からはみ出ている第２の領域（１２）とを有することを特徴とする半導体装置。 A semiconductor element (1), a first metal body (3) provided on the back surface (2) side of the semiconductor element (1) and serving as an electrode and a radiator, and a surface (4) of the semiconductor element (1) A second metal body (5) provided on the side and serving as both an electrode and a radiator, and a second metal body (5) provided between the surface (4) of the semiconductor element (1) and the second metal body (5). 3 metal body (6), mold for sealing the semiconductor element (1), the first metal body (3), the second metal body (5), and the third metal body (6) In a semiconductor device comprising a resin (7),
When the third metal body (6) is viewed from a direction substantially perpendicular to the surface (4) of the semiconductor element (1), the third metal body (6) 1. A semiconductor device comprising a first region (11) opposite to 1) and a second region (12) protruding from the semiconductor element (1). 前記第３の金属体（６）における前記第２の領域（１２）の厚さは、前記第１の領域（１１）の厚さよりも薄いことを特徴とする請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the thickness of the second region (12) in the third metal body (6) is smaller than the thickness of the first region (11). 前記第２の領域（１２）は、前記第３の金属体（６）の外周の一部に設けられていることを特徴とする請求項６または７に記載の半導体装置。 The semiconductor device according to claim 6 or 7, wherein the second region (12) is provided in a part of an outer periphery of the third metal body (6). 前記第３の金属体（６）は、前記第２の金属体（５）と接合される面（６ｄ）に隣接する側面（６ｅ）と、前記側面（６ｅ）に設けられた凹部（１４）とを有することを特徴とする請求項６に記載の半導体装置。 The third metal body (6) includes a side surface (6e) adjacent to a surface (6d) to be joined to the second metal body (5), and a recess (14) provided on the side surface (6e). The semiconductor device according to claim 6, further comprising: １つの前記第１の金属体（３）と１つの前記第３の金属体（６）との間に複数の前記半導体素子（１ａ、１ｂ）が配置されていることを特徴とする請求項６ないし９のいずれか１つに記載の半導体装置。 The plurality of semiconductor elements (1a, 1b) are arranged between one said first metal body (3) and one said third metal body (6). 10. The semiconductor device according to any one of items 9 to 9.
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