JP2005353715A - Electron beam exposure apparatus and pattern generation method - Google Patents

Abstract

An electron beam exposure apparatus capable of developing a pixel value at high speed even in a drawing pattern having many oblique lines.
The graphic data is provided with attribute data 102 such as external cells, minute cells, power supply wirings, cell wirings, etc. of design data, or accuracy information 103 such as high definition, standard accuracy, and low accuracy. The graphic development unit 230 subdivides the graphic information 101 such as diagonal lines and rectangles into small rectangular information corresponding to the accuracy information 103, and obtains the pixel occupation area corresponding to the electron beam from the rectangular information divided by the image generation unit 240. The output unit 250 outputs the pixel value for each pixel to the blanking control unit. In particular, the development speed of diagonal lines can be improved. Further, since the accuracy attribute of the design data and the characteristics of the electron beam exposure apparatus can be separated, the apparatus can be easily adjusted.
[Selection] Figure 1

Description

  The present invention relates to an electron beam exposure apparatus for writing a semiconductor integrated circuit on a wafer, and more particularly to a conversion method for converting graphic information into pixel values which are control information of an electron beam.

  Conventionally, as disclosed in Patent Document 1, as a high-speed electron beam exposure apparatus, an electron beam is passed through several openings to form an electron beam of an arbitrary shape and exposed to a wafer. Has been put to practical use.

  However, as the miniaturization of processes progresses year by year, the miniaturization of patterns also progresses, and the number of basic figures as exposure units has increased rapidly. For this reason, the amount of processing increases, and a decrease in throughput has become a problem. In particular, in order to accurately draw the hatched portion constituting the figure, it is necessary to decompose it into finer basic figures.

  On the other hand, in recent years, as an epoch-making method for improving the throughput of an electron beam exposure apparatus, as disclosed in Patent Document 2, a multi-beam type electron beam exposure apparatus that performs raster scanning of a plurality of electron beams has been proposed. ing.

  Patent Document 3 shows that a diagonal line or a curved line cannot form a pattern on a wafer with a combination of a conventional rectangle or trapezoid with high accuracy.

JP-A-5-259045

JP 11-195589 A Japanese Patent Laid-Open No. 5-114549

  In the multi-beam method of Patent Document 2, throughput is improved by changing the amount of deflection of the electron beam for each group of figures. However, this throughput is a throughput of exposure time, and time when converting a figure into pixel data is not taken into consideration.

  Due to the increase in the amount of graphic data accompanying the recent miniaturization of processes, the time for converting a graphic into pixel data tends to increase and become longer than the exposure time of the electron beam. In particular, in order to accurately draw oblique lines, it is necessary to convert a figure into pixel data that is an exposure unit, and it is difficult to improve throughput.

  As described above, in the prior art, although the exposure apparatus itself considers processing with high accuracy including oblique lines, it does not consider converting graphics into pixel data at high speed, and there are many oblique lines. When the pattern of the semiconductor integrated circuit is exposed, the processing time increases.

  An object of the present invention is to provide an electron beam exposure apparatus that converts a pattern of a semiconductor integrated circuit with many oblique lines into pixel values at high speed and a pattern generation method thereof.

  In order to achieve the above object, the present invention provides a pattern generation unit that converts graphic data of a semiconductor integrated circuit into a pixel value corresponding to an irradiation amount of an electron beam irradiated on a wafer, and an electron beam according to the pixel value. An electron beam exposure apparatus that controls an irradiation amount and scans the wafer to expose the graphic data onto the wafer surface, wherein the graphic data includes at least a graphic shape and It consists of graphic attributes, and the graphic attributes include information related to accuracy when converting to the pixel value, and the pattern generator corresponds to the graphic attributes when approximating the graphic by dividing it into rectangles. Then, the number of divisions is changed.

  Alternatively, the graphic data includes at least a graphic including a diagonal line and a graphic attribute, and the graphic attribute includes information related to accuracy when converting to the pixel value, and the pattern generation unit includes the diagonal line. When approximating by dividing into vertical lines and horizontal lines, the number of divisions is changed corresponding to the attribute of the figure.

  In addition, the attribute of the graphic is a cell or wiring type or high-definition, standard precision, low-definition information, and the pattern generation unit has an attribute conversion unit that determines the number of divisions according to the attribute of the graphic. Features.

  Further, the attribute conversion unit determines the number of divisions so that the vertical line and horizontal line vertices obtained by dividing the diagonal line have a certain distance or less from the diagonal line. Alternatively, when the pattern generation unit divides the diagonal line into horizontal lines for every integer multiple of pixels, the attribute conversion unit determines the integer multiple based on the division number.

  The pattern generation method of the present invention approximates graphic data including at least a graphic and graphic attributes with a plurality of rectangles, and obtains a pixel value corresponding to the irradiation amount of the electron beam irradiated on the wafer from the graphic data converted into the rectangle. A pattern generation method for an electron beam exposure apparatus, wherein the graphic data includes at least a graphic shape and a graphic attribute, and the graphic attribute implicitly or explicitly indicates an accuracy when converting to the pixel value. When information is included and the figure is divided into a plurality of rectangles for approximation, the number of divisions into the rectangles is changed according to the attributes of the figure, and conversion into the pixel values is performed.

  As described above, according to the present invention, it is possible to control the development accuracy to the pixels developed on the wafer based on the attributes of the cells and wiring patterns of the semiconductor integrated circuit, so that the pixels are developed with high definition regardless of the type of the conventional attribute. The pixel values can be developed at a higher speed than the conventional one.

  In addition, according to the present invention, since the conversion unit that converts the attribute of the cell or wiring pattern of the semiconductor integrated circuit into the development accuracy of the pixel value developed on the wafer, the characteristics of the electron beam exposure apparatus and the semiconductor integrated circuit are provided. Can be treated independently. This makes it possible to handle the cell and wiring characteristics independently by the conversion unit without feeding back the original large-scale design data of the semiconductor integrated circuit, thereby greatly simplifying the adjustment work. .

  First, before describing the embodiments, the basic principle and configuration of the present invention will be described. According to the present invention, in addition to graphic information to be developed, graphic attribute information can be input as pattern input in the electron beam exposure apparatus. That is, in a figure including a diagonal line, the conversion accuracy of the hatched part is changed depending on the attribute. Since the graphic portion that does not require accuracy can be converted into a rough basic graphic (rectangular shape), the number of basic graphic elements can be reduced and the throughput of the apparatus can be improved.

  Hereinafter, the attribute will be described in more detail. In the electron beam exposure system, cells and wiring patterns of semiconductor integrated circuits are given as graphic information, which is turned on or off, or converted into electron beam pixel values that are the irradiation amount or irradiation time, and the entire wafer surface. Is irradiated and exposed to light.

  In the conventional electron beam exposure apparatus, the conversion processing to the pixel value is performed with the same accuracy for any graphic information. However, in actual graphic information, it is necessary to maximize the accuracy of the device, such as in-cell wiring and gate patterns that make up fine cells of the memory, wide-area wiring patterns in semiconductor integrated circuits, and power supplies Some of them may be standard or low precision, such as a pattern of external cells for clock wiring or a relatively large interface.

  Therefore, in addition to graphic information, the attribute information is input, and according to the attribute, high-definition pattern generation for each graphic, pattern generation with standard accuracy, and pattern generation at high speed can be performed if low accuracy is acceptable. I did it.

  The attributes can be given as the type of cell as a library, the type of wiring as a wiring layer, or high definition, standard accuracy, and low accuracy. Furthermore, it is also possible to make adjustments for each apparatus by mapping or converting to actual accuracy such as an error within 1%, within 10%, within 20%, etc. according to the actual process and apparatus.

  In the pattern generation process, a graphic is converted into pixel information based on the input graphic information and attributes or accuracy information obtained by converting the attribute. At this time, based on the accuracy information, conversion using a development method that prioritizes high speed is performed. Specifically, there are a method of dividing diagonal lines into rectangles and setting the number of divisions to a number obtained from the required accuracy, and a method of roughening the coordinate system of the pattern to be generated in accordance with the required accuracy.

  In this way, compared to the case where all graphic information is expanded to pixels with the maximum accuracy, many figures can be converted to pixels at high speed with the required definition, thus reducing the overall processing time. I can do it.

  The attribute information given in addition to the graphic information is converted into accuracy information that can be handled by the electron beam exposure apparatus by a conversion table or conversion program given in advance. As a result, graphic information such as cells and wiring patterns of semiconductor integrated circuits can be created independently of the electron beam exposure apparatus. Adjustment of the electron beam exposure apparatus can be performed by changing a conversion table or conversion program given in advance. It can be done easily.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. FIG. 1 is a block diagram showing an embodiment of a pattern generation unit 200 which is a characteristic part of the electron beam exposure apparatus of the present invention.

  The graphic data 100 of the semiconductor integrated circuit stores graphic information 101 including graphic types and coordinates, and graphic attribute information 102 indicating whether the graphic is a fine cell or a power supply wiring. The graphic data 100 enters the input unit 210 of the pattern generation unit 200, and the attribute information is converted from the attribute information to the accuracy information 103 by the attribute conversion unit 220 and sent to the graphic development unit 230.

  The graphic development unit 230 divides graphic information such as diagonal lines and rectangles into small rectangular information based on the converted accuracy information 103. The graphic information converted into the rectangular information is sent to the pixel generation unit 240, and the pixel corresponding to the electron beam is occupied from the rectangular information obtained by dividing the graphic in order to obtain the output intensity of the electron beam in the electron beam exposure apparatus. The process which calculates | requires an area is performed. The obtained value for each pixel, that is, the irradiation intensity of the electron beam is buffered by the output unit 250 and then output as the pixel value 201 to the next stage.

  The pattern generation unit in FIG. 1 may be in another embodiment. For example, the graphic data 110 is a graphic attribute indicating that the graphic is a fine cell, low-precision power supply wiring, a high-definition graphic, or a standard precision graphic. Is stored in advance. In the pattern generation unit 200, the graphic information 101 and the accuracy information 103 are input and converted into pixel values by the graphic development unit 230 and the pixel generation unit 240. That is, the attribute conversion process is performed on the pattern generation unit 200 shown in FIG. 1 when the graphic data 110 is created in advance.

  Furthermore, the graphic development unit 230 and the pixel generation unit 240 can also calculate data in advance by software and store the pixel values calculated as graphic data in the lookup table. At present, considering the huge amount of graphic data and the amount of processing, these need to be processed by hardware, but can be processed by software in the near future. Even in such a case, the feature of the present invention that processing can be performed at high speed by giving an attribute to a graphic and converting it into accuracy information is not lost.

  Next, the overall configuration of the electron beam exposure apparatus will be described. First, the entire design procedure of the semiconductor integrated circuit will be described with reference to FIG. First, a logic designer creates a specification of a semiconductor integrated circuit to be created, performs a logic design 10 based on the specification, and creates an RTL (Register Transfer Level) 11. The RTL 11 is usually created hierarchically in a high-level hardware description language. The RTL 11 further performs logic synthesis 12 to convert it into a gate level description such as AND, OR, and register, and creates a gate file 13 that is a gate level description.

  Next, the physical arrangement and connection of the actual integrated circuit are performed by the arrangement wiring 14 with the gate file 13 indicating the logical signal connection. For this purpose, basic cell physical information such as AND, OR, and registers is required, and a normal cell library 16 is prepared. The cell library 16 is created by the cell design 17 based on the performance in advance when the process of the semiconductor manufacturing apparatus is determined.

  In the placement and wiring 14, cells are placed on the integrated circuit with reference to the cell library 16 based on the cell types described in the gate file 13 and mutual connection information, and further, mutual wiring is performed. As a result, a graphic file 15 is created.

  The graphic file 15 includes patterns of diffusion layers, oxide films, and contact portions, which are gate patterns of transistors, from higher levels such as external cells for connection to external pins, internal modules, and wiring between modules, as will be described later. It is described hierarchically as graphic information. The types of figures related to the gates of external cells and transistors raised here are treated as implicit attributes in this embodiment. On the other hand, a high-definition processing figure can be defined in the cell library 16 by the cell design 17 as an explicit attribute.

  The graphic file 15 is converted into pixel values by the pattern generation 18, and the pattern is written on the wafer 20 by the multi-electron beam exposure apparatus 19. The graphic file 15 in FIG. 2 is the same as the graphic data 100 in FIG. 1, and the pattern generation 18 corresponds to the pattern generation unit 200 in FIG.

  Next, the relationship between the cell pattern, the integrated circuit, and the wafer will be described with reference to FIG. A plurality of integrated circuits 21 are arranged on the wafer 20. The integrated circuit 21 has a connection portion 22 with an external pin and an internal module 23, which are wired to each other. The internal module is obtained by arranging a large number of basic cells such as the cell 24 and wiring between them.

  In the case of a normal CMOS, it is composed of figures such as a diffusion layer 25, a contact 26, a polysilicon 27, and a metal wiring 28, and is given as a cell definition. In this case, definitions such as cell name: inverter, diffusion layer: rectangular position / coordinate, contact: rectangular position / coordinate are made, and the cell is called by a high-level description and a description for connecting the contacts is made. Further, a hierarchical description is made so as to define it as a module or a macro cell. When this pattern is actually transferred onto the wafer, only the figure of each layer is cut out, developed into pixel values, and exposed to an electron beam.

  Now, how the graphic data of such a semiconductor integrated circuit is exposed on the wafer will be described. FIG. 4 is an embodiment showing the overall configuration of the multi-electron beam exposure apparatus of the present invention.

  The overall control unit 500 instructs the pattern generation unit 200 to import the graphic data 100. The graphic data 100 is successively developed into pixels and passed to the blanking control unit 300. When a certain amount of pixel data is transferred to the blanking control unit 300 in accordance with the pixel development status from the pattern generation unit 200, the overall control unit 500 gives a drawing instruction to the blanking control unit 300.

  The blanking control unit 300 allows the electron beam to pass for a certain period of time through a blanker 430 that controls pixel values of a plurality of electron beams based on the pixel values. An electron beam irradiation unit 400 that performs electron beam exposure includes an electron source 410, an electron lens 420 that deflects the electron source 410 into a plurality of electron beams, and a blanker 430 that passes the electron beam for a certain period of time in response to an instruction from the blanking control unit 300. And an electronic lens 440. Further, a plate 450 having a small hole for preventing the electron beam deflected by the blanker 430 from passing therethrough, an electron lens 460 for focusing the electron beam on the size of the wafer on which the electron beam is drawn, and scanning the electron beam in a minute region of the wafer. It has a deflector 470 that performs deflection for the purpose. The deflector 470 is controlled by the deflection controller 600. Further, a movable wafer stage 490 for scanning an electron beam within a range where the deflector 470 cannot move is provided, and is controlled by the stage controller 700. A wafer 20 on which a pattern is to be written is placed on the wafer stage 490.

  The plurality of electron beams are deflected by the electron lens 420 and reach the blanker 430. The blanker 430 passes through a small hole sandwiched between electrodes connected to a signal from the blanking control unit 300. At that time, if a potential difference is given to the electrodes, the electron beam cannot be moved straight but bends. When this electron beam passes through the electron lens 440, the electron beam that has traveled straight can pass through the hole of the plate 450 having a small hole, but cannot pass the electron beam bent by the blanker. Thereby, a plurality of electron beams can be selectively passed.

  The passed electron beam can move a minute electron beam by the electromagnetic force given to the deflector 470 according to an instruction from the deflection control unit 600. Further, a large movement can be performed by an actuator 710 that moves while detecting the position of the wafer stage 490 according to an instruction from the stage controller 700.

  This is shown in FIG. The wafer 20 is irradiated with a plurality of electron beams 801 and 802 while being controlled by the blanker 430 at the same time. This scans the area 800 on the wafer by the action of the deflection controller 600 and the deflector 470, and executes irradiation of the electron beam in the area. Furthermore, the entire surface of the wafer 20 can be irradiated with an electron beam by largely moving the wafer 20 in accordance with an instruction from the stage controller 700.

  FIG. 6 shows the relationship between the position of the electron beam and the exposure amount. The wafer 20 is irradiated with an exposure distribution 820 as shown in the figure by a single electron beam irradiation. By irradiating with a time corresponding to the value of each pixel at a distance Dx of one pixel, an arbitrary pattern can be drawn on the wafer. A portion of the resist where the sum of the exposure amounts becomes equal to or higher than the photosensitive sensitivity 830 can change the resist, and the resist on the wafer can be removed with a resist remover.

  Next, a method of generating a drawing pattern at high speed based on accuracy information from the graphic data 100 will be described with reference to FIG. FIG. 7A shows the structure of the graphic file 15 that is the result of performing the placement and routing process 14 of the semiconductor integrated circuit. As described above, the graphic file 15 is hierarchically defined, and the chip is composed of external pins, a plurality of modules, and intermodule wiring. An external pin calls an external cell, and a module is defined by a call of a predefined internal cell and its connection.

  These external cells and internal cells are basic cell libraries such as so-called AND, OR, and registers, or combinations thereof. In the lowermost layer, as shown in FIG. 7B, a diffusion layer, an oxide film, polysilicon , Contacts, metal wiring, etc., which are constituted by graphic data corresponding to each layer. Since the actual drawing on the wafer is performed for each layer in the drawing, when inputting to the electron beam exposure apparatus, as shown in FIG. Converted to data. The graphic data developed in each layer has the structure shown in FIG. 7D, and is composed of graphic types such as polygons and polygonal lines, absolute or relative positions, coordinates indicating shapes, cell types, and attributes indicating wiring types. Is done. This attribute includes external cells, large cells for power, standard cells used for internal gates, high-definition cells such as RAM cells, basic wiring such as clock and bus lines, and standard wiring that is wiring inside the module. There are types such as high-definition wiring used in RAM cells. Actually, as shown in FIG. 7E, the definition is divided into three stages of high definition, standard accuracy, and low accuracy.

  Normally, these attributes can be automatically added when converting from the chip to the graphic data for drawing shown in FIG. Further, when defining the chip and library cell of FIGS. 7A and 7B, it is possible to individually set each layer and each figure. In that case, the attribute set individually is given priority over the attribute set by default. For example, although it is an external cell, it can be used when processing with high accuracy.

  Next, a method for converting graphic data into pixel values will be described. First, FIG. 8 is used to show a schematic processing flow, and a specific pixel conversion method is described with reference to FIGS. 9-11. In this conversion method, for example, the pattern generation unit 200 can be configured by a CPU and processed by software without depending on the hardware of FIG.

  First, in step s101 of FIG. 8, graphic data 110 to be converted is input. Next, attribute determination is performed in step s102. If an attribute is specified in the graphic data 110, the attribute is converted to a precision specified in advance in step s104. If the attribute is not specified, it is converted to the default precision specified in advance in step s103.

  In step s105, the graphic data 101 whose attributes are converted to precision is divided into diagonal lines by vertical and horizontal lines according to the number of divisions determined according to the given precision. By this division, the graphic data 101 becomes rectangular data and is converted into pixel data (pixel value) in step s106. The graphic data converted into pixel data is sent to the exposure apparatus and used as the intensity (irradiation time) of the electron beam that is actually irradiated onto the wafer.

  The processing procedure shown here is the same as the processing content of the pattern generation unit 200 in the electron beam exposure apparatus shown in FIG. 1, and is realized by hardware in consideration of realistic processing time at the present time. is there. However, if the performance of the processor and the memory increase in the near future, it becomes possible to perform processing in a realistic time even with software, and the implementation is not limited to hardware.

  Next, a specific method of dividing the diagonal line into vertical and horizontal lines according to the given accuracy in step s105 will be described.

  FIG. 9A shows an example of a figure to be developed, and a rectangle 901 and a trapezoid 902 are defined. The horizontal axis and the vertical axis indicate the definition space of a figure, and in this embodiment, it is defined by a coordinate system having 1 nm as the minimum unit. That is, the rectangle 901 is defined by four points (8, 8), (56, 8), (56, 136), and (8, 136), assuming that the coordinates are represented by (X, Y). The trapezoid 902 is defined by four points (56, 8), (144, 132), (96, 132), and (56, 76).

  Further, in this embodiment, the size of one pixel, that is, the interval between electron beams is 16 nm, and when the figure in FIG. 9A is developed into pixel values, ideally as shown in FIG. A pixel group is obtained. Here, the value of one pixel is given by the area ratio in the pixel area of the figure, and in FIG. 9B, the pixel value that is the ratio is represented by the size of a circle. Actually, the value of one pixel is represented by 8 bits, and the area ratio of the figure to the pixel is represented by a value of 0 to 255.

  In general, the process of obtaining the area occupied by pixels developed from such a figure is known as straight line generation with anti-aliasing. When the occupation area of the rectangle 901 is obtained, 64 is obtained as a pixel value having diagonally (0, 0) and (15, 15) from the coordinates (8, 8) on the lower left side of the lower side. This is because the area having diagonally (8,8) and (15,15) consists of 64 coordinate grid points, and the occupied area ratio is 64/256, which is normalized as 255 8-bit data. To obtain 63.75. More specifically, the number of coordinate grid points can be obtained from a table having coordinates (X, Y) as an input, and 255/256 times the number can be obtained by a table or a simple logic circuit. Thus, the occupied area and pixel value of the rectangle 901 can be easily obtained.

  On the other hand, the occupied area of the trapezoid 902 having diagonal lines can be obtained from a coordinate grid point sequence closest to a straight line by a straight line generation algorithm, and the occupied area can be obtained from the obtained coordinate grid points. However, since it is necessary to calculate a maximum of 16 coordinate grid points in order to obtain a pixel value of one pixel, a very long processing time is required.

  Therefore, in this embodiment, as shown in FIG. 9C, the diagonal line of the trapezoid 902 is converted into a figure composed of a horizontal line and a vertical line like a figure 903 and processed. This method will be referred to as a first oblique line developing method.

  For example, the portion corresponding to the diagonal line on the right side of the figure 903 is divided so that about one vertex is generated at one pixel, that is, 16 coordinate grid points, and is divided into nine horizontal lines and nine vertical lines. It is divided. As a result, similar to the method of using the area occupied by the pixel of the rectangle 901, it can be obtained from the coordinates (X, Y) of the vertex using the table, and the speed can be increased. Naturally, if the number of divisions is larger than the length of the straight line, that is, the length 124 of the long side of the straight line in this case (difference in Y coordinate: 132-8), it becomes slower. However, if the division is performed so that about one vertex is generated per pixel, almost the same result as the calculation result of the ideal pixel value of FIG. 9B is obtained as shown in FIG. 9D. I can do it.

  In the present embodiment, the number of divisions in which the maximum distance between the vertex generated when the straight line is divided and the original straight line is equal to or less than a certain value is obtained and divided. For example, the standard accuracy is 1/2 pixel (8 coordinate lattice), the high definition is 1/4 pixel (4 coordinate lattice), and the low accuracy is 1 pixel (16 coordinate lattice). In fact, the major axis of the lower right side of the trapezoid 902 is 124, the minor axis is 88, and in order to make the maximum error from the straight line when this is divided into m equal to 1/4 pixel, by simple geometric calculation, 8.97 ···, and m becomes 9. The flow of this calculation is shown below.

  The 1/4 pixel is 4 in the coordinate system in the present embodiment. The length of the hypotenuse of the right triangle of the base 124 and the height 88 is the square root of the sum of squares of length and width, and is 152.05. Considering a right triangle that is a point that is a distance of 4 from the hypotenuse and perpendicular to the hypotenuse, the right triangle is similar to the original triangle, so the length of the hypotenuse of the horizontal right triangle is This is 4 × (152.05 / 88), which is 6.91. Considering the distance from the original straight line, the doubled distance is an allowable error, so 13.82 is the maximum length of the divided horizontal lines. By dividing 124 by this, it can be calculated as 8.97. The division number m is an integer larger than the allowable value obtained from the length of the straight line.

  In this embodiment, the pattern generation unit 200 does not sequentially calculate the value of m, but inputs the slope of the straight line, that is, the X coordinate of the start point and end point of the straight line, and the Y coordinate difference divided by m. In this method, the vertex coordinates are obtained sequentially only by addition. As described above, the attribute conversion unit shown in FIG. 1 associates the high-definition, standard accuracy, and low-accuracy, which are attribute information, with a specific criterion for the number of straight lines (the maximum separation distance between the straight line and the vertex). 220 functions.

  In the present embodiment, in order to give a linear coordinate increment in advance, the attribute conversion unit 220 performs a process of halving or doubling the coordinate according to the attribute. In the case of half, since it is divided finely, a straight line can be divided with high definition. When it is doubled, it is divided roughly, so that a straight line can be divided with low definition. In the embodiment that does not have the attribute conversion unit 22, this conversion process is performed when the graphic data is created.

  As described above, according to the first oblique line development method, compared to simply generating a straight line, when a ¼ pixel shift can be tolerated, the processing amount is about one-eighth. Processing is possible. In addition, since the divided vertical and horizontal lines are randomly arranged with respect to the boundary of the pixels, when an electron beam having a size of usually 3 to 4 pixels is exposed, an error of an adjacent pixel is offset. is there.

  Next, as a second oblique line development method, the occupied area of the pixel is obtained from the intersection of the straight line and the lattice line at the boundary of the pixel. FIG. 10 shows a method of expanding a square surrounded by four vertices (16, 32), (144, 48), (144, 128), (16, 96) into pixel values. The upper and lower sides, which are diagonal lines, sequentially obtain pixel boundaries, that is, points where X or Y intersects with vertical and horizontal grid lines such as 16, 32, 48, 64, and generate horizontal lines having the same area as the occupied area. .

  For example, in the diagonal line on the lower side, the Y coordinate intersecting with the grid line of X = 32 is obtained by the inclination × distance + intercept, so in the case of FIG. 9, it is (48−32) / (144-16) · 16 + 32, and Y = 34 It is obtained. Further, when X = 48, Y = 36 is obtained. Therefore, the area of the pixels whose diagonals are (16, 32) and (32, 34) is an intermediate value Y = 33 between the start point Y = 32 and the end point Y = 34 of the Y coordinate of the obtained grid line. The area is the same as when the lower side is (16, 33), (32, 33).

  Thus, by dividing the original straight line into one horizontal line for each pixel, the area in the rectangle and the means for calculating the pixel value can be used, and as shown in FIG. The pixel value can be obtained correctly.

  In the case of a figure with low precision and good attributes, as shown in FIG. 10C, a point that intersects with a straight line is obtained for each grid line for four pixels. As a result, as shown in FIG. 10D, the pixel value to be roughly obtained can be obtained with a small amount of processing.

  In the development of the same lower side, the Y coordinate intersecting with the grid line that is 4 pixels away from the starting point is obtained by (48−32) / (144-16) · (80−16) +32. As in the case of FIG. 10A, the intermediate value between Y = 32 and Y = 40 is Y = 36, and the lower side is the first line segment that divides (16, 36) and (80, 36). Ask.

  Furthermore, a specific method for easily obtaining the intersection between the lattice line at the pixel boundary and an arbitrary straight line will be described with reference to FIG.

  Consider a straight line starting at the vertex 910 in a two-dimensional coordinate space. The coordinates of the start point 910 are (Xs, Ys) and the end point is (Xe, Ye). Here, the outer product S of the vector formed from the vector from the start point to the end point and the arbitrary coordinate point (X, Y) from the start point is expressed as (X-Xs) when Xe-Xs is set to DX and Ye-Ys is set to DY. -DY-DX-(Y-Ys). This outer product S has an absolute value representing the area of a triangle, and the sign indicates the rotation direction of the vector from the start point to the coordinate point (X, Y), indicating whether it is above or below the straight line. ing.

FIG. 11 shows a method for obtaining the intersection of the pixel boundary grid line and the straight line. For example, if the starting point 910 is placed at an arbitrary coordinate point (X, Y), the outer product S is zero. That is, the outer product S of the coordinate points on the straight line is zero. In addition, at the lattice point 911 at the pixel boundary, the outer product S is (16− | Xs | ₁₆ ) · DY + (16− | Ys | ₁₆ ) · DX. Here, | Xs | ₁₆ represents a remainder obtained by dividing Xs by 16, that is, a value of lower 4 bits. If this is a negative value, the coordinate point 911 is on the upper side of the straight line as shown in FIG. Thereafter, the coordinate points 912 and 913 are obtained by adding 16 · DY to the obtained outer product S. Further, the outer product S of the coordinate points 914 and 915 is obtained by subtracting 16 · DX from each of the coordinate points 912 and 913.

  In this way, it is possible to sequentially determine the vertical relationship with respect to a straight line of lattice points at the pixel boundary. That is, since the coordinate point 911 is negative, the existence of the intersection 916 with the grid line of the pixel boundary is known. If the outer product of the coordinate point 911 is negative and the outer product of the coordinate point 912 is positive, the existence of the intersection 917 is present. In the same manner, the existence of the intersections 918 and 919 is known. Actually, it is necessary to obtain the coordinates of the intersection points 916, 917, 918, and 919.

  In the case of intersections with grid lines parallel to the Y axis such as intersections 916, 918, and 919, the cross product is obtained as a value obtained by dividing the outer product S by 16 · DX. For example, since the difference between the outer product S of the coordinate point 912 and the outer product S of the coordinate point 914 is 16 · DX, the outer product S of the coordinate point 914 corresponds to the distance Fy with the intersection 918 as it is. Similarly, in the case of the intersection 917 that intersects the grid line parallel to the X axis, the distance Fx to the intersection 917 can be obtained by dividing the outer product S of the coordinate point 911 by 16 · DY. Here, a division operation is required, and the gate amount and gate delay become a problem when implemented by hardware. However, since the accuracy of the obtained result may be 4 bits in this embodiment, a very simple circuit is required. For example, it can be realized by arranging four stages of adders / subtracters in a pipeline.

  According to the second oblique line development method shown above, the division is performed in one operation as compared to the conventional straight line generation method (particularly famous for Bresenham's straight line generation method) in which points on a straight line are generated in coordinate units. Since the points can be obtained, the straight line can be divided by 1/16 of the processing. In addition, since the dividing point is generated at the pixel boundary, the raster scan type device that generates the pixel for each raster has an effect that the pixel generation process is simplified.

  As described above, according to this embodiment, since the development accuracy of pixels developed on the wafer can be controlled based on the attributes of the cells and wiring patterns of the semiconductor integrated circuit, the pixels are developed with high definition regardless of the type of the conventional attribute. It is possible to develop the pixel values at a higher speed than in the past. In particular, in the case of cells and wiring patterns with many diagonal lines, the performance of the conventional method is one digit (16 times) lower than that of a rectangle, but it is possible to develop pixel values with the same performance as a rectangle. Become.

  In addition, according to this embodiment, since there is a conversion unit that converts the attribute of the semiconductor integrated circuit cell or wiring pattern into the development accuracy of the pixel value developed on the wafer, the characteristics of the electron beam exposure apparatus and the semiconductor integration The circuit characteristics can be handled independently. In other words, design data for semiconductor integrated circuits is assigned and managed with attributes such as high definition, standard accuracy, and low accuracy at the cell, wiring, module, and chip levels. The standard value can be set and adjusted so that, for example, the error is 4 nm or less and the low accuracy is 8 nm or less. As a more specific effect, this makes it possible to handle the cell and wiring characteristics independently by the conversion unit without feeding back the original large-scale design data of the semiconductor integrated circuit. The adjustment work is greatly simplified.

  Further, according to the present embodiment, attributes such as high definition, standard accuracy, and low accuracy can be explicitly set (and not set) in the design data of the layered semiconductor integrated circuit, and the internal cell of the cell or wiring can be set. Because it is implicitly set as a default attribute from attributes such as external cells, intra-cell wiring, and inter-module wiring, it is possible to convert pixel values to cell or wiring units without increasing attribute setting data more than necessary. The deployment accuracy can be controlled.

  In the present embodiment, a method of converting pixel data into a pixel data centered on an oblique line is shown. However, the present invention also reduces the accuracy and increases the speed even when determining the proportion (area) of a graphic such as a rectangle. Can be In the above embodiment, the ratio of the pixels is sequentially obtained from the lower coordinates of the rectangular vertices. However, if low accuracy is acceptable, the lower coordinates of the vertices are ignored and the presence / absence of the pixels is determined. Speed can be increased. This is particularly effective when pattern generation is realized by software, and the method of converting the attribute of a figure, which is a feature of the present invention, into accuracy information and further converting it into a pixel is limited to the case where the figure includes diagonal lines. It goes without saying that it is not done.

The block diagram of the pattern production | generation part of the electron beam exposure apparatus by one Example of this invention. Explanatory drawing which shows the flow from the design of a semiconductor integrated circuit to the completion of a wafer. The cross-sectional enlarged view which shows the relationship between the chip | tip on a wafer, and a cell pattern. 1 is an overall configuration diagram of a multi-electron beam exposure apparatus according to an embodiment of the present invention. Explanatory drawing which shows the exposure procedure of the pixel to a wafer. Explanatory drawing which shows the characteristic of an electron beam, and the state of exposure. 4 is an explanatory diagram showing various data structures of a semiconductor integrated circuit. FIG. The flowchart which shows the process sequence of the pattern generation part by one Example of this invention. Explanatory drawing which shows expansion | deployment to the pixel value by the 1st diagonal line expansion | deployment method. Explanatory drawing which shows expansion | deployment to the pixel value by the 2nd diagonal line expansion | deployment method. Explanatory drawing which shows the detail of the 2nd diagonal line expansion | deployment method.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 20 ... Wafer, 100 ... Graphic data and attribute data, 101 ... Graphic information, 102 ... Attribute information, 103 ... Accuracy information, 200 ... Pattern generation part, 210 ... Input part, 220 ... Attribute conversion part, 230 ... Graphic conversion part, 240 ... pixel generation unit, 250 ... output unit, 300 ... blanking control unit, 400 ... electron beam irradiation unit, 430 ... blanker, 470 ... deflector, 490 ... wafer stage, 500 ... overall control unit, 600 ... deflection control unit , 700 ... Stage controller, 800 ... Deflection range, 830 ... Resist sensitivity.

Claims (7)

A pattern generation unit that converts graphic data of the semiconductor integrated circuit into a pixel value corresponding to the irradiation amount of the electron beam irradiated on the wafer, and controls the irradiation amount of the electron beam according to the pixel value. An electron beam exposure apparatus comprising: an electron beam exposure unit that scans the image data to expose the graphic data on the wafer surface;
The graphic data includes at least a graphic shape and graphic attributes, and the graphic attributes include information related to accuracy when converting to the pixel value,
The electron beam exposure apparatus according to claim 1, wherein when the pattern is approximated by dividing the figure into rectangles, the number of divisions is changed in accordance with the attribute of the figure. A pattern generation unit that converts graphic data of the semiconductor integrated circuit into a pixel value corresponding to the irradiation amount of the electron beam irradiated on the wafer, and controls the irradiation amount of the electron beam according to the pixel value. An electron beam exposure apparatus comprising: an electron beam exposure unit that scans the image data to expose the graphic data on the wafer surface;
The graphic data includes a graphic including at least a diagonal line and a graphic attribute, and the graphic attribute includes information related to accuracy when converting to the pixel value,
The electron beam exposure apparatus according to claim 1, wherein the pattern generation unit changes the number of divisions corresponding to the attribute of the graphic when the diagonal line is approximated by dividing it into a vertical line and a horizontal line. The attribute of the figure is the cell or wiring type or high definition, standard accuracy, low definition information,
The electron beam exposure apparatus according to claim 2, wherein the pattern generation unit includes an attribute conversion unit that determines the number of divisions according to an attribute of the graphic.   4. The electron beam exposure according to claim 3, wherein the attribute conversion unit determines the number of divisions such that a vertex of a vertical line and a horizontal line obtained by dividing the diagonal line is equal to or less than a predetermined distance from the diagonal line. apparatus.   4. The electron beam according to claim 3, wherein when the pattern generation unit divides the diagonal line into horizontal lines every integer multiple of pixels, the attribute conversion unit determines the integer multiple based on the division number. Exposure device. A pattern generation method for an electron beam exposure apparatus that approximates figure data consisting of at least figures and figure attributes by a plurality of rectangles, and obtains pixel values corresponding to the irradiation amount of the electron beam irradiated on the wafer from the figure data converted into rectangles Because
The graphic data includes at least a graphic shape and a graphic attribute, and the graphic attribute includes information that implicitly or explicitly indicates accuracy when converting to the pixel value,
A pattern generation method characterized in that, when the figure is divided into a plurality of rectangles and approximated, the number of divisions into the rectangle is changed according to the attribute of the figure and converted into the pixel value. The pattern generation method according to claim 7, wherein the graphic data includes a graphic including diagonal lines, and the diagonal lines are approximated by dividing them into vertical lines and horizontal lines.

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