JP2005300977A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of performing sufficient charging to respective pixels without increasing electric power consumption even if the on time of switches of a multiplexer circuit is short and maintaining high sharpness at a low cost. <P>SOLUTION: Analog switches ASW are successively turned on by control signals Sca, Seb and Scc in a scanning period when the respective pixels are selected by a scanning signal Sdi to write a video signal Sgi through the respective analog switches and signal lines into pixels selected with the scanning signal. The scanning signals are turned off and all the control signals Sca, Seb and Scc for controlling the respective analog switches in the period when the pixels are not selected by the scanning signals are simultaneously supplied to the respective analog switches to simultaneously turn on all the analog switches. A plurality of the signal lines are simultaneously interconnected through all of the turned on analog switches and the potentials on the signal lines are set at nearly an intermediate potential. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an active matrix liquid crystal display device in which pixels are arranged at intersections of a plurality of scanning lines and a plurality of signal lines.

  As shown in FIG. 6, the active matrix liquid crystal display device includes a pixel display unit 1, a scanning line driving circuit 3, and a signal line driving circuit 5. The pixel display unit 1 includes a thin film transistor (a thin film transistor) at each intersection of a plurality of scanning lines d1, d2,... Dn from the scanning line driving circuit 3 and a plurality of signal lines e1, e2, e3,. TFT) 11, a liquid crystal capacitor 13 constituting a liquid crystal, and an auxiliary capacitor 15. The counter electrodes of the liquid crystal capacitor 13 and the auxiliary capacitor 15 in each pixel unit are connected to the common electrode 6.

  Each scanning line di (i = 1, 2,..., N) from the scanning line driving circuit 3 is connected to the gate of the thin film transistor 11 of each pixel portion of the pixel display unit 1 and is output from the scanning line driving circuit 3. A signal is sequentially supplied to the gate of the thin film transistor 11 of each pixel portion of the pixel display portion 1 through each scanning line d1.

  Each signal line ei (i = 1, 2, 3,...) From the signal line driving circuit 5 is connected to the source of the thin film transistor 11 in each pixel portion of the pixel display portion 1. The signal line drive circuit 5 includes a plurality of drive ICs 9 having a D / A converter function, and outputs of the plurality of drive ICs 9 are respectively connected to a plurality of signal lines ei. The video signal from each driving IC 9 of the signal line driving circuit 5 is supplied to the source of the thin film transistor 11 of each pixel portion of the pixel display unit 1 via each signal line ei, and gated by the scanning signal from the scanning line driving circuit 3. A video signal is supplied from the source of each thin film transistor 11 to the liquid crystal capacitor 13 and the auxiliary capacitor 15, and an analog amplitude voltage of the video signal is charged to the liquid crystal capacitor 13 and the auxiliary capacitor 15.

  In the active matrix type liquid crystal display device configured as described above, the scanning line driving circuit 3 sequentially outputs the scanning signal Sdi of the ON voltage level Vgh as shown in FIG. 7A to each scanning line di. . In this sequential output, for example, when the scanning signal Sdi is output to the i-th scanning line di, the scanning line Sdi is applied to the gate of each thin film transistor 11 of each pixel unit of the pixel display unit 1 connected to this scanning line di. The gates of the thin film transistors 11 connected to the scanning line di are supplied, and the video signals Se1 (R1) and Se2 (as shown in FIGS. 7B to 7D) are output from the driving ICs 9 of the signal line driving circuit 5. G1), Se3 (B1),... Are output to the respective signal lines e1, e2, e3,..., And these video signals are supplied to the liquid crystal capacitors 13 and auxiliary capacitors of the respective pixel portions via the gated thin film transistor 11 sources. 15, the liquid crystal capacitor 13 and the auxiliary capacitor 15 are charged with the analog amplitude voltage of the video signal.

  As shown in FIG. 7A, the scanning signal Sdi becomes the off voltage level Vgi, that is, turns off, and when the scanning for the i-th scanning line di is finished, the gated thin film transistors 11 are turned off, and the liquid crystal capacitance 13 The voltage charged in the auxiliary capacitor 15 is held until the next scanning is performed.

  When the i-th scanning is completed in this way, the scanning signal Sdi + 1 is output to the (i + 1) -th scanning line di + 1, and each thin film transistor 11 connected to the scanning line di + 1 is gated in the same manner and the signal line driving is performed. The video signals Se1 (R1), Se2 (G1), Se3 (B1),... From the respective driving ICs 9 of the circuit 5 are similarly connected to the sources of the gated thin film transistors 11 via the respective signal lines e1, e2, e3,. The analog amplitude voltage of the video signal is charged in the liquid crystal capacitor 13 and the auxiliary capacitor 15 of each pixel portion. Similarly, when the (i + 1) th scanning signal Sdi + 1 is turned off, the gated thin film transistors 11 are turned off, and the voltages charged in the liquid crystal capacitor 13 and the auxiliary capacitor 15 are held until the next scanning is performed.

  Thereafter, the image corresponding to the video signal can be entirely displayed by the pixel display unit 1 by sequentially repeating the same scanning for each scanning line di.

  FIG. 8 shows a plurality of switches 21a, 21b, 21c which are switch means constituting a multiplexer circuit between the driving IC 9 of the signal line driving circuit 5 and the signal line ei in the active matrix type liquid crystal display device shown in FIG. It is a circuit diagram which shows the structure of the liquid crystal display device provided with. In FIG. 8, the configurations of the pixel display unit 1 and the scanning line driving circuit 3 are the same as those shown in FIG.

  Thus, by providing the plurality of switches 21a, 21b, and 21c constituting the multiplexer circuit between the driving IC 9 and the signal line ei, the number of driving ICs 9 in the signal line driving circuit 5 and the output of the driving IC 9 are connected. It is possible to reduce the number of video signals g1,.

  That is, in the liquid crystal display device shown in FIG. 8, three switches 21a and 21b are provided for each video signal line gi (i = 1,...) Connected to the output of the drive IC 9 of the signal line drive circuit 5. 21c and each video signal line gi is connected to the three signal lines ei via the switches 21a, 21b and 21c, so that the drive provided in the signal line drive circuit 5 of FIG. The number of ICs 9 and the number of video signal lines gi are the number of driving ICs 9 provided in the signal line driving circuit 5 of the liquid crystal display device shown in FIG. 6 and the number of video signal lines gi connected to the output of the driving IC 9. The number is reduced to 1/3 of the number, and this enables a significant reduction in size and economy.

  In the liquid crystal display device of FIG. 8 having the multiplexer circuit in this way, the video signal Sgi output from each drive IC 9 of the signal line drive circuit 5 to each video signal line gi is switched from the video signal line gi to the switches 21a, 21b, 21c and the signal line ei are supplied to the pixel display unit 1. In the pixel display unit 1, the video signal Sgi is supplied to the liquid crystal capacitor 13 and the auxiliary capacitor 15 through the source of the thin film transistor 11 of the pixel display unit 1 gated by the scanning signal Sdi from the scanning line driving circuit 3 as described above. The analog amplitude voltage of the video signal Sgi is supplied to the liquid crystal capacitor 13 and the auxiliary capacitor 15.

  More specifically, the operation of the liquid crystal display device shown in FIG. 8 will be described with reference to the timing chart shown in FIG. In the timing chart of FIG. 9, FIG. 9A shows the scanning signal Sdi, and FIGS. 9B, 9C, and 9D show control signals Sca for controlling on / off of the switches 21a, 21b, and 21c, respectively. , Scb, and Scc, FIG. 9E shows the video signal Sgi corresponding to B1, R1, and G1 that are output signals of the driving IC 9, and FIG. 9F shows the potential on the signal line ei corresponding to G1. A waveform Sei is shown. The control signals Sca, Scb, Scc are supplied from control means (not shown).

  In the liquid crystal display device shown in FIG. 8, the i-th scanning signal Sdi as shown in FIG. 9A is output from the scanning line driving circuit 3, and the i-th scanning signal Sdi is output as the i-th scanning line. When supplied to the pixel display unit 1 via di, each thin film transistor 11 connected to the i-th scanning line di is gated by the scanning signal Sdi.

  Thus, when each thin film transistor 11 connected to the i-th scanning line di is gated, the switch 21a is first turned on by the control signal Sca shown first in FIG. 9B. At this time, the video signal Sgi shown in FIG. 9E output from the driving IC 9 of the signal line driving circuit 5 onto the video signal line g1 is output to the signal line e1 via the switch 21a. From e1, the liquid crystal capacitor 13 and the auxiliary capacitor 15 of the corresponding pixel portion are supplied to the liquid crystal capacitor 13 and the auxiliary capacitor 15 through the source of each gated thin film transistor 11, and the liquid crystal capacitor 13 and the auxiliary capacitor 15 are charged with the analog amplitude voltage.

  Next, when the switch 21b is turned on by the control signal Scb shown in FIG. 9C, similarly, the video signal Sgi shown in FIG. 9E is output to the signal line e2 via the switch 21b. From e2, the liquid crystal capacitor 13 and the auxiliary capacitor 15 of the corresponding pixel portion are supplied to the liquid crystal capacitor 13 and the auxiliary capacitor 15 through the source of each gated thin film transistor 11, and the liquid crystal capacitor 13 and the auxiliary capacitor 15 are charged with the analog amplitude voltage.

  Similarly, when the switch 21c is turned on by the control signal Scc shown in FIG. 9 (d), the video signal Sgi passes through the switch 21c to the signal line e3 and has a negative potential waveform Sei as shown in FIG. 9 (f). And the liquid crystal capacitor 13 and the auxiliary capacitor 15 of the corresponding pixel portion are charged from the signal line e3 through the source of each gated thin film transistor 11.

  When the scanning line Sdi is turned off as shown in FIG. 9A and scanning for the i-th scanning line di is completed, the gated thin film transistors 11 are turned off, and the liquid crystal capacitor 13 and the auxiliary capacitor 15 are charged. The voltage is held until the next scan is performed.

  Next, when the (i + 1) th scanning line di + 1 is output from the scanning line driving circuit 3 to the (i + 1) th scanning line di + 1 and each thin film transistor 11 connected to the scanning line di + 1 is gated, the control is performed as described above. Signals Sca, Scb, and Scc are sequentially output, and in response to this, switches 21a, 21b, and 21c are sequentially turned on. In response to this turn-on, signals are output from drive IC 9 onto the video signal line as shown in FIG. The video signal Sgi is sequentially output to the signal lines e1, e2, and e3 through the switches 21a, 21b, and 21c, and the liquid crystal capacitor 13 and the auxiliary capacitor 15 of the corresponding pixel portion are connected through the sources of the gated thin film transistors 11. The analog amplitude voltage is charged to the liquid crystal capacitor 13 and the auxiliary capacitor 15.

  Thereafter, the pixel display unit 1 can display the entire image for the video signal by sequentially repeating the same scanning for each scanning line di.

In FIG. 9, in the black raster display, the voltage of the video signal Sgi that gives the pixel a negative black display level during the period when the control signal Scc is on in the i-th scan is the liquid crystal of the pixel portion. The voltage of the video signal Sgi that charges the capacitor 13 and the auxiliary capacitor 15 and gives a positive black display level to the pixel during the period when the control signal Scc is on is charged in the (i + 1) th scan. The capacitor 13 and the auxiliary capacitor 15 are charged. Further, the polarity of the video signal Sgi to the pixel corresponding to G1 is inverted with respect to the polarity of the video signal Sgi to the pixel for B1 and R1, and the scanning signal Sdi is supplied to the same scanning line di in the next frame. The video signal Sgi output to each signal line ei is reversed in polarity so that the polarity is reversed for each pixel so that the liquid crystal is AC driven, thereby preventing the compositional decomposition of the liquid crystal and extending the operating life. Secured.
Japanese Patent Application No. 2004-40128

  As shown in FIG. 8, in the liquid crystal display device having a multiplexer circuit, the number of drive ICs 9 and the number of video signal lines gi can be reduced, and the size and cost can be reduced. The charging time for the pixels is a short period in which the switches 21a, 21b, and 21c constituting the multiplexer circuit are turned on by the control signals Sca to Scc. Therefore, the analog amplitude voltage of the video signal is changed to the liquid crystal capacitance 13 of each pixel. In addition, there is a problem that it takes a short time to fully charge the auxiliary capacitor 15 and the image quality is likely to deteriorate due to insufficient charging.

  In addition, in order to sufficiently charge the analog amplitude voltage of the video signal to the liquid crystal capacitor 13 and the auxiliary capacitor 15 of each pixel in a short period when the switches 21a, 21b, and 21c are turned on, the output of the drive IC 9 of the signal line drive circuit 5 Therefore, it is necessary to reduce the output resistance of the driving IC 9 and increase the charging current supplied from the driving IC 9 to the liquid crystal capacitor 13 and the auxiliary capacitor 15. There is a problem that the current consumption in the drive IC 9 of the line drive circuit 5 is increased, the power consumption of the entire liquid crystal display device is increased, and the price is increased.

  The present invention has been made in view of the above, and an object of the present invention is to sufficiently charge each pixel without increasing power consumption even when the switch on time of the multiplexer circuit is short. An object of the present invention is to provide a liquid crystal display device capable of maintaining high image quality at a low price.

  In the liquid crystal display device according to the first aspect of the present invention, pixels are arranged at intersections of a plurality of scanning lines and a plurality of signal lines, and video signals from the plurality of signal lines are supplied to each pixel selected by the scanning lines. A pixel display portion that performs display by writing, a drive IC that supplies a video signal via a video signal line, and N (N is an integer of 2 or more) for each video signal line from the drive IC ) Switch means for connecting a signal line selected from the N signal lines to a video signal line connected to the output of the driving IC for each group when each line is made to correspond, and the scanning line The output of the driving IC is controlled to a high impedance state during a period when the pixel is not selected by the scanning signal from the pixel, and the pixel in the next scanning is scanned by a plurality of scanning lines among the N signal lines. Video signal to be written Control means for controlling the switch means so that only signal lines having a polarity different from that of the video signal written to the pixel in the previous scan are mutually connected to the output of the driving IC in the high impedance state. This is the gist.

    According to the present invention, each video signal line from the driving IC that supplies the video signal is connected to the N signal lines via the switch means, and the output of the driving IC is output during a period in which no pixel is selected by the scanning signal. Is controlled to the high impedance state, and the polarity of the video signal is the polarity of the previous scan in the next scan among the N signal lines via the switch means with respect to the output of the drive IC in the high impedance state. Since only different signal lines are interconnected at the same time, the increase in charging time and power consumption due to the same polarity is suppressed by setting the potential of only the signal lines having different polarities to an almost intermediate potential. Charging is performed to compensate for the intermediate potential, charging time can be shortened, charging is eliminated, image quality is not deteriorated due to insufficient charging, power consumption is reduced, and cost can be reduced. Can.

  Hereinafter, the best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described with reference to the drawings.

  FIG. 1 is a timing chart showing an operation sequence of the liquid crystal display device according to the embodiment of the present invention. The circuit configuration of the liquid crystal display device according to the embodiment shown in the figure is the same as the circuit configuration shown in FIG. 8, and a plurality of pixels constituting the pixel display unit 1, the scanning line driving circuit 3, the signal line driving circuit 5, and the multiplexer circuit. The switches 21a, 21b, and 21c are provided, and the operation sequence of the switches 21a, 21b, and 21c and the output impedance of the drive IC 9 constituting the signal line drive circuit 5 are set to high impedance at a predetermined timing in FIG. This is different from the circuit configuration.

  Specifically, as can be seen by comparing the timing chart of this embodiment shown in FIG. 1 with that shown in FIG. 9, in this embodiment, the i-th scanning signal Sdi and the i + 1-th scanning signal in FIG. During a period in which the scanning signal Sdi is not output from the scanning line driving circuit 3 as between the scanning signal Sdi + 1, that is, in a period in which each pixel of the pixel display unit 1 is not selected by the scanning signal Sdi from the scanning line di. As indicated by reference numeral 20, the operation timing of the switches 21a, 21b, 21c is controlled by a control means (not shown) so that the switches 21a, 21b, 21c are simultaneously turned on, and the signal line drive circuit 5 is driven during this same period. The output of the IC 9 is set or controlled by a control means (not shown) so as to be in a high impedance state. The circuit from the video signal line gi connected to the output to a plurality of (three in the present embodiment) signal lines ei via the switches 21a, 21b, and 21c is insulated from the output of the drive IC 9. It is what.

  As a result, a plurality of signal lines ei are simultaneously connected to the output of the driving IC 9 in the high impedance state via the switches 21a, 21b, and 21c, and the plurality of signal lines ei are electrically connected via the switches 21a, 21b, and 21c. Are connected to each other. Accordingly, the plurality of signal lines ei interconnected via the switches 21a, 21b, and 21c are completely insulated from the output of the driving IC 9 and are in a suspended state that is not electrically connected to anywhere. At this time, the charges of different polarities held on the plurality of signal lines ei are neutralized through the interconnection paths via the switches 21a, 21b, 21c, and the plurality of signal lines ei. The upper potential is substantially an intermediate potential of the analog amplitude voltage of the video signal as indicated by reference numeral 24 in FIG.

  Specifically, as illustrated in FIG. 1A, the i-th scanning signal Sdi is output from the scanning line driving circuit 3, and each corresponding pixel of the pixel display unit 1 is output by the i-th scanning signal Sdi. When the switch 21c is turned on as indicated by reference numeral 22 following the switches 21a and 21b as shown in FIG. 1D, the video signal Sgi shown in FIG. And the electric potential on the signal line e3 is charged with the video signal from the driving IC 9 until the electric potential on the signal line e3 becomes the electric potential of the negative black display level of the video signal Sgi as shown in FIG. Further, the negative black display level voltage of the video signal Sgi is supplied from the signal line e3 through the thin film transistor 11 of the corresponding pixel (that is, the pixel selected by the scanning signal Sdi) and the auxiliary voltage 13 and the auxiliary voltage. To charge the amount 15.

  Next, the i-th scanning signal Sdi from the scanning line driving circuit 3 is turned off, and the pixel of the pixel display unit 1 is not selected. As indicated by reference numeral 20, the switches 21a, 21b, When the switch 21c is turned on at the same time, as shown in FIG. 1 (f), the potential on the signal line e3, which is the negative black display level of the video signal Sgi, is turned on by the switches 21a, 21b, 21c. Is neutralized via the interconnection path, and becomes an intermediate potential of the analog amplitude voltage of the video signal as indicated by reference numeral 24 in FIG.

  Next, as shown in FIG. 1A, when the (i + 1) th scanning signal Sdi + 1 is output and the corresponding pixel of the pixel display unit 1 is selected by the (i + 1) th scanning signal Sdi + 1, the control is performed. When the signals Sca, Scb, and Scc are sequentially output, and the switches 21a, 21b, and 21c are sequentially turned on, video signals are sequentially applied to the signal lines connected to the switches 21a, 21b, and 21c. The potential is charged from approximately the intermediate potential to the maximum voltage level of the video signal so as to compensate for the approximately intermediate potential described above. This charging operation will be described in the case of the switch 21c corresponding to the control signal Scc. The potential on the signal line immediately before the switch 21c is turned on is substantially at an intermediate potential as shown by reference numeral 24 in FIG. When a positive black display level voltage of the video signal Sgi is applied to the substantially intermediate potential via the switch 21c, the potential on the signal line is compensated for the substantially intermediate potential in FIG. ), The battery is rapidly charged to a positive black display level voltage in a short time.

  Then, as described above, after the potential on each signal line is charged from approximately the intermediate potential to the maximum voltage level of the video signal, the maximum level voltage of this video signal is further reduced from the signal line to the liquid crystal of the corresponding pixel. The capacity 13 and the auxiliary capacity 15 are charged.

  That is, in the above operation, as indicated by reference numeral 26 in FIG. 1 (f), the potential on the signal line e3 immediately before the video signal Sgi reaches the positive black display level potential is substantially equal to the reference numeral 24. Since the voltage of the positive black display level of the video signal Sgi from the drive IC 9 via the switch 21c is supplied above the intermediate potential so as to compensate for this almost intermediate potential, Conventionally, the time required for charging with the video signal from the drive IC 9 until the potential reaches the potential of the black display level of the positive polarity, as shown by the reference numeral 100 in FIG. Compared with the case where the potential is swung and maintained at a potential deeper than the intermediate potential, the time is significantly shortened.

  Therefore, the positive black display level voltage of the video signal Sgi can sufficiently charge the liquid crystal capacitor 13 and the auxiliary capacitor 15 of the corresponding pixel from the signal line e3 in a short time, resulting in insufficient charging. In addition, the image quality is not deteriorated due to insufficient charging, and the power consumption is not increased, but rather it should be supplied above the intermediate potential so as to supplement the intermediate potential. Therefore, the current consumption in the drive IC 9 of the signal line drive circuit 5 can be reduced. Conversely, in the case of the same current consumption, the number of signal lines that can be driven by the signal line drive circuit 5 can be increased. Lower prices can be achieved.

  In the above embodiment, the case where the number of switches 21a, 21b, and 21c constituting the multiplexer circuit is three and the number of signal lines selected in a time division manner via the switches 21a, 21b, and 21c is three is described. However, the present invention is not limited to this, and it goes without saying that the same effect can be obtained even when two or more arbitrary switches and two or more arbitrary signal lines are used.

  FIG. 2 is a circuit diagram showing a configuration of a plurality of analog switches constituting a part of a multiplexer used in the liquid crystal display device according to the embodiment of the present invention.

  The liquid crystal display device of the embodiment shown in FIG. 2 has one video image instead of a multiplexer circuit in which three switches 21a, 21b, and 21c correspond to one video signal in the liquid crystal display device shown in FIG. 8 is different from the liquid crystal display device shown in FIG. 8 in that a multiplexer circuit having a unit in which two groups of four analog switches ASW1 to ASW4 or ASW5 to ASW8 are associated with the signal Sgi is provided. The configuration and operation of are the same as in FIG.

  In FIG. 2, the video signal Sg1 is connected to the respective sources of the analog switches ASW1 to ASW4, and the signal lines e1 (R1), e2 (G1), e3 (B1), e4 (via the analog switches ASW1 to ASW4, respectively. R2), respectively. Further, the video signal Sg2 is connected to the respective sources of the analog switches ASW5 to 8, and the signal lines e5 (G2), e6 (B2), e7 (R3), e8 (G3) are connected via the analog switches ASW5 to 8 respectively. Are connected to each.

  The analog switches ASW1 and ASW7 are supplied with a control signal ASWU1 at their gates, the analog switches ASW2 and ASW8 are supplied with a control signal ASWU2 at their gates, the analog switches ASW3 and ASW5 are supplied with a control signal ASWU3 at their gates, and the analog switch ASW4 ASW6 is applied with a control signal ASWU4, and each analog switch ASW is turned on when a control signal ASWU is applied to the gate, thereby supplying the video signal Sgi to the signal line ei.

  3 switches the polarity of the video signal Sgi supplied to the signal line ei every two horizontal scanning periods in the liquid crystal display device having the multiplexer circuit configured as shown in FIG. 2, and every two adjacent signal lines ei. In the signal line 4 selection 2H2V inversion driving method in which the video signal Sgi with the polarity reversed is supplied, the order in which the signal line ei is selected by the analog switch ASW and the polarity at that time are 1 to 4 of n frames and n + 1 frames. It is a figure shown with respect to the scanning line of a line.

  In FIG. 3, for example, when the signal lines e1 (R1), e2 (G1), e3 (B1), and e4 (R2) corresponding to the video signal Sg1 in the second row of the n frame are viewed, first, “−1” is obtained. “Signal line e2 (G1), negative polarity” as shown by “2”, “Signal line e4 (R2), positive polarity” as shown by “2”, and “Signal as shown by“ 3 ”third. "Signal line e3 (B1), negative polarity" is sequentially selected as indicated by "line e1 (R1), positive polarity" and "-4" fourth. Looking at the third row of the same frame, first, “signal line e1 (R1), negative polarity”, second “signal line e3 (B1), positive polarity”, third “signal line e4 ( “R2), positive polarity”, “signal line e2 (G1), negative polarity” is selected sequentially.

  In the sequential selection described above, paying attention to the signal lines e1 (R1), e2 (G1), e3 (B1), and e4 (R2), the video signal Sg1 in the second to third rows of the same n frame as described above is used. The polarities on the corresponding signal lines e1 (R1), e2 (G1), e3 (B1), and e4 (R2) are “positive polarity to negative polarity” in the signal line e1 (R1), and in the signal line e2 (G1). “Negative to negative”, signal line e3 (B1) “negative to positive”, and signal line e4 (R2) “positive to positive”. As a result, the polarity of the signal lines e1 (R1) and e3 (B1) is reversed in the second to third rows, and the polarity of the signal lines e2 (G1) and e4 (R2) in the second to third rows. It turns out that it is the same.

  Here, as described with reference to FIG. 1, each driving IC 9 that outputs the video signal Sgi in a period when the scanning signal Sdi from the scanning line driving circuit 3 is turned off and the pixel of the pixel display unit 1 is not selected. 1 is turned on and the analog switches ASW1 to ASW4 are all turned on as indicated by reference numeral 20 in FIG. 1, and the signal lines e1 (R1), e2 (G1), e3 (B1), e4 are turned on. When (R2) is interconnected via the analog switches ASW1 to ASW4, there are two signal lines ei each having a positive polarity and a negative polarity. Therefore, the four signal lines e1 (R1), e2 (G1), e3 The potentials on (B1) and e4 (R2) are substantially intermediate potentials between positive and negative, as in the case indicated by reference numeral 24 in FIG.

  Here, as described above, the polarities on the signal lines e1 (R1), e2 (G1), e3 (B1), and e4 (R2) corresponding to the video signal Sg1 in the second to third rows of the n frame are as follows. In the case of inversion as in the signal lines e1 (R1) and e3 (B1), as described above, the analog switches ASW1 to ASW1 are turned on and the potentials on the signal lines e1 (R1) and e3 (B1) are set. Although it is effective to set the potential to an almost intermediate potential, when all the analog switches ASW1 to ASW4 are turned on when the signal lines e2 (G1) and e4 (R2) are the same without being inverted, the signal line e2 Since the potential on (G1) and e4 (R2) is once shifted to the opposite polarity side and the video signal of the same polarity is written in the next frame, the operation in this case increases the charging time and consumes To increase power That.

  Therefore, in the present embodiment, in order to lengthen the charging time and eliminate the troublesome operation that increases the power consumption, the analog switch ASW connected to the same signal line without reversing the polarity. Does not turn on during the period when the pixel of the pixel display unit 1 is not selected, and turns on only the analog switch ASW connected to the signal line whose polarity is inverted while the pixel of the pixel display unit 1 is not selected. As in the embodiment of FIG. 1 on the signal line where the polarity is inverted, the control means (not shown) controls the voltage so that it is almost at the intermediate potential, shortens the charging time for the next video signal, and writes the video signal to the pixel. It is stabilized.

  FIG. 4 is a timing chart showing the operation of the analog switches ASW1 to ASW4 in the second row of the n frame in FIG. The analog switches ASW1 to ASW1 are firstly arranged according to the selection order “3, −1, −4, 2” shown with the polarity in the second row of the n frame in FIG. As a result, ASW2 is turned on, whereby a negative video signal is supplied to the pixel via the analog switch ASW2 and the signal line e2, and then the analog switch ASW4 is turned on secondly as indicated by reference numeral 402. A positive video signal is supplied to the pixel via the switch ASW4 and the signal line e4, and then the analog switch ASW1 is turned on thirdly as indicated by reference numeral 403, whereby the analog switch ASW1 and the signal line e1 are passed. Thus, a positive video signal is supplied to the pixel, and the analog switch ASW3 Becomes down, thereby the analog switch ASW3, the negative polarity of the video signal through the signal line e3 is supplied to the pixel.

  Next, in the period when the scanning signal is turned off and each pixel of the pixel display unit 1 is not selected, as indicated by reference numerals 405 and 406, the analog switch ASW1 connected to the signal line whose polarity is inverted next, 3 is turned on, and the potential on the signal lines e1 and 3 is set to an almost intermediate potential via the analog switches ASW1 and 3 interconnected by this turning on.

  FIG. 5 is a timing chart showing the operation of the analog switches ASW1 to ASW1 in the third row of the n frame in FIG. The analog switches ASW1 to ASW1-4 are indicated by reference numerals 501, 502, 503, and 504 in FIG. 5 according to the selection order “−1, −4, 2, 3” shown together with the polarity of the third row of the n frame in FIG. First, the analog switch ASW1 is turned on. Second, the analog switch ASW3 is turned on. Third, the analog switch ASW4 is turned on. Finally, the analog switch ASW2 is turned on.

  Then, in a period in which the scanning signal is turned off and each pixel of the pixel display unit 1 is not selected, as indicated by reference numerals 505 and 506, the analog switches ASW2 and 4 connected to the signal line whose polarity is inverted next. Only on, and the potential on the signal lines e2 and 4 is set to a substantially intermediate potential via the analog switches ASW2 and 4 interconnected by this on.

  In the above embodiment, four signal lines are associated with each one video signal, the polarity of the video signal supplied to the signal line is switched every two horizontal scanning periods, and adjacent signal lines are switched. The signal line 4 selection 2H2V inversion driving method is described in which the video signal having the polarity inverted every two lines is supplied, but the present invention is not limited to this.

FIG. 5 is a timing chart showing an operation sequence of the liquid crystal display device according to the embodiment of the present invention. It is a circuit diagram which shows the circuit structure of the several analog switch which comprises some multiplexers used for the liquid crystal display device concerning embodiment of this invention. 2 is a diagram showing the selection order of signal lines by the analog switch ASW and the polarity at that time for 1 to 4 scanning lines of n frames and n + 1 frames in the signal line 4 selection 2H2V inversion driving method in the multiplexer circuit having the configuration shown in FIG. It is. FIG. 4 is a timing chart showing operations of analog switches ASW1 to ASW1 in the second row of the n frame in FIG. 3. FIG. 4 is a timing chart showing operations of analog switches ASW1 to ASW4 in the third row of the n frame in FIG. 3. It is a circuit diagram showing a configuration of an active matrix type liquid crystal display device. FIG. 7 is a timing chart showing an operation of the liquid crystal display device shown in FIG. 6. It is a circuit diagram which shows the structure of the active matrix type liquid crystal display device provided with the some switch which comprises a multiplexer circuit. FIG. 9 is a timing chart showing an operation of the liquid crystal display device shown in FIG. 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pixel display part 3 Scan line drive circuit 5 Signal line drive circuit 9 Drive IC
DESCRIPTION OF SYMBOLS 11 Thin-film transistor 13 Liquid crystal capacity 15 Auxiliary capacity 21a, 21b, 21c Switch ASW1-8 Analog switch

Claims (1)

A pixel display unit that performs display by writing a video signal from the plurality of signal lines to each pixel selected by the scanning line, in which pixels are arranged at each intersection of the plurality of scanning lines and the plurality of signal lines;
A driving IC for supplying a video signal via a video signal line;
A signal selected from the N signal lines for each group when the video signal lines from the driving IC correspond to N (N is an integer of 2 or more) signal lines. Switch means for connecting a line to a video signal line connected to the output of the drive IC;
During a period in which no pixel is selected by the scanning signal from the scanning line, the output of the driving IC is controlled to a high impedance state, and the next scanning is performed by scanning with a plurality of scanning lines among the N signal lines. The switch means so that only the signal lines whose polarity of the video signal to be written to the pixel is different from the polarity of the video signal written to the pixel in the previous scan are simultaneously connected to the output of the high impedance state driving IC. And a control means for controlling the liquid crystal display device.

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