JP2005303418A - Diplexer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low cost diplexer with excellent productivity and a low profile wherein coupling between a high pass filter side and a low pass filter side is eliminated so as to enhance isolation between ports. <P>SOLUTION: In the diplexer, since a low frequency trap circuit 4, a high frequency trap circuit 7, capacitive elements 6b, 9b of a high pass filter 6 and a low pass filter 9 are formed on the front side of a multilayer circuit board 20, and inductance elements 6a, 9a of the high pass filter 6 and the low pass filter 9 are formed to an inner layer of the multilayer circuit board, the front side of the multilayer circuit board 20 can effectively be utilized and the number of layers of the multilayer circuit board 20 can be decreased so as to attain excellent productivity, a low cost and a low profile. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a diplexer used in a mobile communication device.

FIG. 7 is a circuit diagram of a conventional diplexer. FIG. 8 is an exploded perspective view showing the configuration of the conventional diplexer. Next, the circuit of the conventional diplexer will be described with reference to FIG. 1 inductor L1 and first capacitors C11 and C12, which are connected between the first port P1 and the second port P2.
The high-pass filter HPF includes a second inductor inductor L2 and second capacitors C21 to C23, and is connected between the second port P2 and the third port P3.

Next, the configuration of the conventional diplexer will be described with reference to FIG. 8. Capacitor electrodes Cp51 and Cp52, capacitor electrodes Cp53 and Cp54, capacitors on the upper surfaces of the second, third and sixth sheet layers 512, 513 and 516 Electrodes Cp55 and Cp56 are formed, respectively.
Stripline electrodes St51 and St52 are formed on the upper surface of the fourth sheet layer 514.
A ground electrode Gp51 and a ground electrode Gp52 are formed on the top surfaces of the fifth and seventh sheet layers 515 and 517, respectively.
In addition, a via-hole electrode Vh5 penetrating each of the sheet layers 512 to 515 is formed on the second to fifth sheet layers 512 to 515.

The first to seventh sheet layers 511 to 517 are stacked and integrally sintered to form the multilayer substrate 51.
The stripline electrode St51 and the capacitor electrodes Cp51, Cp53, and Cp55, and the stripline electrode St52 and the capacitor electrodes Cp54 and Cp56 are connected to each other through the via-hole electrode Vh5 inside the multilayer substrate 51. In addition, the side and front and back surfaces of the multilayer substrate 51 are electrically connected to the capacitor electrode Cp51, and are electrically connected to the external terminals T51 and T52 serving as the first and second ports P1 and P2 and the capacitor electrode Cp52. Then, the external terminal T53 that becomes the third port P3 and the external terminal T54 that is electrically connected to the ground electrodes Gp51 and Gp52 and becomes the ground terminal are formed.

Then, the first and second inductors L1 and L2 are formed by the stripline electrodes St51 and St52, respectively.
The capacitor electrodes Cp51 and Cp53 form the first capacitor C11, the capacitor electrode cp55 and the ground electrodes Gp51 and Gp52 form the first capacitor C12.
Further, the capacitor electrode Cp51, Cp54 forms the second capacitor C21, the capacitor electrode Cp52, Cp54 forms the second capacitor c22, and the capacitor electrode Cp56 and the ground electrode Gp51, Gp52 form the second capacitor c23 (for example, patents) Reference 1).

Japanese Patent Laid-Open No. 2000-349581 (FIGS. 6 and 7)

  In the conventional diplexer, on the surface of the multilayer substrate 51, external terminals T51 and T52 that become the first and second ports P1 and P2, an external terminal T53 that becomes the third port P3, and an external terminal that becomes the ground terminal Since T54 is formed and inductors and capacitors are formed in the inner layer of the multilayer substrate 51, the effectiveness of the surface of the multilayer substrate 51 is poor, and the number of multilayer substrates 51 is increased. There is a problem that the property is poor, the cost is increased, and the thickness is increased.

  The first inductor L1 constituting the low-pass filter LPF and the second inductor L2 constituting the high-pass filter HPF are formed by the stripline electrode St51 and the stripline St52, respectively. These striplines St51, St52 Are formed adjacent to each other on the fourth sheet layer 514, there is a problem that they are coupled to each other and the isolation between the first port P1 and the third port P3 is lowered.

  An object of the present invention is to provide a diplexer that is highly productive, inexpensive, thin, and has improved isolation between ports by eliminating coupling between the high-pass filter side and the low-pass filter side. .

  As a first solving means for solving the above-mentioned problem, a low-pass trap circuit for attenuating a low-frequency band below a predetermined frequency and a high-pass filter connected in series to the low-pass trap circuit, A high-pass filter section interposed between the terminal and the first input / output terminal, a high-frequency trap circuit for attenuating the high-frequency band below the predetermined frequency, and the high-frequency trap circuit connected in series A low-pass filter comprising a low-pass filter portion interposed between a common terminal and a second input / output terminal, the high-pass filter portion, and a multilayer circuit board forming the low-pass filter portion, Each of the high-pass filter and the low-pass filter has an inductance element and a capacitance element, and on the surface of the multilayer circuit board, the low-pass trap circuit, A frequency trap circuit, thereby forming the high-pass filter and the capacitive element of the low-pass filter, the inner layer of the multilayer circuit board, and a configuration in which the formation of the high-pass filter and the inductance element of the low-pass filter.

  As a second solution, on the surface of the multilayer circuit board, a capacitive element of the low-frequency trap circuit and a capacitive element of the high-frequency trap circuit are arranged in parallel with a gap therebetween, and the low-frequency trap The inductance element of the circuit and the inductance element of the high-frequency trap circuit are arranged to be spaced apart from each other on both sides of the area where the capacitive element is formed.

  As a third solution, the inductance element of the high-pass filter formed in the inner layer of the multilayer circuit board is disposed to face the low-frequency trap circuit formed on the surface of the multilayer circuit board. In addition, the inductance element of the low-pass filter formed in the inner layer of the multilayer circuit board is arranged to face the high-frequency trap circuit formed on the surface of the multilayer circuit board.

  As a fourth solution, a plurality of the low-frequency trap circuits are provided corresponding to the plurality of low-frequency bands in different bands, and the high-frequency trap circuit is a plurality of the high-frequency frequencies in different bands. A plurality of low-frequency trap circuits corresponding to the low-frequency band close to the predetermined frequency side among the plurality of low-frequency trap circuits are disposed on the common terminal side, In the high frequency trap circuit, a high frequency trap circuit corresponding to the high frequency band close to the predetermined frequency side is arranged on the common terminal side.

  Further, as a fifth solving means, the capacitance element and the inductance element of each of the low-frequency trap circuit and the high-frequency trap circuit formed on the surface of the multilayer circuit board, and the surface of the multilayer circuit board Each of the capacitive elements of the formed high-pass filter and the low-pass filter is formed of a thin film or a thick film, and the high-pass filter and the low-pass filter formed in an inner layer of the multilayer circuit board. The inductance element was formed by a thick film.

The diplexer according to the present invention includes a low-pass trap circuit that attenuates a low-frequency band below a predetermined frequency and a high-pass filter connected in series to the low-pass trap circuit, and includes a common terminal and a first input / output terminal. A high-pass filter section interposed between the high-frequency filter section, a high-frequency trap circuit that attenuates a high-frequency band below a predetermined frequency, and a low-pass filter connected in series to the high-frequency trap circuit. A low-pass filter section interposed between the two input / output terminals, a high-pass filter section, and a multilayer circuit board that forms the low-pass filter section. The high-pass filter and the low-pass filter include an inductance element and a capacitive element, respectively. On the surface of the multilayer circuit board, each of a low-pass trap circuit, a high-pass trap circuit, a high-pass filter, and a low-pass filter is provided. To form the element, the inner layer of the multilayer circuit board, and a configuration of forming the respective inductance elements of the high-pass and low-pass filters.
That is, the low-pass trap circuit, the high-pass trap circuit, the high-pass filter and the low-pass filter are formed on the surface of the multilayer circuit board, and the high-pass filter and the low-pass filter are formed on the inner layer of the multilayer circuit board. Since each inductance element is formed, the surface of the multilayer circuit board can be used effectively, the number of multilayer circuit boards can be reduced, the productivity is good, the cost is low, and a thin one is obtained.

  In addition, on the surface of the multilayer circuit board, the capacitive element of the low-frequency trap circuit and the capacitive element of the high-frequency trap circuit are arranged in parallel with each other, and the inductance element of the low-frequency trap circuit and the inductance of the high-frequency trap circuit are arranged. Since the elements are spaced apart from each other on both sides of the area where the capacitive element is formed, the inductance elements constituting the high-pass filter portion and the inductance elements constituting the low-pass filter portion are separated from each other. Therefore, it becomes difficult to couple with each other, and the mutual isolation between the first input / output terminal and the second input / output terminal is improved.

  The inductance element of the high-pass filter formed on the inner layer of the multilayer circuit board is disposed opposite to the low-frequency trap circuit formed on the surface of the multilayer circuit board and formed on the inner layer of the multilayer circuit board. Since the inductance element of the low-pass filter is disposed opposite to the high-frequency trap circuit formed on the surface of the multilayer circuit board, it has a good space factor and can be reduced in size and thickness.

  A plurality of low-frequency trap circuits are provided corresponding to a plurality of low-frequency bands in different bands, and a plurality of high-frequency trap circuits are provided corresponding to a plurality of high-frequency bands in different bands. A low frequency trap circuit corresponding to a low frequency band close to a predetermined frequency side of the low frequency trap circuit is arranged on the common terminal side, and a high frequency band close to the predetermined frequency side among a plurality of high frequency trap circuits. Since the high-frequency trap circuit corresponding to is arranged on the common terminal side, the pass characteristics of the high-pass filter portion and the low-pass filter portion are improved, and the mutual isolation is improved.

  Also, the capacitive elements and inductance elements of the low-frequency trap circuit and high-frequency trap circuit formed on the surface of the multilayer circuit board, and the capacitive elements of the high-pass filter and low-pass filter formed on the surface of the multilayer circuit board Is formed of a thin film or a thick film, and the inductance elements of the high-pass filter and the low-pass filter formed in the inner layer of the multilayer circuit board are formed of the thick film, so that they are thin and can be reduced in size.

  FIG. 1 is a circuit diagram showing an embodiment of a diplexer of the present invention, FIG. 2 is a transmission characteristic diagram of the diplexer of the present invention, and FIG. 3 is a multilayer circuit according to the diplexer of the present invention. FIG. 4 is a top view showing the pattern of the surface of the substrate, FIG. 4 is related to the diplexer of the present invention, and is a top view showing the pattern of the second inner surface of the multilayer circuit board. FIG. FIG. 6 is a bottom view showing the pattern of the bottom surface of the third layer of the multilayer circuit board according to the diplexer of the present invention.

  Next, the circuit configuration of the diplexer according to the present invention will be described with reference to FIG. 1. A predetermined frequency (eg, 2.2 GHz) is provided between the common terminal 1 and the first input / output terminal 2 that are input terminals for antenna connection. A higher frequency band than the demultiplexing frequency), for example, a signal in a transmission / reception frequency band (bandwidth is 2.4 GHz to 2.5 GHz) of a Bluetooth (abbreviated as BT) (registered trademark of Nokia, etc.) system; The wireless LAN system transmits / receives a signal in a transmission / reception frequency band (bandwidth: 4.9 GHz to 6.0 GHz), and the frequency between the common terminal 1 and the second input / output terminal 3 is lower than a predetermined frequency. Side frequency band, for example, a signal in a GSM system transmission / reception frequency band (band is 806 MHz to 960 MHz), a DCS system and a PCS system transmission / reception frequency band (band is 1710) Transmitting a signal Hz~1990MHz).

  A high pass filter unit 10 is provided between the common terminal 1 and the first input / output terminal 2, and a low pass filter unit 11 is provided between the common terminal 1 and the second input / output terminal 3.

The high-pass filter unit 10 includes two low-frequency trap circuits 4 and 5 and a high-pass filter 6 that are inserted in series.
The first low-frequency trap circuit 4 is composed of a parallel resonant circuit of an inductance element 4a and a capacitive element 4b, and the resonant frequency is selected, for example, in the vicinity of 1900 MHz to attenuate the transmission / reception frequency bands of the DCS system and the PCS system. .
The second low-frequency trap circuit 5 is also composed of a parallel resonant circuit of an inductance element 5a and a capacitive element 5b, and the resonant frequency is selected, for example, in the vicinity of 920 MHz to attenuate the transmission / reception frequency band of the GSM system.

  The first low-frequency trap circuit 4 is disposed on the common terminal 1 side, the high-pass filter 6 is disposed on the first input / output terminal 2 side, and the second low-frequency trap circuit 5 is disposed on the first low-frequency trap circuit. It is inserted between the circuit 4 and the high pass filter 6.

  The high-pass filter 6 has a half-section high-pass filter, the inductance element 6a constituting this is connected between the output terminal of the second low-frequency trap circuit 5 and the ground, and the capacitive element 6b is the second low-frequency filter. It is connected between the output terminal of the trap circuit and the first input / output terminal 2.

The low-pass filter unit 11 includes two high-frequency trap circuits 7 and 8 and a low-pass filter 9 inserted in series. The first high-frequency trap circuit 7 is composed of a parallel resonant circuit of an inductance element 7a and a capacitive element 7b, and the resonance frequency thereof is selected, for example, in the vicinity of 2.45 GHz, and is a Bluetooth (registered trademark of Nokia Corporation) system. The transmission / reception frequency band is attenuated.
The second high-frequency trap circuit 8 is also composed of a parallel resonance circuit of an inductance element 8a and a capacitance element 8b, and the resonance frequency is selected, for example, in the vicinity of 5.5 GHz to attenuate the transmission / reception frequency band of the wireless LAN system.

  The first high-frequency trap circuit 7 is disposed on the common terminal 1 side, the low-pass filter 9 is disposed on the second input / output terminal 3 side, and the second high-frequency trap circuit 8 is disposed on the first high-frequency trap circuit. It is inserted between the circuit 7 and the low-pass filter 9.

  The low-pass filter 9 has a half-section low-pass filter, and the inductance element 9a constituting the low-pass filter 9 is connected between the output terminal of the second high-frequency trap circuit 8 and the second input / output terminal 3, and the capacitive element 9b. Is connected between the output terminal of the second high-frequency trap circuit and the ground.

  In the above configuration, the first low frequency trap circuit 4 (1900 MHz), the first high frequency, and the wrap circuit 7 (2.45 GHz) close to the predetermined frequency are disposed on the common terminal 1 side. The isolation between the input / output terminal 2 and the second input / output terminal 3 is improved.

The transmission characteristics between the common terminal 1 and the first input / output terminal 2 and the transmission characteristics between the common terminal 1 and the second input / output terminal 3 in the above configuration are as shown in FIGS. Become.
Frequency points 1 to 4 in FIG. 2 indicate the positions of the center frequencies of the GSM system transmission / reception frequency band, the DCS system and PCS system transmission / reception frequency bands, the Bluetooth system transmission / reception frequency band, and the wireless LAN system transmission / reception frequency band, respectively.

The attenuation poles A1 and A2 in the transmission characteristic A are due to the first low-frequency trap circuit 4 and the second low-frequency trap circuit 5, respectively. At the frequencies of the attenuation poles A1 and A2, signals in the transmission / reception frequency band of the GSM system and the transmission / reception frequency band of the DCS system / PCS system input to the common terminal 1 are transmitted by the first and second low-frequency trap circuits 4 and 5. Since these signals are reflected, those signals are efficiently output to the second input / output terminal 3.
Therefore, as shown in the transmission characteristic B, the attenuation amount is extremely small at the frequency point 1 and the frequency point 2.
Also, the transmission / reception frequency band signal of the Bluetooth system and the transmission / reception frequency band signal of the wireless LAN system are not disturbed by the transmission / reception frequency band signal of the GSM system and the transmission / reception frequency band signal of the DCS system / PCS system.

The attenuation poles B1 and B2 in the transmission characteristic B are due to the first high-frequency trap circuit 7 and the second high-frequency trap circuit 8, respectively.
At the frequencies of the attenuation poles B1 and B2, signals in the transmission / reception frequency band of the Bluetooth system and the transmission / reception frequency band of the wireless LAN system input to the common terminal 1 are reflected by the first and second high-frequency trap circuits 7 and 8. Therefore, those signals are efficiently output to the first input / output terminal 2.
Therefore, as shown in the transmission characteristic A, the attenuation amount becomes extremely small at the frequency point 3 and the frequency point 4.
Further, the signal in the transmission / reception frequency band of the GSM system and the signal in the transmission / reception frequency band of the DCS system / PCS system are not disturbed by the signal in the transmission / reception frequency band of the Bluetooth system and the signal in the transmission / reception frequency band of the wireless LAN system.

The attenuation pole A3 in the transmission characteristic A is due to series resonance by the first high-frequency trap circuit 7, the second high-frequency trap circuit 8, and the capacitive element 9b in the low-pass filter 9, and this is the attenuation pole B1. Appears at a frequency between B2.
Therefore, an unnecessary signal existing between the transmission / reception frequency band of the Bluetooth system and the transmission / reception frequency band of the wireless LAN system is attenuated, so that interference caused by this signal is reduced.

Similarly, the attenuation pole B3 in the transmission characteristic B is due to series resonance by the inductance element 6a in the first low-frequency trap circuit 4, the second low-frequency trap circuit 5, and the high-pass filter 6, and this is the attenuation pole A1. And appear at a frequency between A2.
Therefore, since unnecessary signals existing between the transmission / reception frequency band of the GSM system and the transmission / reception frequency band of the DCS system / PCS system are attenuated, the interference caused by this signal is reduced.

The diplexer having the above circuit configuration is formed on a rectangular multilayer circuit board 20 made of a plurality of laminated plates.
The multilayer circuit board 20 is made of a material such as low-temperature fired ceramic (LTCC), and is formed of three layers of laminates 20a, 20b, and 20c. FIG. 3 is a pattern diagram formed on the upper surface of the first layer of laminate 20a. The strip line 21 constitutes the inductance element 4a of FIG. 1, and the electrode 21a on one end side and the electrode 21b on the other end side overlap in the vertical direction, and between these electrodes 21a and 21b. Is provided with a dielectric Z made of an insulating material.
Accordingly, the capacitive element 4b of FIG. 1 is constituted by the two electrodes 21a and 21b and the dielectric Z between them.

Further, the strip line 22 constitutes the inductance element 7a of FIG. 1, and the electrode 22a on one end side and the electrode 22b on the other end side overlap in the vertical direction, and between these electrodes 22a and 22b. A dielectric Z made of an insulating material is provided.
Accordingly, the capacitive element 7b of FIG. 1 is configured by the two electrodes 22a and 22b and the dielectric Z between them.
The strip lines 21 and 22 are connected to each other at one end, the electrode 21a at one end of the strip line 21 is connected to the electrode 22a at one end of the strip line 22, and a via hole 23a is provided in the vicinity thereof. It has been.

  Then, the electrodes 21a and 21b of the strip line 21 and the electrodes 22a and 22b of the strip line 22 are arranged in parallel with a distance from each other, and the strip line 21 is disposed on both sides of the region with the juxtaposed region therebetween. And the strip line 22 are arranged in a separated state.

The strip line 24 constitutes the inductance element 5a of FIG. 1, and the electrode 24a on one end side thereof is connected to the electrode 21b on the other end side of the strip line 21 and is vertically connected to the electrode 24b on the other end side. A dielectric Z made of an insulating material is provided between the electrodes 24a and 24b.
Accordingly, the capacitive element 5b of FIG. 1 is constituted by the two electrodes 24a and 24b and the dielectric Z between them.
The strip line 24 is formed in a spiral shape, and the other end side of the strip line 24 crossing the spiral portion is insulated from the spiral portion by a dielectric Z made of an insulating material. .

The strip line 25 constitutes the inductance element 8a of FIG. 1, and the electrode 25a on one end side thereof is connected to the electrode 22b on the other end side of the strip line 22 and is vertically connected to the electrode 25b on the other end side. A dielectric Z made of an insulating material is provided between the electrodes 25a and 25b.
Therefore, the capacitive element 8b of FIG. 1 is configured by the two electrodes 25a and 25b and the dielectric Z between them.

  Then, the electrodes 24a and 24b of the strip line 24 and the electrodes 25a and 25b of the strip line 25 are arranged in parallel with a distance from each other, and the strip line 24 is provided on both sides of the juxtaposed region. And the strip line 25 are disposed in a separated state.

  Further, the electrode 24c on the other end side of the strip line 24 is provided with an electrode 26a on one end side of the conductive line 26 so as to overlap in the vertical direction with the dielectric Z interposed therebetween. 1 and the electrode 26b on the other end side of the conductive line 26 is provided with an electrode 27a on one end side of the conductive line 27 so as to overlap in the vertical direction with the dielectric Z interposed therebetween. Another of 6b is provided.

Therefore, the capacitive element 6a of FIG. 1 is configured by a series connection of a capacitance formed between the electrode 24c and the electrode 26a and a capacitance formed between the electrode 26b and the electrode 27a.
A via hole 29 a is provided on the other end side of the strip line 24, and a via hole 30 a is provided on the other end side of the conductive line 27.

Further, an electrode 31 is provided on the electrode 25c on one end side of the strip line 25 so as to overlap in the vertical direction with the dielectric Z interposed therebetween, and as a result, the capacitive element 9b of FIG. 1 is configured.
The electrode 31 is provided with a via hole 31 a, and a via hole 32 a is provided on one end side of the strip line 25.

As is apparent from the above configuration, the electrodes 21a / 21b, 24a / 24b, 24c / 26a, and the electrodes 22a / 22b, 25a / 25a constituting the capacitive elements 4b to 9b are provided on the center side of the multilayer circuit board 20. 25b and 25c / 31 are arranged in two rows, and the strip lines 21 and 24 and the strip lines 22 and 25 are arranged on both sides of the electrodes so as to be separated from each other and arranged side by side. Arranged in rows.
Therefore, the strip lines 21 and 24 constituting the high-pass filter unit 10 and the strip lines 22 and 25 constituting the low-pass filter unit 11 are separated from each other, so that it is difficult to couple with each other. Mutual isolation between the two input / output terminals 3 is improved.

  The capacitive elements 4b to 9b and the strip lines 21, 22, 24, 25 formed on the surface of the multilayer circuit board 20 are formed by a thin film technique such as vapor deposition or sputtering, or a thick film technique such as printing or coating. Has been.

  When these are formed by a thin film, the strip line and the electrode are made of copper, aluminum, etc., and the dielectric is made of silicon nitride, barium titanate, lead titanate, etc. When these are formed by a thick film, the strip line and electrode are made of silver paste or silver-palladium paste, and the dielectric is made of silicon nitride, barium titanate, lead titanate, or the like. used.

FIG. 4 shows an inner layer pattern provided on the upper surface of the second laminated plate 20b. A ground conductor 37 is provided on the upper surface of the laminated plate 20b, and a plurality of via holes 38a, 38b are provided on the laminated plate 20b. , 38c, 38d, 38e, 38f, 38g, and 38h.
The ground conductor 37 located in the inner layer is formed by a thick film technique such as printing or coating, and the ground conductor 37 is made of silver paste or silver-palladium paste.

FIG. 5 shows an inner layer pattern provided on the upper surface of the third layered laminate 20c. The strip line 33 constitutes the inductance element 6a of FIG. 1, and a via hole 33a is provided at one end thereof. In addition, a via hole 33b is provided on the other end side.
Further, the via hole 33a and the first-layer via hole 29a are connected by a connection conductor (not shown) through the second-layer via hole 38f, and one end side of the inductance element 6a is connected to the capacitive element 6b. At the same time, the strip line 33, which is the inductance element 6a located in the inner layer, is in a state of being opposed to the first layer strip lines 21 and 24 with the second layer ground conductor 37 interposed therebetween.

The strip line 34 provided on the upper surface of the third layer constitutes the inductance element 9a of FIG. 1. A via hole 34a is provided on one end side and a via hole 34b is provided on the other end side. Is provided.
The via hole 34a and the first layer via hole 32a are connected by a connection conductor (not shown) through the second layer via hole 38g, and one end side of the inductance element 9a is connected to the capacitive element 9b. At the same time, the strip line 34, which is the inductance element 9a located in the inner layer, is in a state of facing the first layer strip lines 22 and 25 with the second layer ground conductor 37 interposed therebetween.

The strip line 33, which is the inductance element 6a, and the strip line 34, which is the inductance element 9a, are provided with electrodes 24c / 26a and electrodes 25c / 31, and are separated from each other on both sides of these electrodes, and Strip lines 33 and 34 are arranged in a state of being arranged in parallel.
Therefore, since the strip line 33 constituting the high pass filter unit 10 and the strip line 34 constituting the low pass filter unit 11 are separated from each other, it is difficult to couple with each other, and the first input / output terminal 2 and the second input / output Mutual isolation with the terminal 3 is improved.

A conductive line 35 is provided on the upper surface of the third layer. A via hole 35a is provided on one end side of the conductive line 35, and a via hole 35b is provided on the other end side. The via holes 23a are connected by a connection conductor (not shown) through a second-layer via hole 38h.
Further, the third layer laminated plate 20c has a via hole 36a provided at a substantially central portion and a via hole 36b provided at a corner portion.

  The strip lines 33 and 34 and the conductive line 35 located in the inner layer are formed by thick film technology such as printing and coating, and the strip lines 33 and 34 and the conductive line 35 are made of silver paste, silver-palladium paste, or the like. .

  FIG. 6 shows a pattern of the lower surface of the third layered laminate 20c. On the lower surface of the laminate 20c, a terminal electrode 39 serving as the input terminal (common terminal) 1 of FIG. 1 and the first input / output of FIG. A terminal electrode 40 to be the terminal 2, a terminal electrode 41 to be the second input / output terminal 3 in FIG. 1, a large-area ground conductor 42, and a plurality of ground electrodes 42 a provided on the ground conductor 42.

  The terminal electrode 39 has a via hole 35b, the terminal electrode 40 has a via hole 36b, the terminal electrode 41 has a via hole 34b, and the ground conductor 42 has via holes 33b and 36a. It is in a state.

  These terminal electrodes 39, 40, 41 and the ground conductor 42 are formed by a thin film technique such as vapor deposition or sputtering, or a thick film technique such as printing or coating. When these are formed by a thin film, the terminal electrode 39, 40, 41 and the ground conductor 42 are made of silver, aluminum, or the like, and when these are formed of a thick film, silver paste, silver-palladium paste, or the like is used.

  The via hole 35b is connected to the terminal electrode 39, which is the common terminal 1, via the connection conductor (not shown) on the other end side of the third-layer conductive line 35. As a result, the via hole located in the first layer 23 a is connected to the terminal electrode 39 through the connection conductor and the conductive line 35.

  In the first-layer conductive line 27, via holes 30a, 38b, and 36b are connected to the terminal electrode 40 that is the first input / output terminal 2 through connection conductors (not shown), and the third-layer conductive line 27 is connected. In the strip line 34, the via hole 34b is connected to the terminal electrode 41, which is the second input / output terminal 3, via a connection conductor (not shown).

Further, the strip line 33 has via holes 38d and 33b connected to the ground conductor 37 located on the upper surface of the second layer and the ground conductor 42 located on the lower surface via connection conductors (not shown). In the electrode 31 positioned, via holes 31a, 38e, and 36a are connected to a ground conductor 37 positioned on the upper surface of the second layer and a ground conductor 42 positioned on the lower surface via connection conductors (not shown).
With such a configuration, a diplexer having a circuit as shown in FIG. 1 is formed on the multilayer circuit board 20.

The circuit diagram which shows one Embodiment of the diplexer of this invention. The transmission characteristic figure of the diplexer of this invention. The top view which concerns on the diplexer of this invention and shows the pattern of the surface of a multilayer circuit board. The top view which shows the pattern of the inner layer upper surface of the 2nd layer of a multilayer circuit board regarding the diplexer of this invention. The top view which shows the pattern of the inner layer upper surface of the 3rd layer of a multilayer circuit board regarding the diplexer of this invention. The bottom view which shows the pattern of the lower surface of the 3rd layer of a multilayer circuit board concerning the diplexer of this invention. The circuit diagram of the conventional diplexer. The disassembled perspective view which shows the structure of the conventional diplexer.

Explanation of symbols

1: Input terminal (common terminal)
2: first input / output terminal 3: second input / output terminal 4: first low-frequency trap circuit 5: second low-frequency trap circuit 6: high-pass filter 7: first high-frequency trap 8: second 9: Low-pass filter 4a-9a: Inductance element 4b-9b: Capacitance element 10: High-pass filter part 11: Low-pass filter part 20: Multilayer circuit board 20a: First layer laminated board 20b: Second layer Laminated plate 20c: 3rd layer laminated plate 21: Strip electric circuit 21a, 21b: Electrode Z: Dielectric 22: Strip line 22a, 22b: Electrode 23a: Via hole 24: Strip line 24a, 24b: Electrode 25: Strip line 25a, 25b: Electrode 26: Conductive line 26a, 26b: Electrode 27: Conductive line 27a: Electrode 29a, 30a: Via hole 31: Electrode 31a: Via hole 32a: Via hole 33: Strip line 33a, 33b: Via hole 34: Strip line 34a, 34b: Via hole 35: Conductive line 35a, 35b: Via hole 36a, 36b: Via hole 37: Ground conductor 38a-38h: Via hole 39, 40 , 41: terminal electrode 42: ground conductor 42a: ground electrode

Claims (5)

A low-frequency trap circuit for attenuating a low-frequency band below a predetermined frequency and a high-pass filter connected in series to the low-frequency trap circuit are interposed between the common terminal and the first input / output terminal. A high-pass filter unit, a high-frequency trap circuit that attenuates the high-frequency band below the predetermined frequency, and a low-pass filter connected in series to the high-frequency trap circuit, and a common terminal and a second input A low-pass filter section interposed between the output terminal, the high-pass filter section, and a multilayer circuit board that forms the low-pass filter section, the high-pass filter and the low-pass filter comprising an inductance element and a capacitive element, respectively. On the surface of the multilayer circuit board, the low-frequency trap circuit, the high-frequency trap circuit, the high-pass filter and the front To form the respective capacitive element of the low-pass filter, the inner layer of the multilayer circuit board, characterized in that the formation of the high-pass filter and the inductance element of the low-pass filter diplexer. On the surface of the multilayer circuit board, the capacitive element of the low-frequency trap circuit and the capacitive element of the high-frequency trap circuit are arranged in parallel with a gap therebetween, and the inductance element of the low-frequency trap circuit and the high-frequency trap 2. The diplexer according to claim 1, wherein an inductance element of the circuit is disposed apart from each other on both sides of the area where the capacitive element is formed. The inductance element of the high-pass filter formed in the inner layer of the multilayer circuit board is disposed to face the low-frequency trap circuit formed on the surface of the multilayer circuit board, and the inner layer of the multilayer circuit board 3. The diplexer according to claim 2, wherein the inductance element of the low-pass filter formed on the surface of the low-pass filter is disposed to face the high-frequency trap circuit formed on the surface of the multilayer circuit board. A plurality of low-frequency trap circuits are provided corresponding to a plurality of low-frequency bands in different bands; a plurality of high-frequency trap circuits are provided corresponding to a plurality of high-frequency bands in different bands; A low-frequency trap circuit corresponding to the low-frequency side frequency band close to the predetermined frequency side among the plurality of low-frequency trap circuits is disposed on the common terminal side, and the predetermined frequency among the plurality of high-frequency trap circuits 4. The diplexer according to claim 2, wherein a high-frequency trap circuit corresponding to the high-frequency band close to the side is disposed on the common terminal side. The capacitive element and the inductance element of each of the low-frequency trap circuit and the high-frequency trap circuit formed on the surface of the multilayer circuit board, and the high-pass filter and the low-pass formed on the surface of the multilayer circuit board Each capacitive element of the filter is formed by a thin film or a thick film, and each of the inductance elements of the high-pass filter and the low-pass filter formed in the inner layer of the multilayer circuit board is formed by a thick film. The diplexer according to any one of claims 1 to 4, wherein the diplexer is provided.

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