JP2005315973A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for supplementing missing packets. <P>SOLUTION: The semiconductor integrated circuit comprises a write address counter 3 for outputting a writing address; a read address counter 4 for counting-up, when a control signal is not activated and performing counting-down, when it is activated; a buffer memory 2 for outputting the voice data stored to a region displayed in a reading address, by storing the voice data in a region displayed in a writing address; a packet error detecting circuit 5 for detecting packet errors; an error packet counter 6 for activating the control signal, while generating the packet errors: a sound volume regulated data preparating circuit 8 for outputting to prepare sound volume regulated data; and a sound volume regulating circuit 7 for overwriting a prescribed part of the voice data with the sound volume regulated data which are to be output to the outside. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit that performs signal processing on a plurality of packets received from the outside and outputs them.

  2. Description of the Related Art Conventionally, a technique that can eliminate noise in a digital signal received from the outside is known (see, for example, Patent Document 1).

  In Patent Document 1, an input digital signal is written according to a write address and a digital signal is read according to a read address, a write address counter that generates a write address in synchronization with a write clock, and a read clock A read address counter that generates a read address in synchronization with the address, an address monitoring unit that switches the read address when the write address and the read address have a preset relationship, and a read from the buffer memory before the read address is switched. A digital signal synchronous transfer circuit having amplitude adjusting means for gradually lowering the amplitude of the output digital signal and gradually restoring the read address after switching the read address is disclosed.

  The digital signal synchronous transfer circuit disclosed in Patent Document 1 switches the read address when the write address and the read address are in a preset relationship, and changes the amplitude of the digital signal before switching the read address. The noise can be eliminated by gradually lowering it and switching it back to the original address after switching. However, this synchronous transfer circuit does not output data that replaces the lost packet when the packet is lost.

JP-A-8-32562 (page 2-3)

  In view of the above, an object of the present invention is to provide a semiconductor integrated circuit capable of outputting data that replaces a lost packet when the packet is lost.

  In order to solve the above problems, a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit that performs signal processing on a plurality of packets received from the outside and outputs a plurality of data contained in the plurality of packets. A first circuit for generating and outputting a first group address for output and counting up or down when the control signal is not activated, and counting down when the control signal is activated Alternatively, by counting up, a second circuit for generating and outputting a second group address for reading a plurality of data included in the plurality of packets, and a plurality of data included in the plurality of packets Sequentially store in a plurality of areas represented by the first group address, and sequentially output a plurality of data stored in the plurality of areas represented by the second group address A buffer memory, a third circuit for activating a packet error signal when the address output from the write address counter matches the address output from the read address counter, and a packet error A fourth circuit for activating the control signal from when the signal is received until a new packet is received from the outside, and creating and outputting predetermined data while the control signal is activated When the control signal is not activated, the fifth circuit for performing the operation outputs a plurality of data output from the buffer memory to the outside, and outputs the buffer memory when the control signal is activated And a sixth circuit for overwriting a predetermined portion of the plurality of data with the predetermined data output from the fifth circuit and outputting the same to the outside.

  Here, the plurality of packets may be packets including audio data encoded by CVSD (Continuous Variable Slope Delta Modulation). Furthermore, the predetermined data created and output by the fifth circuit may be “0b01”.

  Further, the sixth circuit may increase the number of places overwritten with predetermined data among a plurality of data according to the time during which the control signal is activated. In addition, the sixth circuit outputs a predetermined portion of the plurality of data output from the buffer memory at a predetermined time after the control signal is activated and then deactivated. It may be overwritten with the data and output to the outside.

The best mode for carrying out the present invention will be described below with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and description is abbreviate | omitted.
FIG. 1 is a diagram showing an outline of a semiconductor integrated circuit according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor integrated circuit 1 includes a buffer memory 2, a write address counter 3, a read address counter 4, a packet error detection circuit 5, an error packet counter 6, a volume adjustment circuit 7, a volume And an adjustment data generation circuit 8. The semiconductor integrated circuit 1 is a circuit for outputting a bit stream obtained by performing digital signal processing on a voice packet encoded by CVSD (Continuous Variable Slope Delta Modulation) received from the outside.

The write address counter 3 counts up to sequentially generate and output a write address as a first group address for storing a plurality of data included in a packet received from the outside at a predetermined timing. Note that the write address counter 3 may generate a write address by counting down.
The buffer memory 2 stores a plurality of data included in a packet received from the outside in a plurality of areas each represented by a write address as a first group address.

The read address counter 4 generates and outputs a read address as a second group address for reading a plurality of data included in the packet stored in the buffer memory 2 at a predetermined timing. As will be described later, the read address counter 4 sequentially generates and outputs read addresses by counting up when the packet error detection circuit 5 does not detect packet loss (packet error). To do. On the other hand, when the packet error detection circuit 5 detects a packet error, the read address counter 4 outputs data in a normal packet before the packet error occurs in reverse order. Addresses that are traced back from the current read address are sequentially generated and output. When the read address counter 4 generates a read address by counting down when the packet error detection circuit 5 does not detect a packet error, and the packet error detection circuit 5 detects a packet error. The read address may be generated by counting up.
The buffer memory 2 sequentially outputs the data respectively stored in the plurality of areas represented by the read addresses as the second group addresses to the volume adjustment circuit 7 as bit streams.

The packet error detection circuit 5 determines that a packet is missing, that is, a packet error has occurred when the address output from the write address counter 3 and the address output from the read address counter 4 match. A detection signal is output to the error packet counter 6.
The error packet counter 6 activates the control signal to activate the read address counter 4 and adjust the volume from the time when the packet error detection signal is received until a new packet is received from the outside, that is, until the packet error is resolved. The data is output to the circuit 7 and the volume adjustment data creation circuit 8.

The volume adjustment data creation circuit 8 creates and outputs data for lowering the volume (attenuating the amplitude of the audio signal) while the control signal is activated. In the present embodiment, since a voice packet encoded by CVSD is input, the volume adjustment data creation circuit 8 creates 2-bit data “0b01”.
When the control signal is not activated, the volume adjustment circuit 7 outputs a plurality of data sequentially output by the buffer memory 2 as it is, and when the control signal is activated, the buffer memory 2 sequentially A predetermined portion of the plurality of data to be output is overwritten with data (here, “0b01”) output by the volume adjustment data creation circuit 8 and output. In CVSD, when data “0b01” is present in the bitstream, the sound volume is lowered. Therefore, when the control signal is activated, the volume of the bit stream output from the volume adjustment circuit 7 is lowered.

FIG. 2 shows the writing of a packet to the buffer memory 2 and the packet from the buffer memory 2 when the packet 2 among the voice packets 1 to 3 supplied to the semiconductor integrated circuit 1 from the outside is lost due to a packet error. It is a figure which shows the outline | summary of reading. Here, packet 1 includes data 1-1 to 1-5, packet 2 includes data 2-1 to 2-5, and packet 3 includes data 3-1 to 3-5. And FIG. 3 is a diagram illustrating an audio signal obtained by decoding packets 1 to 3.
As shown in FIG. 2, when packet 2 out of packets 1 to 3 is lost due to a packet error, data 1-1 to 1-5 included in packet 1 and data 3-1 to 1 included in packet 3 are displayed. 3-5 are sequentially stored in addresses 1 to A of the buffer memory 2.

On the other hand, the read address counter 4 sequentially outputs the addresses 1 to 5 for reading the data 1-1 to 1-5 included in the packet 1 to the buffer memory 2, and the data 1-1 to 1-5 are output from the volume adjustment circuit. 7 is supplied. At this time, since the packet error detection circuit 5 does not detect a packet error, the volume adjustment circuit 7 outputs the data 1-1 to 1-5 to the outside as they are.
Thereafter, the packet error detection circuit 5 detects a packet error, and the error packet counter 6 is from when the packet error detection signal is received until a new packet is received from the outside, that is, until the packet error is resolved. During this time, the control signal is activated.

  When the control signal is activated, the read address counter 4 outputs data (here, data 1-1 to 1-5) in a normal packet (here, packet 1) before the occurrence of the packet error in reverse order. Therefore, addresses (here, addresses 5 to 1) retroactive from the read address when the packet error occurs are sequentially generated and output. Further, the volume adjustment data creation circuit 8 creates data “0b01” and outputs it to the volume adjustment circuit 7. The volume adjustment circuit 7 sequentially outputs data in which the first 2 bits of each of the data 1-5 to 1-1 are overwritten with “0b01”. Thereafter, the control signal is deactivated, and the read address counter 4 sequentially outputs the addresses 6 to A for sequentially reading the data 3-1 to 3-5 included in the packet 3 to the buffer memory 2. 1 to 5 are sequentially output to the outside. FIG. 4 is a diagram showing an output bit stream at this time, and FIG. 5 is a diagram showing an audio signal obtained by decoding the bit stream shown in FIG.

In the present embodiment, the volume adjustment circuit 7 overwrites a total of five places of the first 2 bits of each of the data 1-5 to 1-1 with “0b01” (see FIG. 4). It is good also as overwriting a less part and it is good also as overwriting a more part.
In this embodiment, the case where one packet (packet 2) is lost has been described. However, a plurality of consecutive packets may be lost. In this case, the volume adjustment circuit 7 may increase the number of places to be overwritten with “0b01” according to the time during which the control signal is activated (the time during which the packet error continues). As a result, the volume can be gradually reduced as packet errors continue.
In addition, after the volume adjustment circuit 7 is activated and then deactivated (after a packet error occurs and then the packet error is resolved), a predetermined location in a normal packet after the packet error is resolved May be overwritten with “0b01”. Thereby, it is possible to prevent the volume from suddenly increasing after the packet error is eliminated.

As described above, according to the present embodiment, even when a packet is lost due to a packet error, as a substitute for the lost packet, the data in which the data included in the packet immediately before the lost packet is attenuated in the reverse order. Therefore, the continuity of the data waveform can be maintained and noise can be reduced.
It is also conceivable to output the data contained in the packet before the packet error occurs in reverse order without being attenuated. However, in this case, the sound changes when a plurality of consecutive packets are lost, and for example, a beep sound is output. On the other hand, if the data in which the data included in the packet before the occurrence of the packet error is attenuated is output in the reverse order as in this embodiment, the sound as described above is output when a plurality of consecutive packets are lost. Can be prevented from being output.

  In the present embodiment, the case where data included in a packet before the occurrence of a packet error is output in the reverse order when a packet is lost due to a packet error has been described. Since data continuity is ensured without reversing the data contained in the packet before the occurrence of the packet error, the data contained in the packet before the occurrence of the packet error may be output in the normal order.

  The present invention can be used in a semiconductor integrated circuit that performs signal processing and outputs a plurality of packets received from the outside.

1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. The figure which shows the example of the writing / reading of the data to the buffer memory 2 of FIG. The figure which shows the example of the audio | voice signal obtained by decoding an input packet. The figure which shows the example of the data which the volume adjustment circuit 7 of FIG. 1 outputs. The figure which shows the example of the audio | voice signal obtained by decoding the data of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit, 2 Buffer memory, 3 Write address counter, 4 Read address counter, 5 Packet error detection circuit, 6 Error packet counter, 7 Volume adjustment circuit, 8 Volume adjustment data creation circuit

Claims (5)

A semiconductor integrated circuit that performs signal processing and outputs a plurality of packets received from the outside,
A first circuit for generating and outputting a first group of addresses for storing a plurality of data contained in the plurality of packets;
Counting up or down when the control signal is not activated, and counting down or counting up when the control signal is activated, thereby reading the plurality of data included in the plurality of packets. A second circuit for generating and outputting a second group address for
The plurality of data included in the plurality of packets are sequentially stored in a plurality of areas represented by the first group of addresses, and the plurality of data stored in the plurality of areas represented by the second group of addresses A buffer memory for sequentially outputting the data of
A third circuit for activating a packet error signal when the address output by the write address counter matches the address output by the read address counter;
A fourth circuit for activating the control signal from when the packet error signal is received until a new packet is received from the outside;
A fifth circuit for creating and outputting predetermined data while the control signal is activated;
The plurality of data output from the buffer memory is output to the outside when the control signal is not activated, and the plurality of data is output from the buffer memory when the control signal is activated A sixth circuit for overwriting a predetermined portion of the data with the predetermined data output by the fifth circuit and outputting the same to the outside;
A semiconductor integrated circuit comprising: 2. The semiconductor integrated circuit according to claim 1, wherein the plurality of packets are packets including audio data encoded by CVSD (Continuous Variable Slope Delta Modulation). The semiconductor integrated circuit according to claim 2, wherein the predetermined data created and output by the fifth circuit is “0b01”. 4. The device according to claim 1, wherein the sixth circuit increases the number of places to be overwritten with the predetermined data in the plurality of data according to a time during which the control signal is activated. A semiconductor integrated circuit according to 1. In the sixth circuit, the fifth circuit outputs a predetermined portion of the plurality of data output from the buffer memory at a predetermined time after the control signal is activated and then deactivated. The semiconductor integrated circuit according to claim 1, wherein the predetermined data to be output is overwritten and output to the outside.

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