JP2005339519A - Resynchronization circuit - Google Patents

Abstract

【Task】
Even if the clock signal used for data output becomes high speed, it has a sufficient replacement margin so that data transfer can be speeded up.
[Solution]
The determination circuit 1100 holds and outputs a signal (determination result) corresponding to the phase difference between the input determination signal and the reference clock signal. The synchronization circuit block 1200 holds the input reception data signal by the strobe signal, and also holds and outputs the reception data signal at the same frequency as the reference clock signal and with the phase of the clock signal according to the determination result. The
[Selection] Figure 1

Description

  In order to pass data between circuits using clock signals having the same frequency but different phases, the present invention resynchronizes data synchronized with one clock signal with the other clock signal and outputs the data. The present invention relates to a resynchronization circuit.

  For example, in a system LSI that controls the read / write operation of a memory, when the read operation is controlled, the data output from the memory in synchronization with the reception-side clock signal is mutually phased at the same frequency as the reception-side clock signal. In order to pass the data to a circuit that operates in synchronization with different system clock signals, a resynchronization circuit is provided that outputs the data after resynchronization with the system clock signal (replacement of the clock signal).

  Such a resynchronization circuit includes a flip-flop that holds received data at the rising edge of the system clock signal, and a flip-flop that holds data at the falling edge, and the receiving side clock signal and the system clock signal Depending on the phase difference, one of the flip-flop outputs is selected and output, and this is held and output as a system clock signal (see, for example, Patent Document 1).

As a result, it is possible to output data synchronized with the receiving clock signal while resynchronizing with the system clock signal.
Special table 2001-520417 gazette

  However, since the conventional resynchronization circuit is configured to hold the received data at the rising edge or falling edge of the system clock signal, it is separated from the center of the period during which the data is effectively output. Data may be retained at different timings. For this reason, when the receiving side clock signal or the like becomes high speed, it is difficult to reliably latch data (that is, the replacement margin is reduced), and it is difficult to increase the data transfer speed.

  The present invention has been made paying attention to the above-mentioned problem, and provides a resynchronization circuit that has a sufficient replacement margin and can speed up data transfer even when the clock signal used for data output becomes high speed. The issue is to provide.

In order to solve the above problems, the invention of claim 1
A resynchronization circuit that receives a strobe signal together with a received data signal, and outputs the received data signal in synchronization with a reference clock signal having the same frequency as the strobe signal;
A reception timing detection circuit for detecting whether a timing at which the level of the received data signal is determined is in any one of a plurality of phase ranges divided into a plurality of phase ranges with respect to one cycle of the reference clock signal;
A first holding circuit for holding the received data signal in synchronization with the strobe signal;
The first holding circuit is synchronized with a second holding circuit clock signal whose level changes in a phase section different from the phase section detected by the reception timing detection circuit at the same frequency as the reference clock signal. A second holding circuit that holds the output of
A third holding circuit that holds and outputs the output of the second holding circuit in synchronization with the reference clock signal;
It is provided with.

The invention of claim 2
The resynchronization circuit of claim 1,
The second holding circuit includes a plurality of types of second holding circuits in which the plurality of holding circuits change the level of the output of the first holding circuit at the same frequency as the reference clock signal in different phase sections. It is characterized in that one signal selected from the signals held in synchronization with the circuit clock signal is held.

The invention of claim 3
The resynchronization circuit of claim 1,
The second holding circuit outputs a plurality of types of second holding circuit clock signals having the same frequency as the reference clock signal and having a level transition in different phase sections. It is characterized by being held in synchronization with one clock signal selected from among them.

The invention of claim 4
The resynchronization circuit of claim 1,
The reception timing detection circuit has a detection data signal whose level transitions at the same timing as when the level of the reception data signal is determined. It is configured to be held by a plurality of holding circuits in synchronization with the detection clock signal, and to perform the detection based on the level of each held signal.

The invention of claim 5
The resynchronization circuit of claim 4,
The detection data signal is a signal in which a reception data signal whose level is periodically inverted is held by the first holding circuit.

  As a result, it is detected which phase section of the reference clock signal is divided into a plurality of phase ranges for one cycle, and the received data signal can be transferred with a sufficient replacement margin.

The invention of claim 6
The resynchronization circuit of claim 4,
The detection data signal is a signal obtained by dividing the strobe signal.

  Thus, if the circuit for dividing the strobe signal and the first holding circuit are formed of the same type of flip-flops, a detection data signal that is accurately synchronized with the output of the first holding circuit can be generated. It becomes possible.

The invention of claim 7
The resynchronization circuit of claim 4,
The detection data signal is a signal obtained by delaying the strobe signal by a time corresponding to a delay amount of the first holding circuit.

  This makes it possible to generate a detection data signal that is accurately synchronized with the output of the first holding circuit.

The invention of claim 8
The resynchronization circuit of claim 4,
The reception timing detection circuit is configured to hold a signal obtained by delaying the detection data signal by a predetermined delay amount.

The invention of claim 9
The resynchronization circuit of claim 8, comprising:
The phase ranges of the plurality of phase sections are each the same size,
The predetermined delay amount for delaying the detection data signal is a delay amount corresponding to a half of a phase range of one phase section.

  As a result, the received data signal can be held and output at a timing closer to the center of the period during which the received data signal is effectively output.

The invention of claim 10 provides
The resynchronization circuit of claim 1,
The reception timing detection circuit is configured to perform the detection in a predetermined detection period;
The second holding circuit is configured to hold the output of the first holding circuit after the reception timing detection circuit performs the detection.

  Thus, since the detection by the reception timing detection circuit is performed in a predetermined period, a strobe signal having a period in which the level is periodically inverted and a period in which the level does not change (that is, a signal having a predetermined frequency intermittently) ), Even if this resynchronization circuit is built in and used in a system LSI that controls the read / write operations of the memory to which data is input and output, It becomes possible to do.

The invention of claim 11
The resynchronization circuit of claim 10 comprising:
The received data signal is a video data signal;
The reception timing detection circuit is configured to perform the detection within a blank period of the video data signal.

  As a result, it is detected during the blank period of the video data signal whether the timing at which the level of the video data signal is determined is within the phase division of the phase range for one cycle of the reference clock signal. Therefore, for example, even when the resynchronization circuit is incorporated and used in a system LSI that controls read / write operations of an image memory that requires high-speed operation, the received data signal is accurately transferred. It becomes possible to do.

The invention of claim 12
The resynchronization circuit of claim 10 comprising:
The received data signal is a data signal output from a memory having a refresh period;
The reception timing detection circuit is configured to perform the detection within a refresh period of the memory.

  As a result, since the detection by the reception timing detection circuit is performed during the refresh period of the memory having the refresh period, it is possible to accurately transfer the received data signal.

The invention of claim 13
The resynchronization circuit of claim 10, comprising:
The reception timing detection circuit is configured to perform the detection during a period in which noise included in the detection data signal is equal to or lower than a predetermined level.

  As a result, in the reception timing detection circuit, it is possible to accurately determine which phase section of the reference clock signal is divided into a plurality of phase sections for one period.

  According to the present invention, even if the clock signal used for data output becomes high speed, a sufficient replacement margin is provided, and data transfer can be speeded up.

  A resynchronization circuit according to an embodiment of the present invention includes a strobe signal (i.e., intermittently having a period in which a logical value is periodically inverted and a period in which the logical value is not changed, such as a DDR-SDRAM (Double Data Rate Synchronous DRAM). Are incorporated into a system LSI that controls read / write operations of a memory to which data is input / output based on a signal having a predetermined frequency.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 of the Invention
(Overall configuration)
FIG. 1 is a block diagram showing a configuration of a resynchronization circuit 1000 according to Embodiment 1 of the invention. First, the overall configuration of the resynchronization circuit will be described.

  As shown in the figure, the resynchronization circuit 1000 includes a determination circuit 1100 and a synchronization circuit block 1200.

  The determination circuit 1100 is controlled by a control circuit (not shown) to determine the phase difference between the input determination signal (described later) and the reference clock signal (SYS_CLK), and the determination result is obtained. The data is decoded and held, and is output to the synchronization circuit block 1200. As will be described in detail later, the determination result is that 90 to 180 degrees of the reference clock signal (when expressed as 90 to 180 degrees, 90 degrees is included in this range, and 180 degrees is not included. ), A signal according to which phase range of 180 to 270 [deg.], 270 to 0 [deg.], And 0 to 90 [deg.] Rises is output.

  Further, in the resynchronization circuit of the present embodiment, this determination operation is controlled by the control circuit so as to be performed during a period when the operation of receiving the actual reception data signal is not performed.

  The synchronization circuit block 1200 holds the input reception data signal by the strobe signal (Strobe), and further holds the reception data signal by a clock signal having the same frequency as the reference clock signal and a phase according to the determination result. Thus, after the transfer margin is increased, the signal is further held by the reference clock signal and output.

(Specific Configuration of Judgment Circuit 1100)
Next, a specific configuration of the determination circuit 1100 will be described. As shown in FIG. 2, the determination circuit 1100 includes flip-flops 1111 to 1114, AND circuits 1121 to 1124, NOR circuits 1113 to 1133, flip-flops 1141 to 1142, and an update control block 1150.

  The determination circuit 1100 is input with the strobe signal delayed by the delay circuit 1240 and the delay circuit 1250 as a determination signal, and performs the determination operation based on the strobe 1T.

  The flip-flops 1111 to 1114 have non-inverted outputs that hold strobe1T at the rising edges of clock signals (CK000, CK090, CK180, and CK270) that have the same frequency as the reference clock signal that is input to the flip-flops and that have different phases, Inverted output is output.

  CK000 is a clock signal having the same phase as the reference clock signal, and CK090, CK180, and CK270 are clock signals delayed in phase by 90 °, 180 °, and 270 ° with respect to the reference clock signal, respectively.

  When the clock signal as described above is input to the flip-flops 1111 to 1114, the strobe 1T is any of 90 to 180 °, 180 to 270 °, 270 to 0 °, and 0 to 90 ° of the reference clock signal. A value corresponding to whether the signal rises in the phase range is output from each flip-flop.

  A specific output is as shown in FIG. In FIG. 3, a column in which “1” is written indicates that the signal is at a high level (H level), and a column in which “0” is written indicates that the signal is at a low level (L level). Show. The columns whose headings are “flip-flop 1111” to “flip-flop 1114” are strobe 1T rising in the flip-flops 1111 to 1114 in the phase ranges of 90 to 180 °, 180 to 270 °, 270 to 0 °, and 0 to 90 °, respectively. The non-inverted output of each flip-flop when is input is shown.

  For example, when strobe1T rising in the phase range of 90 to 180 ° shown in FIG. 4 is input, the non-inverted outputs of the flip-flops 1111 to 1114 are L level, H level, H level, and L level, respectively.

  The AND circuits 1121 to 1124 and the NOR circuits 1131 to 1133 decode the signals output from the flip-flops 1111 to 1114 and output them from the NOR circuit 1131 and the NOR circuit 1133.

  Specifically, in the column of “AND circuit 1121” to “AND circuit 1124” in FIG. 3, the columns of the AND circuits 1121 to 1124 are 90 to 180 °, 180 to 270 °, 270 to 0 °, and 0 to 0, respectively. The output of each AND circuit when strobe1T rising in the phase range of 90 ° is input is shown.

  For example, when strobe1T rising in the phase range of 90 to 180 ° is input, the outputs of the AND circuits 1121 to 1124 become the H level, the L level, the L level, and the L level, respectively. In this case, the outputs of NOR circuits 1131 and 1133 are both at the L level.

  The flip-flops 1141 to 1142 hold the decoded output (determination result) and output it as two signals of rsync_late and rsync_chph.

  Specifically, the columns of “rsync_late” and “rsync_chph” in FIG. 3 indicate the outputs of the flip-flops 1141 to 1142, respectively. For example, when strobe 1T rising in the phase range of 90 to 180 ° is input to the determination circuit 1100, the values held in the flip-flops 1141 to 1142 are all at the L level.

  The update control block 1150 includes a flip-flop 1151 and an AND circuit 1152, and the flip-flops 1141 to 1142 hold the flip-flop 1141 to 1142 according to a signal (rssync_hold) instructing to update the determination result input from the control circuit. The judgment result is updated. This rsync_hold is a signal whose period of H level is a period of one period or more of SYS_CLK in order to make an accurate determination. Therefore, the determination result is updated in a period in which rsync_hold is at the H level, and outputs (determination results) of the NOR circuit 1131 and the NOR circuit 1133 at the timing when rsync_hold is changed from the H level to the L level are the flip-flop 1141 and the output respectively. It is held in the flip-flop 1142.

  As described above, the determination result output from the determination circuit 1100 is that any one of the four phase ranges in which the determination signal is 0 to 90 °, 90 to 180 °, 180 to 270 °, and 270 to 0 °. It will indicate whether to stand up. That is, the determination circuit 1100 outputs a signal according to which phase range of the reference clock signal rises from 90 to 180 °, 180 to 270 °, 270 to 0 °, and 0 to 90 °.

(Specific Configuration of Synchronous Circuit Block 1200)
Next, a specific configuration of the synchronization circuit block 1200 will be described. As shown in FIG. 1, the synchronization circuit block 1200 includes a flip-flop 1210, selectors 1221 to 1224, flip-flops 1231 to 1234, a delay circuit 1240, and a delay circuit 1250.

  The flip-flop 1210 holds the input data (Data) with the strobe signal and outputs a received data signal (D). The received data signal (D) has a width corresponding to one cycle of the reference clock signal.

  The selector 1221 selects and outputs CK270 when the rsync_chph is at L level, and selects and outputs CK000 when it is at H level.

  The selector 1222 selects and outputs CK090 when the rsync_chph is at the L level, and selects and outputs CK180 when the rsync_chph is at the H level.

  The selector 1223 selects and outputs the output of the flip-flop 1233 when the rsync_late is at the L level, and selects and outputs the output of the flip-flop 1232 when the rsync_late is at the H level.

  The selector 1224 operates as a delay circuit that delays the output of the flip-flop 1210 by a delay amount equivalent to that of the selector 1221 or the selector 1222. That is, the selector 1224 is not limited to a selector as long as it has a delay amount equivalent to that of the selector 1221 and the selector 1222.

  The flip-flop 1231 holds the input received data signal (D) at the rising edge of CK 270 or CK 000 selected and input by the selector 1221.

  The flip-flop 1232 holds the received data signal (D) at the rising edge of CK090 or CK180 selected and input by the selector 1222.

  The flip-flop 1233 holds the output of the flip-flop 1231 at the rising edge of CK180.

  The flip-flop 1233 is provided for the following reason.

  When CK000 is selected by the selector 1221, the output of the flip-flop 1231 may be output as it is if the CK000 and the reference clock signal have the same phase.

  However, in practice, CK000 and the reference clock signal are out of phase, so that the output of the flip-flop 1231 needs to be held in the flip-flop 1234 by the reference clock signal. In this case, depending on the phase difference between CK000 and the reference clock signal, there is a possibility that mis-latching occurs due to holding by the flip-flop 1234 before the output of the flip-flop 1231 rises.

  Therefore, in the resynchronization circuit of this embodiment, the flip-flop 1233 is provided, and the output of the flip-flop 1231 is temporarily held by the flip-flop 1233 by the CK 180, thereby preventing the mis-latch.

  When the CK 270 is selected by the selector 1221, the output of the flip-flop 1231 may be output as it is to the selector 1223 without being held by the flip-flop 1233. However, in this embodiment, the circuit configuration is simplified. Also in this case, the output of the flip-flop 1231 is held by the flip-flop 1233.

  Among the CK000, CK090, CK180, and CK270, a holding circuit that holds data by a clock signal that rises at the timing closest to the center of the period during which the received data signal (D) is effectively output is a selector 1221-1223, And flip-flops 1231-1233.

  The flip-flop 1234 holds and outputs the output of the selector 1223 at the rising edge of the reference clock signal.

  The delay circuit 1240 delays the strobe signal by a delay amount equivalent to that of the flip-flop 1210. As a result, the determination signal has the same phase as the received data signal.

  The delay circuit 1250 further delays the strobe signal delayed by the delay circuit 1240 by 45 ° (a delay amount that is 1/8 of the period of the reference clock signal) and outputs the delayed signal to the determination circuit 1100 as strobe1T. .

  As described above, the determination signal is not the strobe signal itself, but the strobe 1T delayed by 45 ° with respect to the strobe signal is as follows.

  For example, when the strobe signal delayed by the delay circuit 1240 is directly input to the determination circuit 1100 and determination is performed using four clock signals CK000, CK090, CK180, and CK270, the determination results are 0 to 90 ° and 90 to 180 °. , 180 to 270 °, and 270 to 0 °, which indicates one of the four phase ranges.

  When the determination result is, for example, 0 to 90 °, ideally, the facing edge of the clock signal having the phase of 45 ° that is the center phase of 0 to 90 ° (the edge having a phase difference of 180 ° with respect to any rising edge) If the received data signal is held by the clock signal that rises at), that is, a clock signal having a phase of 225 °, it can be held at the timing closest to the center of the period during which the received data signal (D) is effectively output. It becomes possible.

  However, since there is no clock signal having a phase of 225 ° in CK000 to CK270, the received data signal is eventually generated by a clock signal (CK180) having a phase of 180 ° or a clock signal (CK270) having a phase of 270 °. Will hold. That is, the received data signal (D) is held by the clock signal that rises at a timing deviated by 45 ° from the center of the period during which the received data signal (D) is being effectively output.

  Therefore, the resynchronization circuit 1000 determines the rising edge of the strobe signal by using strobe1T delayed by 45 ° as the determination signal, so that the determination results are 45 to 135 °, 135 as shown in FIG. Any one of four phase ranges of ˜225 °, 225 to 315 °, and 315 to 45 °, and a clock signal (CK270, CK000, CK090, or CK180 facing each other from the center phase of each phase range) Is selected, the received data signal (D) can be held at the timing closest to the center of the period during which the received data signal (D) is effectively output, and the transposition margin can be increased.

  The table of FIG. 5 shows the relationship between the phase range of the rising edge of the determination signal (strobe1T), the phase range of the rising edge of the received data signal (D), and the clock signal that holds the received data signal. In this table, the column with the heading “1statch” indicates which output of the flip-flop 1231 and the flip-flop 1232 is selected, and the portion where CK180 is described in the column with the heading “2ndlatch” It shows that the flip-flop 1233 holds the output of the flip-flop 1231 at CK180.

  FIGS. 6 to 9 are timing charts showing the relationship among the clock signal holding the received data signal, the received data signal, and the output of the resynchronization circuit. For example, FIG. 6 shows an example where the rising edge of the received data signal is in the phase range of 45 ° to 135 °. In this example, the received data signal is held at CK 270 and then held at CK 180. Further, it is shown that it is held and output by the reference clock signal (SYS_CLK). Similarly, FIG. 7 shows an example when the rising edge of the received data signal is 135 to 225 °, FIG. 8 shows an example when 225 to 315 °, and FIG. 9 shows an example when 315 to 45 °.

  Note that the replacement margin increases as the number of phase sections in the phase range to be determined increases. In this case, however, the number of types of clock signals to be generated increases, and the circuit scale corresponding to the number of clock signals is increased.

  Further, in the resynchronization circuit of the present embodiment, since the above four clock signals are used so that the determination result is in the four phase ranges as described above, the delay amount of strobe1T is set to 45 °. When the number of phase segments is changed, the phase segment may be delayed by a delay amount corresponding to half of the phase range of one phase segment.

(Resynchronization circuit operation)
In the resynchronization circuit 1000, prior to changing the clock signal of the received data signal (D), the determination circuit 1100 performs an operation of determining in which phase range of the reference clock signal the strobe signal rises. The period during which this determination operation is performed (determination period) needs to be a period in which the strobe signal periodically inverts the logical value.

  For example, when strobe1T that rises at a phase of 90 to 180 ° as shown in FIG. 4 is input during the determination period, the determination circuit 1100 operates as follows, and rsync_late whose levels are all L levels, and rsync_chph is output to the synchronization circuit block 1200.

  When rsync_hold of H level is input from the control circuit during the determination period, and strobe1T is input to the determination circuit 1100 as a determination signal, the flip-flops 1111 to 1114 have L level, H level, H level, and Hold the L level and output. Outputs of the flip-flops 1111 to 1114 are decoded by AND circuits 1121 to 1124, a NOR circuit 1131, and a NOR circuit 1133. Specifically, AND circuits 1121-1124 output H level, L level, L level, and L level signals, respectively, and NOR circuits 1131 and 1133 output L level signals as decoding results, respectively. To do.

  Here, when rsync_hold is shifted from the H level to the L level by the control circuit, the flip-flop 1141 and the flip-flop 1142 hold the outputs of the NOR circuit 1131 and the NOR circuit 1133, respectively, and rsync_late and rsync_chph ( These signals are output to the synchronous circuit block 1200 as both signals of L level.

  When the determination operation is completed and the received data signal (D) input from the memory or the like is synchronized with the reference clock signal, the received data signal (D) rising in a phase range of 90 to 180 °, for example, is input. The received data signal (D) is held by the CK 270 that rises at the timing closest to the center of the period during which the received data signal (D) is being effectively output, and further held and output by the reference clock signal.

  That is, since rsync_chph held by the determination circuit 1100 is at the L level, CK270 is input to the flip-flop 1231 and CK090 is input to the flip-flop 1232 by the selectors 1221-1222. The flip-flops 1231 to 1232 hold and output the received data signal (D) according to the clock signal input thereto. The output of the flip-flop 1231 is further held in the flip-flop 1233 by the CK 180.

  On the other hand, since rsync_late is also at the L level, the selector 1223 selects the output of the flip-flop 1233, which is held and output by the flip-flop 1234 by the reference clock signal (SYS_CLK). The output of the flip-flop 1234 is a signal (data) obtained by changing the received data signal from the strobe signal to the reference clock signal.

  As described above, according to the present embodiment, since it is determined in advance in which phase range of the reference clock signal the rising edge of the strobe signal rises during the determination period, one received data signal (D) is effectively output. The received data signal can be held by the clock signal that rises at the timing closest to the center of the period, and the received data signal can be transferred with a sufficient replacement margin even if the reference clock signal becomes high speed. .

  In addition, since the determination result is retained, it is possible to transfer the received data signal even when data is input based on a strobe signal having a predetermined frequency intermittently.

  In the first embodiment, the outputs of the AND circuit 1124 and the NOR circuit 1132 of the determination circuit 1100 are not used, but the decoding of the outputs of the flip-flops 1111 to 1114 has a predetermined decoding result as shown in FIG. If obtained, any three outputs of the AND circuits 1121 to 1124 may be used. In this case, the present invention is not limited to the above example as long as a predetermined logic circuit is provided instead of the NOR circuits 1131 to 1133 to decode the output of the AND circuit.

  The clock signals (CK000 and CK270) used in the update control block 1150 are not limited to the above example as long as the two clock signals have a phase difference of 270 °.

<< Embodiment 2 of the Invention >>
The resynchronization circuit according to the second embodiment of the present invention is an example of an apparatus that uses a received data signal as a determination signal. In the following embodiments, components having the same functions as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  FIG. 10 is a block diagram showing the configuration of the resynchronization circuit 2000. As shown in the figure, the resynchronization circuit 2000 includes a determination circuit 2100 and a synchronization circuit block 2200.

  Compared to the determination circuit 1100 of the first embodiment, the determination circuit 2100 uses a reception data signal instead of a strobe signal as a determination signal, and determines in which phase range of the reference clock signal (SYS_CLK) the reception data signal rises. It is different in the configuration.

  Specifically, as shown in FIG. 11, the determination circuit 2100 includes flip-flops 2111 to 2114, flip-flops 2121 to 2127, AND circuit 2128, EXOR circuits 2131 to 2133, NOR circuit 2134, OR circuits 2135 to 2136, flip-flops. 2141 to 2142, and an update control block 1150.

  In the flip-flops 2111 to 2114, the flip-flops 2121 to 2127, and the AND circuit 2128 (hereinafter referred to as edge detection unit), the rising edge of the input determination signal (strobe1T) is 90 to 180 °, 180 to 270 °, A value corresponding to which phase range rises (or falls) between 270 to 0 ° and 0 to 90 ° is output. This portion corresponds to the flip-flops 1111 to 1114 and the AND circuits 1121 to 1124 of the determination circuit 1100 in FIG. Note that the flip-flops 2121 to 2122 are flip-flops for timing adjustment of the flip-flops 2123 to 2126. The edge detector configured as described above can operate at a higher speed than the first embodiment.

  The EXOR circuits 2131 to 2133, the NOR circuit 2134, and the OR circuits 2135 to 2136 are configured to decode and output the output of the edge detection unit.

  As a result, the determination circuit 2100 can determine in which phase range the received data signal whose value changes at the rising edge or the received data signal whose value changes at the falling edge changes.

  The specific relationship between the rising or falling phase range of the edge of the input determination signal (strobe1t) and the output of the determination circuit 2100 (rsync_late and rsync_chph) is as shown in the table of FIG. In the table of FIG. 11, a column in which “1” is written indicates that the signal is at the H level, and a column in which “0” is written indicates that the signal is at the L level.

  Compared with the synchronization circuit block 1200, the synchronization circuit block 2200 delays the reception data signal (D) instead of the strobe signal by the delay circuit 1250, and outputs this to the determination circuit 2100 as strobe1T, as shown in FIG. Is different.

  In the resynchronization circuit configured as described above, when a determination operation is performed, it is necessary to input data (Data) of a pattern that alternately repeats the H level and the L level during the determination period as a determination signal. . That is, it is necessary to systematically secure data (Data) in the determination period so as to have such a data pattern.

  For example, when data input from a DDR-SDRAM is received and re-synchronized with a reference clock signal, data that can alternately read 0 and 1 in advance in a predetermined address area of the DDR-SDRAM is used. Writing is performed by a write operation, and a determination period is provided at the time of system startup or the like, and a read operation is performed on the address area of the DDR-SDRAM during that period.

  As a result, the data (Data) input during the determination period alternately repeats the H level and the L level, so that the phase range in which the data changes can be accurately determined.

  Therefore, also in the present embodiment, it is possible to transfer the received data signal with a sufficient replacement margin even if the reference clock signal becomes high speed.

  In addition, since the determination result is held, the received data signal can be transferred even when data is input intermittently based on a strobe signal having a predetermined frequency.

  Moreover, in the resynchronization circuit of the present embodiment, the received data signal is used as the determination signal. Therefore, even if the signal is delayed by the flip-flop 1210, the phase range in which the received data signal rises (or falls) is more accurately determined. It becomes possible to judge.

<< Embodiment 3 of the Invention >>
The resynchronization circuit according to the third embodiment of the present invention is an example of an apparatus that uses a signal obtained by dividing the strobe signal as a determination signal.

  FIG. 12 is a block diagram showing a configuration of resynchronization circuit 3000. As shown in the figure, the resynchronization circuit 3000 includes a determination circuit 2100 and a synchronization circuit block 3200.

  In the synchronous circuit block 3200, the flip-flop 3240 divides the strobe signal by two, and a signal obtained by delaying the strobe signal by the delay circuit 1250 is output to the determination circuit 2100 as strobe1T.

  By dividing the strobe signal by 2 in this way, a signal corresponding to the received data signal (D) having a pattern in which the H level and the L level are alternately repeated is generated from the strobe signal (that is, imitating the received data signal). In addition, unlike the resynchronization circuit of the second embodiment, it is not necessary to write a determination signal in a memory or the like so that “0” and “1” can be alternately read in advance.

  In the present embodiment configured as described above, it is also possible to transfer the received data signal with a sufficient replacement margin even if the reference clock signal becomes high speed.

  In addition, since the determination result is held, the received data signal can be transferred even when data is input intermittently based on a strobe signal having a predetermined frequency.

  In addition, since the signal delay time in the flip-flop 1210 and the signal delay time in the flip-flop 3240 are substantially the same, it is possible to more accurately determine the phase range in which the received data signal rises (or falls). .

  In each of the above embodiments, an example in which data output based on a strobe signal having a predetermined frequency is received intermittently has been described. However, data synchronized with a continuous clock signal is received. In each case, the above embodiments can be applied.

  In each of the above embodiments, an example in which a period during which no actual data is received is described as the determination period. However, the determination operation is performed in parallel with the data reception, and the determination result is obtained after the data reception ends. May be updated. In this case, for example, an update flip-flop that holds the outputs of the flip-flop 1141 and the flip-flop 1142 is provided, and a signal that controls the update is input to the update flip-flop from outside the resynchronization circuit or the like. What is necessary is just to comprise.

  The determination may be made at a predetermined cycle. As a result, for example, when the temperature of the system LSI in which the resynchronization circuit is incorporated changes, the delay amount of the signal changes, the determination can be made appropriately, and the resynchronization can be accurately performed. It becomes possible to do. An example of the predetermined cycle is a DRAM (Dynamic Random Access Memory) refresh period. When a video data signal is input as the received data signal, a blank period of the video data signal may be set as the determination period.

  In addition, since it is desirable that the determination period is a period in which the input signal has as little noise as possible, it is preferable to perform the determination when the noise is equal to or lower than a predetermined level. As a result, the phase range can be determined more accurately.

  Even if the delay circuit 1250 is not provided, the determination of the phase range by the determination circuit 1100 or the determination circuit 2100 is possible.

  In addition, the determination circuit 1100 and the determination circuit do not determine the clock signal that holds the received data signal (D) by a single determination, but performs a plurality of determinations, for example, so that one determination result is output by a majority decision. 2100 may be configured.

  In addition, the synchronization circuit block may be configured such that after one clock signal holding the reception data signal is selected from among a plurality of clock signals, the reception data signal is held by one flip-flop. As a result, the number of flip-flops can be reduced, and the circuit scale can be suppressed.

  In addition, a flip-flop that holds the received data signal is provided for each of a plurality of clock signals, and a synchronization circuit block is configured to select a signal having the largest transfer margin from signals held by these flip-flops. May be. With this configuration, flip-flops are required for the plurality of types of clock signals, but it is not necessary to provide a selector in the path of the clock signal, and timing design is facilitated.

  Further, the correspondence relationship between the level (logical value) of each signal and the content indicated by the level shown in the above embodiments is merely an example, and the present invention is not limited to these.

  The resynchronization circuit according to the present invention has an effect of having a sufficient transposition margin even when the clock signal used for data output becomes high speed, and speeding up the data transfer, and the frequency is the same. Is useful as a resynchronization circuit for outputting data synchronized with one clock signal in resynchronization with the other clock signal in order to pass data between circuits using clock signals with different phases.

It is a block diagram which shows the structure of the resynchronization circuit of Embodiment 1 of this invention. It is a block diagram which shows the structure of a judgment circuit. It is a truth table of a judgment circuit. It is a timing chart of a clock signal or the like input to the determination circuit. It shows the relationship between the phase range in which the determination signal (strobe1T) rises, the phase range in which the received data signal (D) rises, and the clock signal that holds the received data signal. The timing chart shows the relationship between the clock signal that holds the received data signal, the received data signal, and the output of this resynchronization circuit when the rising edge of the received data signal is in the phase range of 45 ° to 135 °. is there. The timing chart shows the relationship between the clock signal that holds the received data signal, the received data signal, and the output of this resynchronization circuit when the rising edge of the received data signal is in the phase range of 135 ° to 225 °. is there. The timing chart shows the relationship between the clock signal that holds the received data signal, the received data signal, and the output of this resynchronization circuit when the rising edge of the received data signal is in the phase range of 225 ° to 315 °. is there. The timing chart shows the relationship between the clock signal that holds the received data signal, the received data signal, and the output of this resynchronization circuit when the rising edge of the received data signal is in the phase range of 315 ° to 45 °. is there. It is a block diagram which shows the structure of the resynchronization circuit of Embodiment 2 of this invention. It is a block diagram which shows the other structural example of a judgment circuit. It is a block diagram which shows the structure of the resynchronization circuit of Embodiment 3 of this invention.

Explanation of symbols

1000 resynchronization circuit 1100 decision circuit 1111 to 1114 flip-flop 1121 to 1124 AND circuit 1131 to 1133 NOR circuit 1141 to 1142 flip-flop 1150 update control block 1151 to 1152 flip-flop 1200 synchronization circuit block 1210 flip-flop 1221 to 1224 selector 1231 to 1234 Flip-flop 1240 Delay circuit 1250 Delay circuit 2000 Resynchronization circuit 2100 Decision circuit 2111 to 2114 Flip-flop 2121 to 2127 Flip-flop 2128 AND circuit 2131 to 2133 EXOR circuit 2134 NOR circuit 2135 to 2136 OR circuit 2141 to 2142 Flip-flop 2161 Flip-flop 2162 AND circuit 220 Synchronization circuit block 3000 re-synchronization circuit 3200 synchronization circuit block 3240 flip-flop

Claims (13)

A resynchronization circuit that receives a strobe signal together with a received data signal, and outputs the received data signal in synchronization with a reference clock signal having the same frequency as the strobe signal;
A reception timing detection circuit for detecting whether a timing at which the level of the received data signal is determined is in any one of a plurality of phase ranges divided into a plurality of phase ranges with respect to one cycle of the reference clock signal;
A first holding circuit for holding the received data signal in synchronization with the strobe signal;
The first holding circuit is synchronized with a second holding circuit clock signal whose level changes in a phase section different from the phase section detected by the reception timing detection circuit at the same frequency as the reference clock signal. A second holding circuit that holds the output of
A third holding circuit that holds and outputs the output of the second holding circuit in synchronization with the reference clock signal;
A resynchronization circuit comprising: The resynchronization circuit of claim 1,
The second holding circuit includes a plurality of types of second holding circuits in which the plurality of holding circuits change the level of the output of the first holding circuit at the same frequency as the reference clock signal in different phase sections. A resynchronization circuit configured to hold one signal selected from each signal held in synchronization with a circuit clock signal. The resynchronization circuit of claim 1,
The second holding circuit outputs a plurality of types of second holding circuit clock signals having the same frequency as the reference clock signal and having a level transition in different phase sections. A resynchronization circuit configured to be held in synchronization with one clock signal selected from among them. The resynchronization circuit of claim 1,
The reception timing detection circuit has a detection data signal whose level transitions at the same timing as when the level of the reception data signal is determined, and has a frequency that is the same as that of the reference clock signal and a level transition in different phase sections. A resynchronization circuit configured to be held by a plurality of holding circuits in synchronization with a detection clock signal and to perform the detection based on the level of each held signal. The resynchronization circuit of claim 4,
The resynchronization circuit according to claim 1, wherein the detection data signal is a signal in which a reception data signal whose level is periodically inverted is held by the first holding circuit. The resynchronization circuit of claim 4,
The resynchronization circuit according to claim 1, wherein the detection data signal is a signal obtained by dividing the strobe signal. The resynchronization circuit of claim 4,
The resynchronization circuit according to claim 1, wherein the detection data signal is a signal obtained by delaying the strobe signal by a time corresponding to a delay amount of the first holding circuit. The resynchronization circuit of claim 4,
The resynchronization circuit, wherein the reception timing detection circuit is configured to hold a signal obtained by delaying the detection data signal by a predetermined delay amount. The resynchronization circuit of claim 8, comprising:
The phase ranges of the plurality of phase sections are each the same size,
The resynchronization circuit according to claim 1, wherein the predetermined delay amount for delaying the detection data signal is a delay amount corresponding to a half of a phase range of one phase section. The resynchronization circuit of claim 1,
The reception timing detection circuit is configured to perform the detection in a predetermined detection period;
The resynchronization circuit, wherein the second holding circuit is configured to hold the output of the first holding circuit after the reception timing detection circuit performs the detection. The resynchronization circuit of claim 10 comprising:
The received data signal is a video data signal;
The resynchronization circuit, wherein the reception timing detection circuit is configured to perform the detection within a blank period of the video data signal. The resynchronization circuit of claim 10 comprising:
The received data signal is a data signal output from a memory having a refresh period;
The resynchronization circuit, wherein the reception timing detection circuit is configured to perform the detection within a refresh period of the memory. The resynchronization circuit of claim 10, comprising:
The resynchronization circuit, wherein the reception timing detection circuit is configured to perform the detection during a period in which noise included in the detection data signal is equal to or lower than a predetermined level.

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