JP2006040923A - ESD protection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit which prevents a latch rise by providing a circuit for controlling a trigger voltage and effective to prevent a damage in an electrostatic discharge prevention apparatus of silicon controlled rectifier (SCR) type. <P>SOLUTION: The resistance value of the silicon controlled rectifier is controlled. When a power is not supplied, it is a high resistance, and when the power is supplied, it can be varied to a low resistance. Thus, when the power is not supplied, the trigger voltage of the silicon controlled rectifier is a low voltage, and when the power is supplied, it becomes a high voltage. When the power is not supplied by this, the protection of an integrated circuit is strengthened and the latch rise can be suppressed at the power supply time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electrostatic breakdown preventing device having a circuit structure for controlling a trigger voltage and a snapback voltage in an electrostatic preventing device having a silicon controlled rectifier (SCR).

  A conventional silicon controlled rectifier (SCR) antistatic device has proposed a circuit as shown in Patent Document 1.

Hereinafter, the prior art will be described using a general silicon controlled rectifier (SCR) configuration. FIG. 2 shows a configuration diagram of a conventional silicon controlled rectifier. In FIG. 2, 1 and 2 are parasitic well resistors R1 and R2, and 3 and 4 are parasitic transistors Q1 and Q2. The collector of Q1, the base of Q2, and R1 are connected, and the base of Q1, the collector of Q2, and R2 are connected. The operation of the silicon controlled rectifier (SCR) configured as described above will be described below. When power is supplied, the voltage drop of R1 and R2 is below the threshold value of Q1 and Q2, but when static electricity is applied, the voltage drop of R1 and R2 exceeds the threshold value of Q1 and Q2, and Q1 and Q2 are turned on. Transition to the latch-up state to release static electricity to an external pad to protect the integrated circuit from static electricity.
Japanese Patent No. 3191209

  In the above-described conventional configuration, the resistance values of R1 and R2, and Hfe of Q1 and Q2 are parameters determined at the manufacturing stage, and the trigger voltage and snapback voltage determined by the parameters are supplied and not supplied. If the trigger voltage is set low to protect the integrated circuit, there is a risk of latch-up. If the trigger voltage is set high, latch-up does not occur but the integrated circuit may be damaged.

  SUMMARY OF THE INVENTION An object of the present invention is to propose a silicon controlled rectifier (SCR) that can change a trigger voltage and a snapback voltage between when power is supplied and when power is not supplied.

  In order to achieve this object, the electrostatic breakdown preventing device of the present invention includes a transistor for controlling a resistance value. The resistance value is controlled when power is supplied to the control terminal of the transistor and when the power is not supplied. With this configuration, the trigger voltage and snapback voltage of the silicon controlled rectifier (SCR) can be changed between when power is supplied and when it is not supplied, thereby preventing latch-up and effectively protecting the integrated circuit from static electricity. It can be.

  The present invention can protect an integrated circuit against static electricity while preventing latch-up in an electrostatic breakdown prevention device of a silicon controlled rectifier (SCR).

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows a first configuration of the electrostatic breakdown preventing apparatus of the present invention. In FIG. 1, reference numeral 5 denotes a transistor Q3. In the normal thyristor structure, the transistor Q3 is inserted into the R2 portion, and the control portion of the transistor Q3 is connected to the power supply pad. The transistors 3 and 4 are the transistors Q1, Q2, and 1 are the resistor R1, which are the conventional examples. The circuit is the same as the configuration of

  The operation of the electrostatic breakdown preventing apparatus of the present embodiment configured as described above will be described below. FIG. 3 is a characteristic diagram showing the current flowing from the first pad 16 to the second pad 17 in the present embodiment, and shows the relationship between the trigger voltage 6 and the snapback voltage 7. When the trigger voltage is exceeded by applying a surge while power is being supplied, the thyristor structure is turned on and a snapback phenomenon occurs as shown in FIG. When a voltage higher than the snapback voltage is applied, the silicon controlled rectifier (SCR) is in a latch-up state. If the snapback voltage is not higher than the operating power supply voltage when supplying power, the power supply voltage will cause latch-up and destroy the semiconductor circuit, but when power is not supplied, set the snapback voltage low. It is necessary to effectively release the surge. If the thyristor parameter is set so that the snapback voltage is higher than the power supply voltage, the latch-up phenomenon will not occur. When the power is not supplied, the control terminal of the transistor Q3 is in a floating state, so that the resistance between the input and output terminals is high, and the voltage drop is large, so that the threshold value of the transistor Q2 is easily exceeded. As a result, the trigger voltage and the snapback voltage are lower than when the power is supplied.

  Therefore, in the embodiment of FIG. 1, the electrostatic breakdown prevention device uses the control terminal of the transistor Q3 to set the trigger voltage and snapback voltage high when power is supplied to inhibit latch-up, while the power is supplied. If not, the trigger voltage and snapback voltage are lowered and the silicon controlled rectifier (SCR) is latched up for the purpose of releasing static electricity.

(Second Embodiment)
FIG. 4 shows an embodiment for realizing the structure in the embodiment shown in FIG. 1 with a small area, and the structure will be described below. FIG. 4 is a layout diagram of the electrostatic breakdown preventing apparatus of the present embodiment. In this embodiment, a second conductivity type first well 9 is provided in a first conductivity type semiconductor substrate 8, and a second conductivity type is adjacent to the first conductivity type third well 11 in the first well 9. A second well 10 is formed. Further, a second conductivity type second impurity region 13 and a third impurity region 14 formed in the third well 11 are formed, and a control line 15 is formed between the second impurity region 13 and the third impurity region 14. A first impurity region 12 of the first conductivity type formed in the second well 10 is formed, and is connected to the third impurity region 14 and the third well 11 by a metal layer, and the first impurity region 12 and the second impurity region are connected. The second impurity region 13 is connected to the second pad 17, the first impurity region 14 is connected to the first pad 16, and the control line 15 is connected to the third pad 18 through the contact holes of the region 13 and the control line 15, respectively. The second pad 17 is connected to VSS, the third pad 18 is connected to VCC, and the first pad is connected to the pad of the circuit to be protected. In the present embodiment, the first conductivity type is a P conductivity type, and the second conductivity type is an N conductivity type. Hereinafter, the operation of the electrostatic breakdown preventing apparatus of the present embodiment configured as described above will be described. In this embodiment, the bipolar transistors 19 and 20 form a thyristor structure. The base of the bipolar transistor 20 has a very high impedance when no power is applied to the control line, and operates at a low voltage by applying a surge or the like. However, when power is applied to the control line, the base of the bipolar transistor 20 has a low impedance and operates only at a high voltage. One of the characteristics of the transistor is the snapback voltage. By setting the base width to an appropriate value, the snapback voltage is set higher than the operating voltage to prevent latch-up and to supply power to the control line. When is not applied, the trigger voltage and the snapback voltage are lowered, so that static electricity can be effectively removed, and the first embodiment can be realized with a small area.

  The electrostatic breakdown preventing apparatus of the present invention is useful as an integrated circuit protection.

Configuration diagram of silicon controlled rectifier (SCR) in the first embodiment of the present invention Configuration of conventional silicon controlled rectifier (SCR) V / I characteristic diagram for explaining the first embodiment of the present invention Layout diagram of the first embodiment of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Resistance 2 Resistance 3 Bipolar NPN transistor 4 Bipolar PNP transistor 5 Control transistor 6 Trigger voltage 7 Snapback voltage 8 First conductivity type semiconductor substrate 9 Second conductivity type first well 10 Second conductivity type second well 11 First 1st conductivity type 3rd well 12 1st conductivity type 1st impurity region 13 2nd conductivity type 2nd impurity region 14 2nd conductivity type 3rd impurity region 15 Control line 16 1st pad 17 2nd pad 18 1st 3 pads

Claims (2)

An electrostatic breakdown preventing apparatus for protecting an integrated circuit from an electrostatic application phenomenon in an input / output pad connected to the integrated circuit, wherein the input is absorbed and released by absorbing current injected by applying static electricity from the input / output. Control the trigger voltage of the SCR by the silicon controlled rectifier (SCR) connected between the output pad and other pads in the integrated circuit, and when power is supplied to the integrated circuit And the trigger means has a transistor for controlling the trigger voltage of the silicon controlled rectifier. A first well of a second conductivity type in a semiconductor substrate of the first conductivity type; a third well of a second conductivity type adjacent to the second well of the first conductivity type in the first well; and the second well A first impurity region and a second impurity region of a second conductivity type formed in the well; a control line formed on the semiconductor substrate between the first impurity region and the second impurity region; and the third well The first impurity region, the second impurity region, the second well, and the metal line are connected to each other through the contact hole. The electrostatic breakdown preventing apparatus according to claim 1, wherein the electrostatic breakdown preventing apparatus is connected.

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