JP2006054326A - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to form a barrier metal film while reducing wiring resistance and improving yield. <P>SOLUTION: The manufacturing method of semiconductor device comprises an insulating layer formation process for forming an insulating layer on the base body (S102-S108), an opening formation process for forming an opening in the insulating layer (S110), a first barrier metal film formation process for forming the first barrier metal film on the insulating layer top and in the opening by using PVD method (S116), a second barrier metal film formation process for forming the second barrier metallic film on it by using CVD method (S118), a third barrier metal film formation process for forming the third barrier metal film on it by using PVD method (S120), a deposition process for depositing a conductive material on it (S112, S124). The sum total film thickness of the first, the second, and the third barrier metal films to be formed are made smaller than 8 nm. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to a metal wiring layer structure in a semiconductor integrated circuit.

  Copper (Cu) wiring having low resistance and high electromigration (EM) resistance is expected as a highly reliable material for highly integrated and miniaturized LSI wiring.

As semiconductor integrated circuits become highly integrated and operate at higher speeds, the delay of signals propagating through wiring between semiconductor elements has been governed by the operating speed of integrated circuits.
In particular, recently, in order to achieve high-speed performance of such LSI, there has been a movement to replace the wiring technology from conventional aluminum (Al) alloy to low resistance Cu or Cu alloy (hereinafter collectively referred to as Cu). It is out. Since Cu is difficult to finely process by the dry etching method frequently used in the formation of Al alloy wiring, Cu film is deposited on the insulating film subjected to the groove processing, and other than the portion embedded in the groove A so-called damascene method, in which the Cu film is removed by chemical mechanical polishing (CMP) to form a buried wiring, is mainly employed. In general, a Cu film is formed by forming a thin seed layer by sputtering or the like and then forming a laminated film having a thickness of about several hundreds of nanometers by electrolytic plating.

  Further, since Cu easily diffuses into the Si-based insulating film, the periphery of Cu must be covered with a diffusion preventing film. Therefore, as described above, when a Cu wiring is formed using the damascene process, titanium (Ti), tantalum (Ta), tungsten (W) is formed in an opening pattern such as a groove or a hole formed in the insulating film. Alternatively, a refractory metal film such as a nitride or an alloy thereof is formed. In general, after forming a refractory metal film, Cu is buried and a barrier metal film made of a refractory metal film for preventing Cu diffusion is disposed around the Cu wiring.

Further, recently, it has been studied to use a low dielectric constant (low-k) film having a low relative dielectric constant as an interlayer insulating film. That is, by using a low-k film having a relative dielectric constant k of 3.5 or less from a silicon oxide film (SiO ₂ film) having a relative dielectric constant k of about 4.2, the parasitic capacitance between wirings is reduced. It has been tried. A method of manufacturing a semiconductor device having a multilayer wiring structure in which such a low-k film and a Cu wiring are combined is as follows.

FIG. 28 is a process sectional view showing a method of manufacturing a semiconductor device having a multilayer wiring structure in which a conventional low-k film and a Cu wiring are combined.
In FIG. 28, a method for forming a device portion or the like is omitted.
In FIG. 28A, a first insulating film 221 is formed on a substrate 200 made of a silicon substrate by a method such as CVD (chemical vapor deposition).
In FIG. 28B, a groove structure (opening H) for forming a Cu metal wiring or a Cu contact plug is formed in the first insulating film 221 by a photolithography process and an etching process.
In FIG. 28C, a barrier metal film 240, a Cu seed film and a Cu film 260 are formed in this order on the first insulating film 221, and annealed at a temperature of 150 to 400 ° C. for about 30 minutes.
In FIG. 28D, the Cu film 260 and the barrier metal film 240 are removed by CMP and planarized to form a Cu wiring in the opening H that is a groove.
In FIG. 28E, a second insulating film 281 is formed after the surface of the Cu film 260 is subjected to reducing plasma treatment.
Furthermore, when forming multilayer Cu wiring, it is common to repeat these processes and to laminate. Here, most of the first insulating film 221 and the second insulating film 281 are low-k films.

  Here, since such a barrier metal film has been conventionally formed by a physical vapor deposition (PVD) method, the film formation rate on the side wall of the groove or hole pattern is significantly reduced. As a result, in order to secure a film thickness on the side wall portion that can prevent diffusion also on the side wall portion, it is necessary to form a film thickness of about 15 nm or more on the substrate surface.

In next-generation devices, the use of a low dielectric constant film as an interlayer insulating film, in particular, a porous low dielectric constant (p-lowk) film having pores is being studied in order to lower the dielectric constant. In other words, the development of low-k film materials having a relative dielectric constant k of 2.5 or less has been promoted, and many of these are porous materials having pores in the material. As Cu wiring is further miniaturized in the future, it is essential to reduce the thickness of the barrier metal, which has a higher resistance than Cu. In order to form an ultra-thin barrier metal film, CVD atomic layer vapor deposition (ALD) has been studied.
There is a Deposition method (for example, see Non-Patent Documents 1 and 2). This method is a method of performing film formation at the atomic layer level by alternately supplying source gases.

FIG. 29 is a gas supply flow diagram showing an example of barrier metal film formation by the ALD method.
First, a tantalum (Ta) raw material is supplied. For example, it will be described with reference to tantalum chloride (TaCl _5). At this time, a certain amount or more is not adsorbed due to the self-limiting effect. Next, purging is performed with argon (Ar). Subsequently, by supplying ammonia (NH ₃ ), tantalum nitride (TaN) as a barrier metal is formed. Finally, purge is performed with Ar. This series of operations is defined as one cycle, and film formation is performed by repeating a cycle corresponding to the required film thickness.
FIG. 30 is a conceptual diagram for explaining how a TaN film is formed in the ALD method.
In FIG. 30A, TaR20 (Ta compound) is adsorbed on the substrate 10 by supplying TaR20 (Ta compound). Further, TaR 20 that is not adsorbed floats around the base 10.
In FIG. 30B, the floating TaR 20 is replaced by supplying Ar.
In FIG. 30C, by supplying NH ₃ , TaR 20 adsorbed on the substrate 10 is reduced to form a TaN film 22.

In addition, as a technique related to the barrier metal film, when the barrier metal film is formed by a chemical vapor deposition (CVD) method, a film forming gas for the barrier metal film in the porous low dielectric constant (p-lowk) film In order to prevent diffusion, a first barrier metal film is formed at one end by the PVD method, and then a second barrier metal film is formed by the CVD method. Further, a technique for forming a third barrier metal film by the PVD method is disclosed (for example, see Patent Document 1).
Japanese Patent Application Laid-Open No. 2004-6541 “Atomic layerdeposition of metal and nitride thin films: Current research efforts and applications for semiconductor device processing”, J. Vac. Sci. Technol. B21 (6), 2003, p2231-2261 “Atomic layerdeposition for nanoscale Cu metallization”, Advanced Metallization Conference 2003Conference Proceedings AMC XIX 2004 Materials Research Society p713-722

  As described above, when a barrier metal film using a refractory metal that prevents Cu from diffusing into the Si-based insulating film is formed by the PVD method, the film formation rate on the sidewall of the groove or hole pattern is significantly reduced. To do. As a result, in order to secure a film thickness on the side wall portion that can prevent diffusion also on the side wall portion, it is necessary to form a film thickness of about 15 nm or more on the substrate surface. Similarly, in order to secure the film thickness at the side wall, the film is formed at a rate higher than the film forming rate at the side wall, and the film is formed to be thicker than necessary at the bottom of the groove or hole (bottom film formation). Speed >> Side film forming speed). Since the resistance value of the barrier metal film using such a refractory metal is remarkably higher than that of Cu, the thick barrier metal film is formed on each bottom portion which becomes the connection surface between the groove and the hole. There was a problem that the connection resistance was increased.

On the other hand, when the film is formed by the CVD method including the ALD method, the difference between the bottom film forming rate and the side wall film forming rate is small compared to the case where the film is formed by the PVD method. Therefore, a thin film formation of a barrier metal film by a CVD method has been studied. However, a barrier metal film using a refractory metal formed by a CVD method has poor wettability with Cu.
FIG. 31 is a cross-sectional view of a semiconductor device in which a barrier metal film using a refractory metal is formed by a CVD method.
In FIG. 31, there is a barrier metal formed by the CVD method between the upper portion of the via connecting the lower layer wiring (M1) and the upper layer wiring (M2) and the lower portion of the upper layer wiring (M2). However, the state where it is separated from the upper wiring (M2) side and is not in close contact is shown. As described above, the barrier metal film using a refractory metal film formed by the CVD method has poor wettability with Cu, so that the adhesion is poor and the connection yield between the groove (upper layer wiring) and the hole (via) is obtained. There was a problem that it was not possible.

Here, as described above, Patent Document 1 discloses a technique of sandwiching the second barrier film formed by the CVD method between the first and third barrier films formed by the PVD method. Although it seems that the problem of wettability with Cu can be solved by sandwiching the CVD film with the PVD film, the barrier metal film cannot be thinned only by sandwiching the CVD film with the PVD film.
FIG. 32 is a diagram illustrating a state in which Cu is diffused through a barrier metal film formed to a thickness of 10 nm by the PVD method.
FIG. 32 shows that Cu is diffused into the insulating film on the side wall of the insulating film even when a laminated film of TaN and Ta is formed with a value of 10 nm on the substrate. Although Cu is deposited by a plating method, it can be seen that Cu diffuses into the insulating film even when a 10 nm thick layer of TaN and Ta is formed in terms of the molecular size of the plating solution. As described above, in order to prevent diffusion even at the side wall portion using the PVD film, it is necessary to form a film thickness of about 15 nm or more on the substrate surface. In Patent Document 1, the PVD film is formed so as not to diffuse the deposition gas by the CVD method into the insulating film. Here, in the film thickness of the barrier metal film such that the plating solution having molecules larger than the deposition gas diffuses, the deposition gas having molecules smaller than the plating solution also diffuses. It can be seen that it is assumed that a barrier metal film having a film thickness is formed by the PVD method. Therefore, the technique of Patent Document 1 cannot reduce the wiring resistance by reducing the thickness of the barrier metal film.

  An object of the present invention is to overcome the above-described problems and to form a barrier metal film with improved yield while reducing wiring resistance.

A method for manufacturing a semiconductor device of the present invention includes:
An insulating film forming step of forming an insulating film on the substrate;
An opening forming step of forming an opening in the insulating film;
A first barrier metal film forming step of forming a first barrier metal film on the insulating film and in the opening using a physical vapor deposition (PVD) method;
A second barrier metal film forming step of forming a second barrier metal film on the first barrier metal film using a chemical vapor deposition (CVD) method;
A third barrier metal film forming step of forming a third barrier metal film on the second barrier metal film using a PVD method;
A deposition step of depositing a conductive material on the third barrier metal film;
With
The total thickness of the first, second and third barrier metal films formed on the insulating film is formed to be smaller than 8 nm.

As will be described later, when the CVD film is sandwiched between PVD films and the total film thickness of the first, second and third barrier metal films is 8 nm or more, the yield between the wirings after a long time has passed. The inventors found that the remarkably decreased.
Therefore, by forming the total film thickness of the first, second and third barrier metal films so as to be smaller than 8 nm, the yield between the wirings can be maintained even after a long time has elapsed.

  Further, the second barrier metal film forming step is characterized in that the second barrier metal film formed on the insulating film is formed to have a thickness smaller than 2 nm.

As will be described later, the inventors have found that the wiring resistance (particularly, via resistance) increases when the CVD film is 2 nm or more.
Therefore, by forming the second barrier metal film so that the film thickness is smaller than 2 nm, the wiring resistance (particularly, via resistance) can be suppressed low.

  Further, the second barrier metal film is formed so as to be thinner than any of the first and third barrier metal films.

  By forming the second barrier metal film so as to be thinner than both the first and third barrier metal films, an effective PVD film can be obtained while reducing the thickness. Can be formed.

  In the second barrier metal film forming step, if an atomic layer vapor deposition (ALD) method is used as the CVD method, it is particularly effective in forming a film having a thickness of less than 2 nm.

  The first, second, and third barrier metal films are made of tantalum (Ta), titanium (Ti), tungsten (W), Ta compound, Ti compound, and W compound, respectively. It is particularly effective when used.

  The method for forming a semiconductor device further includes a diffusion preventing film forming step of forming a diffusion preventing film on the wall surface of the opening before the first barrier metal film forming step.

  By forming the diffusion preventing film on the wall surface of the opening, it is possible to prevent diffusion of Cu and the CVD barrier metal film on the wall surface.

  Furthermore, in the diffusion preventing film forming step, it is particularly effective to form the diffusion preventing film so that the film thickness is 20 nm or less.

  In the diffusion prevention film forming step, it is easy to form the diffusion prevention film using the CVD method, and it is particularly effective.

  Furthermore, it is particularly effective to use a silicon compound as the material of the diffusion preventing film in the diffusion preventing film forming step.

  It is effective to use at least one of silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbonate (SiOC), and silicon nitride (SiN) as the silicon compound.

  Further, if the insulating film is a low dielectric constant film having a relative dielectric constant of 2.5 or less, it is more preferable for further miniaturization.

  The resistance can be reduced by using copper (Cu) as the conductive material.

The semiconductor device of the present invention is
A first conductive film using a conductive material;
A second conductive film using the conductive material formed on the first conductive film;
An insulating film using an insulating material, disposed on a side surface of the second conductive film;
Using a barrier metal material, a chemical vapor deposition (CVD) method formed between the second conductive film and the insulating film and between the first and second conductive films is used. A barrier metal film having a formed CVD film and two PVD films formed to sandwich the CVD film using a physical vapor deposition (PVD) method;
With
The barrier metal film is characterized in that a total film thickness of the CVD film and the two PVD films is smaller than 6.2 nm between the first and second conductive films.

  The second conductive film deposits the conductive material in an opening provided in the insulating film. Further, as will be described later, when the total thickness of the barrier metal film is less than 8 nm on the surface of the insulating film and the CVD film is less than 2 nm, the yield between the conductive films is increased even after a lapse of time while keeping the wiring resistance low. The inventors have found that it can be maintained. That is, it can be said that it is particularly effective when the total film thickness of the two PVD films is 6 nm or less on the surface of the insulating film. Here, the PVD film has a film thickness of about 70% of the surface of the insulating film at the bottom of the opening. Therefore, when the total film thickness of the CVD film and the two PVD films is formed to be smaller than 6.2 nm between the first and second conductive films corresponding to the bottom of the opening of the second conductive film. Even after a lapse of time, the yield between the conductive films can be maintained, which is particularly effective.

  Further, in the barrier metal film, the CVD film is formed thinner than any of the two PVD films.

  The CVD film is formed thinner than any of the two PVD films, so that an effective PVD film can be formed while reducing the thickness.

  The semiconductor device further includes a diffusion prevention film formed between the barrier metal film and the insulating film.

  As described above, by providing a diffusion prevention film between the barrier metal film and the insulating film, it is possible to prevent the diffusion of Cu and the CVD barrier metal film on the wall surface.

  According to the present invention, the total film thickness of the first, second, and third barrier metal films can be made thinner than before by forming the total film thickness on the substrate during film formation to be smaller than 8 nm. it can. Since the film thickness can be reduced, the wiring resistance can be reduced. Furthermore, by forming the total thickness of the barrier metal film so as to be smaller than 8 nm, the yield between the wirings can be maintained even after a lapse of time.

Embodiment 1 FIG.
In the first embodiment, a case where a via is formed on a lower layer wiring will be described.
FIG. 1 is a flowchart showing the main part of the semiconductor device manufacturing method according to the first embodiment.
In FIG. 1, in the present embodiment, when forming a via on a lower wiring layer, as an interlayer insulating film forming process for via, an SiC film forming process (S102) for forming an SiC film, a porous insulating material A p-lowk film forming step (S104) for forming a p-lowk film using Pt, a helium (He) plasma processing step (S106) for plasma-treating the surface of the p-lowk film, and a SiO ₂ film forming step for forming a SiO ₂ film As a step (S108), an opening forming step (S110) for forming an opening, a pore sealing step (S112) as a diffusion preventing film forming step, an etch back step (S114), and a barrier metal film forming step, First barrier metal film forming step by PVD method (S116), second barrier metal film forming step by CVD method (S118), PVD method A third barrier metal film forming step (S120), and a conductive material depositing step for depositing a conductive material to be a via forming step, a seed film forming step (S122), a plating step (S124), and a planarizing step. A series of steps (S126) is performed.

FIG. 2 is a diagram showing the relationship between the via resistance and the cumulative probability due to the difference in the thickness of the TaN film by the ALD method.
Here, first, the inventors investigated the relationship between the via resistance (cumulative probability) due to the difference in film thickness of the TaN film formed by the CVD method, particularly the ALD method, and the cumulative probability (cumulative probability). It was. A sample structure having an upper and lower wiring width of 160 nm was used. As a comparison object, measurement was also performed when a TaN film of 10 nm and a Ta film of 15 nm were formed on the substrate during film formation by the PVD method. As shown in FIG. 2, the via resistance is higher than that of the PVD film having a large film thickness when the ALD film is 2 nm (value of 2 nm or more and less than 3 nm) on the substrate when the ALD film is formed. It can be seen that the via resistance is lower than that of the PVD film having a large film thickness at 1 nm (value of 1 nm or more and less than 2 nm) on the substrate during film formation. In other words, the inventors have found that when an ALD film is used as a barrier metal film, an increase in via resistance can be suppressed by using a film thickness smaller than 2 nm (less than 2 nm) on the substrate during film formation.

Furthermore, the inventors have found that an increase in via resistance can be reduced by sandwiching a barrier metal film by a CVD method with a barrier metal film by a PVD method. Here, a sample structure having an upper and lower wiring width of 5 μm was used. The resistance value is a value obtained by dividing the total resistance of 15000 chain patterns by the number of connected vias.
FIG. 3 is a diagram showing the relationship between the via resistance and the cumulative probability due to the difference in the configuration of the barrier metal film.
In FIG. 3A, a Ta film formed by PVD is formed on the Cu side (upper side) embedded in the groove in a stacked film of a TaN film formed by CVD (here, in particular, ALD) and a Ta film formed by PVD. Shows the case.
In FIG. 3B, a case where a Ta film by the PVD method is formed on the lower wiring side (lower side) in a laminated film of a TaN film by the CVD (here, particularly, ALD) method and a Ta film by the PVD method is shown. Show.
In FIG. 3C, in a stacked film of a TaN film by CVD (here, in particular, ALD) and a Ta film by PVD, TaN by ALD is sandwiched between two Ta films by PVD (sandwich) (Sandwich) structure).
3D, in the case of the structure of FIG. 3A, in the case of the structure of FIG. 3B, in the case of the structure of FIG. 3C, and further in the case of only a film by the PVD method (PVD), The relationship between the via resistance and the cumulative probability is compared in the case of only the film by the ALD method (ALD only).
As shown in FIG. 3D, the sandwich structure in which TaN by ALD method is sandwiched between Ta films by PVD method has a smaller via resistance than the case of only the film by ALD method. It can be seen that there is less change than providing.

  Here, in the sample structure described in FIG. 2, the upper and lower wiring widths were 160 nm. In this case, since the stress generated in the via from the wiring side is small, the connection yield is obtained even with 1 nm of ALD alone, and the effect of reducing the via resistance is obtained by reducing the interface resistance. However, when the upper and lower connection wiring width in which the stress generated in the via from the wiring side becomes large is 5 μm, for example, there is a problem that the connection yield cannot be secured because the adhesion between the wiring / via is low by ALD alone. . Therefore, in FIG. 3D, when only the film by the ALD method is used (ALD only), the via resistance increases rapidly. Therefore, the inventors considered that the cause of the decrease in adhesion was due to the wettability between the ALD-TaN / Cu materials, and found that the problem was solved by sandwiching with PVD-Ta as a wetting layer. By sandwiching between the PVD films, the via resistance can be reduced not only when the stress generated in the via from the wiring side is large, but also when the upper and lower wiring width is small and the stress generated in the via from the wiring side is small.

  As described above, in FIG. 3, the upper and lower connection wiring widths forming the via chain pattern are thicker than those in FIG. In FIG. 3, this resistance value is a value obtained by dividing the total resistance of 15000 chain patterns by the number of connected vias. For this reason, the via resistance has a value including some wiring additional resistance. Therefore, the resistance value in FIG. 3D is different from that in FIG. 2, but this is a difference in wiring resistance due to the upper and lower wiring widths.

FIG. 4 is a diagram showing the relationship between the via yield of the barrier metal film having a sandwich structure and the stress time.
Furthermore, the inventors investigated the relationship between the via yield of the barrier metal film having a sandwich structure and the stress time. In FIG. 4, the TaN film formed by the ALD method has a thickness of 1 nm (a value not less than 1 nm and less than 2 nm). A PVD-Ta film with a thickness of 5 nm (a value between 5 nm and less than 6 nm) on the Cu side (upper side) and a PVD-Ta film with a thickness of 2 nm (a value between 2 nm and less than 3 nm) on the lower wiring side (lower side) When the ALD-TaN film of 1 nm is sandwiched (total film thickness is 8 nm or more), PVD-Ta film of 2 nm (value of 2 nm or more and less than 3 nm) and lower wiring side on the Cu side (upper side) embedded in the groove When the 1 nm ALD-TaN film is sandwiched between a PVD-Ta film of 5 nm (value of 5 nm or more and less than 6 nm) on the (lower side) (total film thickness is 8 nm or more), the time for applying stress elapses. It can be seen that the via yield decreases significantly as the time elapses. On the other hand, a PVD-Ta film of 2 nm (value of 2 nm or more and less than 3 nm) on the Cu side (upper side) embedded in the groove and a PVD-Ta of 2 nm (value of 2 nm or more and less than 3 nm) on the lower wiring side (lower side) When the ALD-TaN film of 1 nm is sandwiched between Ta films (total film thickness is 5 nm (having a value of 5 nm or more and less than 8 nm)), the via yield is stable even after the time for applying stress. I understand that. In other words, the total film thickness of the PVD-Ta film on the Cu side (upper side), the PVD-Ta film on the lower wiring side (lower side), and the intermediate ALD-TaN film embedded in the groove is The inventors found that when the thickness is smaller than 8 nm, it is possible to suppress a decrease in via yield.

  Therefore, the laminated structure of the refractory metal film formed by using both the PVD method and the CVD method is a PVD method in which a thin film refractory metal film having a thickness of less than 2 nm is formed on the substrate formed by using the CVD method. A barrier metal film using a refractory metal by CVD and Cu is formed by forming a three-layer structure sandwiched between thin film refractory metals formed by using a thin film and making the total film thickness smaller than 8 nm on the substrate during film formation. And the connection yield between the groove (lower layer wiring) and the hole (via) can be secured.

FIG. 5 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 5 shows from the SiC film formation step (S102) to the SiO ₂ film formation step (S108) in FIG. Subsequent steps will be described later.

In FIG. 5A, as a SiC film forming step, a base silicon carbide (SiC) film having a film thickness of 50 nm using SiC is deposited on the substrate 200 on which the lower wiring layer is formed by a CVD method. 275 is formed. Here, the film is formed by the CVD method, but other methods may be used. The SiC film 275 also has a function as an etching stopper. Since it is difficult to generate the SiC film, a silicon carbonate (SiOC) film may be used instead of the SiC film. Alternatively, a silicon carbonitride (SiCN) film or a silicon nitride (SiN) film can be used. As the substrate 200, for example, a substrate such as a silicon wafer having a diameter of 300 mm is used. The lower wiring layer is an interlayer insulating film for a lower wiring in which a base SiC film 212, a p-lowk film 220, and a cap SiO ₂ film 222 are formed on the device layer 210, a barrier metal film 240, a seed film 250, and Cu. A film 260 is formed. Contact plugs or other layers may be formed on the device layer 210.

In FIG. 5B, as a porous low-k (p-lowk) film forming step, a porous insulating property is formed on the SiC film 275 formed by the SiC insulating film forming step formed on the substrate 200. A p-lowk film 280 using a material is formed with a thickness of 250 nm. By forming the p-lowk film 280, an interlayer insulating film having a relative dielectric constant k lower than 3.5 can be obtained. As a material of the p-lowk film 280, for example, porous methylsilsesquioxane (MSQ) can be used. As the formation method, for example, a SOD (spin on selective coating number and name, name of agent) method of forming a thin film by spin-coating a solution and heat-treating can be used. For example, the film is formed at a rotation speed of the spinner of 900 min ⁻¹ (900 rpm). The wafer is baked on a hot plate at a temperature of 250 ° C. in a nitrogen atmosphere, and finally cured on a hot plate at a temperature of 450 ° C. in a nitrogen atmosphere for 10 minutes. A porous insulating film having a predetermined physical property value can be obtained by appropriately adjusting the MSQ material, formation conditions, and the like. For example, the density is 0.7 g / cm ³ and the relative dielectric constant k is 1.8. The composition ratio of Si, O, and C in the low-k film is p-lowk having physical properties in which Si is in the range of 25 to 35%, O is in the range of 45 to 57%, and C is in the range of 13 to 24%. A membrane 280 is obtained.

Then, as a He plasma treatment process, the surface of the p-lowk film 280 is modified by helium (He) plasma irradiation. By modifying the surface by He plasma irradiation, the adhesion between the p-lowk film 280 and a CVD-SiO ₂ film 284 as a cap film, which will be described later, formed on the p-lowk film 280 can be improved. . For example, the gas flow rate is 1.7 Pa · m ³ / s (1000 sccm), the gas pressure is 1000 Pa, the high frequency power is 500 W, the low frequency power is 400 W, and the temperature is 400 ° C. When the cap CVD film is formed on the p-lowk film, it is effective to improve the adhesion with the cap CVD film by performing plasma treatment on the surface of the p-lowk film. As types of plasma gas, ammonia (NH ₃ ), nitrous oxide (N ₂ O), hydrogen (H ₂ ), He, oxygen (O ₂ ), silane (SiH ₄ ), argon (Ar), nitrogen (N ₂ ) Among these, He plasma is particularly effective because it causes little damage to the p-lowk film. The plasma gas may be a mixture of these gases. For example, it is effective to use He gas mixed with other gases.

In FIG. 5 (c), as the SiO ₂ film forming step, said after the He plasma treatment, as a cap film, the SiO ₂ by a thickness of 50nm is deposited on the p-low k film 280 by the CVD method, SiO ₂ A film 284 is formed. By forming the SiO ₂ film 284, the p-lowk film 280 that cannot be directly subjected to lithography can be protected, and a pattern can be formed in the p-lowk film 280. Such cap CVD films include SiO ₂ films, SiC films, SiOC films, SiCN films, etc., but from the viewpoint of reducing damage, the SiO ₂ film is excellent, and from the viewpoint of reducing the dielectric constant, the SiOC film has improved breakdown voltage. From the viewpoint, the SiC film and the SiCN film are excellent. Furthermore, it is possible to use SiO ₂ film and the SiC film laminated film of, or SiO ₂ film and the SiCO film laminated film of, or a laminated film of SiO ₂ film and SiCN film. Furthermore, a part or all of the cap CVD film may be removed by chemical mechanical polishing (CMP) in a planarization step described later. The dielectric constant can be further reduced by removing the cap film. The thickness of the cap film is preferably 10 nm to 150 nm, and 10 nm to 50 nm is effective in reducing the effective relative dielectric constant.

  In the above description, the interlayer insulating film may not be a low-k film having a relative dielectric constant of 3.5 or less, but is a low-k film, particularly a relative dielectric constant k of 2.5 or less, This is particularly effective when a porous p-lowk film having a rate of 30% or more is included.

FIG. 6 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 6 shows from the opening forming step (S110) to the etch-back step (S114) in FIG. Subsequent steps will be described later.

In FIG. 6A, as an opening forming process, an opening 150 which is a wiring groove structure for producing a damascene wiring is formed in the SiO ₂ film 284 and the p-lowk film 280 by a lithography process and a dry etching process. . An exposed SiO ₂ film 284 and a p-lowk film positioned under the exposed SiO ₂ film 284 with respect to the substrate 200 on which the resist film is formed on the SiO ₂ film 284 through a lithography process such as a resist coating process and an exposure process (not shown). The opening 150 may be formed by removing 280 by anisotropic etching using the underlying SiC film 275 as an etching stopper. By using the anisotropic etching method, the opening 150 can be formed substantially perpendicular to the surface of the substrate 200. For example, as an example, the opening 150 may be formed by a reactive ion etching method.

In FIG. 6B, as a pore sealing process which is an example of a diffusion prevention film forming process, an opening using SiC is formed on the surface of the opening 150 and the SiO ₂ film 284 formed by the opening forming process by a CVD method. The SiC film is deposited until the film thickness on the partial wall surface reaches 5 nm, and the SiC film 230 is formed. Here, the film is formed by the CVD method using high-density plasma from the viewpoint of ease of formation, but other methods may be used. In order to reduce the film thickness of a barrier metal film, which will be described later, in particular, the first barrier metal film by the PVD method, a p-lowk film of a deposition gas when forming the second barrier metal film by the CVD method (ALD method) It becomes difficult to prevent diffusion to 280. Further, since the total film thickness of the barrier metal films formed by the PVD method and the CVD method is less than 8 nm, it is difficult to prevent diffusion of Cu deposited thereafter into the p-lowk film 280 only with the barrier metal film. . Therefore, by forming the SiC film 230 serving as a sidewall on the wall surface of the p-lowk film 280, diffusion of the CVD film forming gas into the p-lowk film 280 and the Cu p-lowk film 280 together with the barrier metal film. Can be prevented from spreading.

FIG. 7 is a conceptual diagram of a CVD apparatus.
In FIG. 7, in the apparatus 350, the substrate 10 that has been processed up to the previous process on the substrate 200, more specifically, the substrate 10 is controlled to a predetermined temperature that also serves as the lower electrode 310 inside the chamber 300. Place on the substrate holder. Then, a deposition gas is supplied into the chamber 300 from the upper electrode 320. Plasma is generated using a high-frequency power source between the upper electrode 320 and the lower electrode 310 inside the chamber 300 evacuated to a predetermined film forming pressure by the vacuum pump 330. Then, the substrate 10 is exposed to a gas plasma atmosphere, and chemical vapor deposition is performed to form SiC on the inner surface of the opening 150 and the upper surface of the substrate 10, thereby forming the SiC film 230. By forming the SiC film 230 with a thickness of 5 nm, it is possible to increase the cross-sectional area of wirings and vias formed thereafter. Since the cross-sectional area of the wiring and via can be increased, an increase in wiring resistance and via resistance can be prevented. Therefore, it can be prevented that the wiring resistance and the via resistance are increased and the operation speed of the semiconductor device is lowered. Further, by preventing an increase in wiring resistance and via resistance, it is possible to prevent a high power supply voltage from being required for the operation of the semiconductor device and to prevent an increase in power consumption. By forming it thin, an increase in dielectric constant as an interlayer insulating film can be prevented.

  In particular, when the relative dielectric constant k is 2.5 or less, it is desirable that the sidewall of the p-lowk film exposed at the via portion is covered with a CVD film. The reason is that when the relative dielectric constant is 2.5 or less, it is often a porous film, and it is effective to perform pore sealing on the side wall of the Cu wiring. This is particularly effective when a barrier metal film is formed by a CVD method including an ALD method. The film thickness of the CVD film is 5 nm on the wall surface here, but it is desirable to form it on the substrate to be 20 nm or less. If it is too thick, the film thickness on the wall surface becomes thick and the wiring width becomes narrow. As a result, since it affects the wiring resistance, it is desirable to increase the cross-sectional area of the via serving as the wiring or connection wiring to reduce the wiring resistance or via resistance (connection resistance). As the kind of the pore sealing CVD film, a silicon compound, particularly a SiC film, a SiCN film, a SiCO film, or a SiN film, which is a nitride film or a carbonized film, is desirable. In particular, a SiC film is optimal from the viewpoint of a low dielectric constant.

In FIG. 6C, as the etch back process, the remaining SiC film 230 formed on the bottom surface of the opening 150 and the SiC film 230 on the SiO ₂ film 284 are removed by etch back. Then, when the SiC film 230 is removed by etch back, the remaining SiC film 275 formed on the bottom surface of the opening 150 is simultaneously removed by etch back. By removing the remaining SiC film 275 formed on the bottom surface of the opening 150, the SiC film 275 and the SiC film 230 are not deposited on the bottom surface of the opening 150. Decreasing the conductivity with the conductive material can be prevented.

FIG. 8 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 8 shows from the first barrier metal film forming step (S116) to the third barrier metal film forming step (S120) in FIG. Subsequent steps will be described later.
In FIG. 8A, as a first barrier metal film forming step, an opening 150 in which an SiC film 230 is formed on the sidewall and a barrier metal film 241 using a barrier metal material are formed on the surface of the SiO ₂ film 248. Tantalum nitride (TaN) is deposited on the substrate so as to have an average film thickness of 2.5 nm in a sputtering apparatus using a sputtering method which is one of physical vapor deposition (PVD) methods, and a barrier is formed. A metal film 241 is formed.

FIG. 9 is a conceptual diagram of a sputtering apparatus.
The inside of the chamber 700 is evacuated by a vacuum pump 730 to form a high vacuum, and argon ions collide with the target 720 connected to the cathode in the high vacuum, and molecules (in this case, TaN) constituting the target 720 are allowed to collide. The substrate is knocked out by a sputtering phenomenon and is deposited on the substrate 200 connected to the anode at the opposite position, more specifically, the substrate 10 that has been subjected to the process up to the previous step on the substrate. Sputtering may be performed in an atmosphere containing nitrogen (N ₂ ) gas using a Ta target.

By forming the barrier metal film 241 that is a PVD film on the Cu film 260 serving as the lower layer wiring, the wettability can be improved and the adhesion between the lower layer wiring and the via can be improved.
Here, as the first barrier metal film, the film thickness (top film thickness) deposited on the substrate of the barrier metal film 241 is desirably 3 nm or less. In particular, about 2.5 nm (for example, 2 to 3 nm) is even better. Here, as described above, the total of PVD films sandwiching the ALD film formed in the next step is desirably 6 nm or less. On the other hand, there is a limit to achieving a thin film that can be controlled using the PVD method. Therefore, a controllable thin film using the PVD method can be formed by setting the film thickness to be deposited on the substrate to 3 nm or less on one side. By depositing a barrier metal film 241 of 3 nm or less on the substrate, the film thickness (bottom film thickness) on the Cu film 260 (that is, the bottom of the opening 150) serving as the lower layer wiring is 60 to 70 of the top film thickness. That is, a barrier metal film 241 having a thickness of 1.8 to 2.1 nm is formed on the bottom of the opening 150. Therefore, the film thickness (bottom film thickness) deposited on the bottom of the opening 150 of the barrier metal film 241 is desirably 2.1 nm or less.

  In FIG. 8B, as a second barrier metal film forming step, a barrier metal film 242 using a barrier metal material is formed on the first barrier metal film 241. Here, the average film thickness of TaN is smaller than 2 nm on the substrate in the apparatus using a CVD method including atomic layer vapor deposition (ALD method or atomic layer chemical vapor deposition: ALCVD method). Thus, a barrier metal film 242 is formed. In particular, 1 nm (a value of 1 nm or more and less than 2 nm) is more preferable.

FIG. 10 is a diagram showing a supply flow of each gas in the TaN film formation step.
Here, a TaN film is formed as the barrier metal film 242. First, pentadiethyl tantalum (Ta [N (C ₂ H ₅ ) ₂ ] ₅ ) is used as a metal raw material for forming the second barrier metal film, and is an example of a reactive species that reacts with the metal raw material, Ammonia (NH ₃ ) is used as the reducing gas for the metal raw material, and hydrogen (H ₂ ) is used as the purge gas. By using H ₂ as the purge gas, the following reactivity can be enhanced. Furthermore, since H ₂ can increase the purity, it is suitable for cleaning.
As a Ta [N (C ₂ H ₅ ) ₂ ] ₅ supply step, Ta [N (C ₂ H ₅ ) ₂ ] ₅ is supplied for 1 s. Thereafter, as an H ₂ supply step, H ₂ is supplied for 1 s and purged. Then, the NH ₃ supply process, the NH ₃ 1s supplies. Then, as the H ₂ supply step, H ₂ is supplied for 1 s and purged. This process is defined as one cycle, and 10 cycles are supplied at a film forming temperature of 300 ° C.

FIG. 11 is a diagram showing a schematic configuration of the ALD apparatus.
In FIG. 11, inside the chamber 600, on the substrate 200, more specifically, on the substrate holder (wafer stage) 610 controlled to a predetermined temperature on the substrate 10 that has been processed up to the previous step. Install in. Then, gas is supplied into the chamber 600 from above. Further, the vacuum pump 630 is evacuated so that the inside of the chamber 600 becomes a predetermined pressure. Solid Ta [N ((C ₂ H ₅ ) ₂ ] ₅ contained in the container 650 is heated to 50 to 70 ° C. The carrier is contained in the heated and melted Ta [N (C ₂ H ₅ ) ₂ ] ₅ . By supplying H ₂ gas as gas, Ta [N (C ₂ H ₅ ) ₂ ] ₅ gasified together with H ₂ can be supplied to the chamber 600 by a kind of bubbling method.

Here, the amount of gas, _Ta for _{[N (C 2 H 5)} 2] 5, 0.5Pa · m 3 /s(300sccm)~1.68Pa · m 3 / s (1000sccm) is desirable. For ^{_{NH 3, 1.68Pa · m 3 /s(1000sccm)~3.36Pa}} · m 3 / s (2000sccm) is desirable. For _{H 2} is ^{purge, 1.68Pa · m 3 /s(1000sccm)~3.36Pa · m} 3 / s (2000sccm) is desirable. The film forming pressure is desirably 665 Pa (5 Torr) or less. The film forming temperature is preferably 250 to 300 ° C.

In forming the TaN film, tantalum chloride (TaCl ₅ ), pentadiemmel tantalum (Ta [N (CH ₃ ) ₂ ] ₅ ), or the like may be used as a metal raw material.

Further, hydrazine (H ₂ NNH ₂ ) or a hydrazine compound such as 1-1 dimethyl hydrazine or 1-2 dimethyl hydrazine may be used as a reducing gas for the metal raw material. By using hydrazine or a hydrazine compound, the reducing action can be made stronger than NH ₃ .

Further, argon (Ar), nitrogen (N ₂ ), or helium (He) may be used as the purge gas. By using Ar, it can be made cheap and easy to handle.

FIG. 12 is a conceptual diagram for explaining an outline of an apparatus including a plurality of chambers.
In FIG. 12, the apparatus 500 has a plurality of chambers 510, 520, and 530. A wafer is set in the cassette chamber 550, and in the transfer chamber 540, a transfer robot transfers or unloads the wafer to each chamber. The first barrier metal film formation, the second barrier metal film formation, and a third barrier metal film formation described later can be performed in the same apparatus capable of vacuum transfer to stabilize the process. it can. Alternatively, the process can be stabilized by performing any two film formations in the same apparatus capable of vacuum transfer. Further, since the processing is performed without exposing the wafer to the outside air, adhesion of particles can be prevented. For example, the first barrier metal film is formed in the chamber 510, and the first barrier metal film is formed in the chamber 520.

FIG. 13 is a diagram illustrating another schematic configuration example of the ALD apparatus.
In the apparatus shown in FIG. 11, gas is supplied from the upper part of the chamber 600 regardless of the size of the substrate 10 and regardless of the gas traveling direction. As shown in FIG. It is more preferable that the gas is uniformly supplied from the shower head 620 to the entire surface of the base 10. Other configurations are the same as those in FIG.

  In FIG. 8C, as a third barrier metal film forming step, a barrier metal film 243 using a barrier metal material is formed on the second barrier metal film 242. Tantalum nitride (TaN) is deposited on the substrate so as to have an average film thickness of 2.5 nm in a sputtering apparatus using a sputtering method which is one of physical vapor deposition (PVD) methods, and a barrier is formed. A metal film 243 is formed. The apparatus configuration is the same as the first barrier metal film forming step in FIG.

By forming the barrier metal film 243 that is a PVD film on the barrier metal film 242 that is an ALD film, the wettability with Cu vias, which will be described later, formed on the barrier metal film 243 is improved. It is possible to improve the adhesion.
Here, as the third barrier metal film, the film thickness (top film thickness) deposited on the base of the barrier metal film 243 is desirably 3 nm or less. In particular, about 2.5 nm (for example, 2 to 3 nm) is even better. As described above, the total of PVD films sandwiching the ALD film is desirably 6 nm or less. On the other hand, there is a limit to achieving a thin film that can be controlled using the PVD method. Therefore, a controllable thin film using the PVD method can be formed by setting the film thickness to be deposited on the substrate to 3 nm or less on one side. By depositing a barrier metal film 243 of 3 nm or less on the substrate, the bottom film thickness (bottom film thickness) of the opening 150 becomes 60 to 70% of the top film thickness. A barrier metal film 243 having a thickness of 1.8 to 2.1 nm is formed. Therefore, the film thickness (bottom film thickness) deposited on the bottom of the opening 150 of the barrier metal film 243 is desirably 2.1 nm or less.

  As described above, the sum of the top film thicknesses of the first, second, and third barrier metal films is desirably smaller than 8 nm. Further, in the ALD film, since the change in film thickness at the formation position is small, it is desirable that the bottom film thickness of the second barrier metal film is also smaller than 2 nm, and the bottom film of the first, second, and third barrier metal films. The total thickness is preferably less than 6.2 nm.

  Further, the PVD method is used while reducing the film thickness by forming the second barrier metal film 242 so as to be thinner than both the first and third barrier metal films. A controllable and effective PVD film can be formed.

In the above description, TaN is used as the barrier metal material. However, the present invention is not limited to this, and tantalum (Ta), titanium (Ti), tungsten (W) and nitride films thereof, or alloys thereof may be used. Absent. For example, in addition to TaN, a tantalum carbonitride (TaCN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium nitride (TiN) or other refractory metal nitride film or carbon nitride film, or tantalum (Ta) Titanium (Ti) or tungsten (W) alone may be used. Alternatively, tantalum silicide (TaSi), titanium silicide (TiSi), WSiN, or the like may be used. Alternatively, a zirconium (Zr) -based barrier metal film may be used. Alternatively, a laminated film made of a plurality of these materials may be used. For example, as a metal raw material for a Ti-based barrier metal film, tetradiethyl titanium (Ti [N (C ₂ H ₅ ) ₂ ] ₄ ), tetradimethyl titanium (Ti [N (CH ₃ ) ₂ ] ₄ ), titanium chloride ( TiCl ₄ ) may be used. As a metal raw material for the W-based barrier metal film, it may be used WF _6.

FIG. 14 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 14 shows from the first seed film formation step (S122) to the plating step (S124) in FIG. Subsequent steps will be described later.
In FIG. 14A, as a seed film formation process, a barrier metal film 243 is formed by using a Cu thin film serving as a cathode electrode in the next electroplating process as a seed film 252 by a physical vapor deposition (PVD) method such as sputtering. Are deposited (formed) on the inner wall of the opening 150 and the surface of the substrate. Here, the seed film 252 was deposited to a thickness of 75 nm.

  Here, the process from the first barrier metal film forming process to the seed film forming process may be either continuous or discontinuous processing (atmospheric exposure).

  In FIG. 14B, as a plating process, a Cu film 262 is deposited on the opening 150 and the substrate surface by electrochemical growth such as electrolytic plating using the seed film 252 as a cathode electrode. Here, a Cu film 262 having a thickness of 300 nm was deposited, and after the deposition, annealing treatment was performed at a temperature of 400 ° C. for 30 minutes.

FIG. 15 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 15 shows the planarization step (S1262) of FIG.
As a planarization step, the Cu film 262, the seed film 252, the barrier metal film 241, the barrier metal film 242, and the barrier metal film 243 that serve as a via layer as a conductive portion deposited on the surface of the SiO ₂ film 284 by the CMP method are polished. By removing, a buried structure as shown in FIG. 15 is formed. The CMP apparatus may be, for example, an orbital system and a Momentum 300 manufactured by Novellus Systems. For example, the CMP load is 1.03 × 10 ⁴ Pa (1.5 psi), the orbital rotational speed is 600 min ⁻¹ (600 rpm), the head rotational speed is 24 min ⁻¹ (24 rpm), and the slurry supply speed is 0.3 L / min ( 300 cc / min), polishing pad is a single layer pad made of polyurethane foam (IC1000 from Rodale), CMP slurry is abrasive-free slurry for Cu (HS-C430-TU made by Hitachi Chemical), colloidal for barrier metal A silica abrasive slurry (HS-T605-8 manufactured by Hitachi Chemical Co., Ltd.) may be used. CMP is performed under the above-described conditions, and the Cu film and the barrier metal film outside the trench are removed to form a damascene Cu wiring.

  16 to 18 are schematic diagrams for explaining the effect of the SiC film 230 formed in the present embodiment. That is, FIG. 16 is a cross-sectional view showing a junction interface between a porous insulating film (MSQ), a barrier metal film, a seed layer serving as a wiring layer, and Cu when a SiC film 230 is not provided as a comparative example. As illustrated in the figure, holes V are formed in the porous insulating film serving as an interlayer insulating film in order to effectively lower the dielectric constant.

  However, when the porous interlayer insulating film and the barrier metal layer are in direct contact as described above, as shown in FIG. 17, the barrier metal diffuses into the interlayer insulating film through the holes. . As a result, the thickness of the barrier metal layer may be reduced, and a continuous thin film state may not be maintained. Then, the metal of the wiring layer (Cu) also diffuses into the interlayer insulating film, and further diffuses into the semiconductor substrate, thereby reducing the reliability of the transistor and the like. In addition, when a metal such as a barrier metal or Cu enters, insulation resistance such as dielectric strength of the interlayer insulating film is reduced, current leakage occurs between adjacent wirings, and reliability of signal propagation by the wiring is reduced. .

  On the other hand, according to the present embodiment, as shown in FIG. 18, by providing SiC film 230 on the surface of the interlayer insulating film, first, diffusion of the barrier metal to the interlayer insulating film can be prevented. . Since the barrier metal can be prevented from diffusing into the interlayer insulating film, the thickness of the barrier metal layer is not reduced, and hence the diffusion of the wiring material into the interlayer insulating film can be prevented.

FIG. 19 is a diagram for explaining the adhesion between TaN and Cu.
FIG. 19B shows a state in which Cu is formed on TaN formed by the ALD method. In FIG. 19B, it can be seen that the wettability between TaN and Cu deposited by the ALD method is poor and Cu is not in close contact. On the other hand, FIG. 19A shows a state in which Cu is formed on TaN formed by the PVD method. Here, in order to focus at the time of photographing, a part where a foreign substance (particle) is attached is photographed, but it can be seen that other surfaces are flat. Therefore, by sandwiching the ALD film between the PVD films as the barrier metal film, adhesion between the lower wiring layer Cu and the via side Cu between the barrier metal film can be improved.

FIG. 20 is a diagram showing the relationship between via resistance and cumulative establishment in the present embodiment.
From FIG. 20, it is possible to compare the connection resistance and the connection yield between the hole pattern (via) and the upper and lower groove pattern (upper layer wiring or lower layer wiring) due to the difference in the configuration of the barrier metal film. When a refractory metal film using a conventional PVD method is formed, the connection resistance value is high (large) because the film thickness of the via bottom (trench bottom) is thick. On the other hand, when the CVD method is used, since the film thickness of the refractory metal film at the bottom of the trench can be reduced, the connection resistance value is low (small), but the wettability with Cu is inferior. Yield deteriorates. When the three-layer laminated refractory metal film structure using the PVD / CVD method in this embodiment (“development” in FIG. 20) is used, connection resistance can be reduced and connection yield can be secured.

Embodiment 2. FIG.
In the second embodiment, a case where upper layer wiring is formed on a via will be described following the first embodiment.
FIG. 21 is a flowchart showing a main part of the method for manufacturing a semiconductor device in the second embodiment.
In FIG. 21, in this embodiment, when forming an upper layer wiring on the via, as an interlayer insulating film forming step for the upper layer wiring, an SiC film forming step (S502) for forming an SiC film, a porous insulating material p-low k film forming step of forming a p-low k film using (S504), helium plasma processing a p-low k film surface (He) plasma treatment step (S506), the SiO ₂ film formation of forming an SiO ₂ film As a step (S508), an opening forming step (S510) for forming an opening, a pore sealing step (S512) as a diffusion preventing film forming step, an etch back step (S514), and a barrier metal film forming step, First barrier metal film forming step by PVD method (S516), second barrier metal film forming step by CVD method (S518), PVD method A third barrier metal film forming step (S520) and a conductive material depositing step for depositing a conductive material to be an upper layer wiring forming step include a seed film forming step (S522), a plating step (S524), and planarization. A series of steps of step (S526) is performed.

FIG. 22 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 22 shows from the SiC film formation step (S502) to the p-lowk film formation step (S504) in FIG. Subsequent steps will be described later.

  In FIG. 22A, as a SiC film forming step, a 50 nm-thick underlying silicon carbide (SiC) film using SiC is deposited by CVD on a substrate on which a via layer is formed, and an SiC film 286 is formed. Form. Others may be the same as the contents described in FIG.

  In FIG. 22B, as a porous low-k (p-lowk) film forming step, a porous insulating property is formed on the SiC film 286 formed by the SiC insulating film forming step formed on the substrate 200. A p-lowk film 285 using a material is formed with a thickness of 250 nm. By forming the p-lowk film 285, an interlayer insulating film having a relative dielectric constant k lower than 3.5 can be obtained. Others may be the same as those described with reference to FIG.

5B, the surface of the p-lowk film 285 is modified by helium (He) plasma irradiation as a He plasma treatment step. By modifying the surface by He plasma irradiation, the adhesion between the p-lowk film 285 and a CVD-SiO ₂ film 290 as a cap film to be described later formed on the p-lowk film 285 can be improved. .

FIG. 23 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 23 shows from the SiO ₂ film formation step (S508) to the opening formation step (S510) in FIG. Subsequent steps will be described later.

In FIG. 23 (a), the as SiO ₂ film forming step, said after the He plasma treatment, as a cap film, the SiO ₂ by a thickness of 50nm is deposited on the p-low k film 285 by the CVD method, SiO ₂ A film 290 is formed. By forming the SiO ₂ film 290, the p-lowk film 285 that cannot be directly subjected to lithography can be protected, and a pattern can be formed in the p-lowk film 285. Others may be the same as the contents described in FIG.

  In the above description, the interlayer insulating film may not be a low-k film having a relative dielectric constant of 3.5 or less, but is a low-k film, particularly a relative dielectric constant k of 2.5 or less, As described above, it is particularly effective when a porous p-low film having a rate of 30% or more is included.

In FIG. 23B, as an opening forming process, an opening 154 that is a wiring groove structure for producing a damascene wiring is formed in the SiO ₂ film 290 and the p-lowk film 285 by a lithography process and a dry etching process. . An exposed SiO ₂ film 290 and a p-lowk film 285 positioned below the exposed SiO ₂ film 290 with respect to a substrate on which a resist film is formed on the SiO ₂ film 290 through a lithography process such as a resist coating process and an exposure process (not shown). May be removed by anisotropic etching using the underlying SiC film 286 as an etching stopper to form the opening 154. Others may be the same as the contents described in FIG.

FIG. 24 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 24 shows the process from the pore sealing process (S512) to the etch-back process (S514) in FIG. Subsequent steps will be described later.

In FIG. 24A, as a pore sealing process which is an example of the diffusion prevention film forming process, an opening using SiC is formed by CVD on the surface of the opening 150 and the SiO ₂ film 290 formed by the opening forming process. An SiC film is deposited until the film thickness on the partial wall surface reaches 5 nm, and an SiC film 232 is formed. Others may be the same as those described in FIG.

In FIG. 24B, as an etch-back process, the SiC film 232 remaining on the bottom surface of the opening 150 and the SiC film 232 on the SiO ₂ film 290 are removed by etch-back. Then, when the SiC film 232 is removed by etch back, the remaining SiC film 286 formed on the bottom surface of the opening 154 is removed by etch back. By removing the remaining SiC film 286 formed on the bottom surface of the opening 154, the SiC film 286 and the SiC film 232 are not deposited on the bottom surface of the opening 154. It is possible to prevent the conductivity of the layer with the conductive material from being lowered.

FIG. 25 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 25 shows from the first barrier metal film formation step (S516) to the second barrier metal film formation step (S518) in FIG. Subsequent steps will be described later.

In FIG. 25A, as a first barrier metal film forming step, an opening 154 in which an SiC film 232 is formed on the side wall and a barrier metal film 246 using a barrier metal material on the surface of the SiO ₂ film 290 are formed. Using a PVD method, TaN is deposited on the substrate so as to have an average film thickness of 3 nm or less to form a barrier metal film 246. In particular, about 2.5 nm (for example, 2 to 3 nm) is even better. By depositing a barrier metal film 246 of 3 nm or less on the substrate, the film thickness (bottom film thickness) on the Cu film 262 serving as a via (that is, the bottom of the opening 154) is 60 to 70% of the top film thickness. That is, a barrier metal film 246 having a thickness of 1.8 to 2.1 nm is formed at the bottom of the opening 154. Therefore, the film thickness (bottom film thickness) deposited on the bottom of the opening 154 of the barrier metal film 246 is desirably 2.1 nm or less. Others may be the same as those described with reference to FIG.

  In FIG. 25B, as a second barrier metal film forming step, a barrier metal film 247 using a barrier metal material is formed on the first barrier metal film 246. A barrier metal film 247 is formed by depositing TaN on the substrate so that the average film thickness is smaller than 2 nm in the apparatus by using the ALD method or the CVD method including the ALCVD method. In particular, 1 nm (a value of 1 nm or more and less than 2 nm) is more preferable. Others may be the same as those described in FIG.

FIG. 26 is a process sectional view showing a process performed corresponding to the flowchart in FIG. 21.
FIG. 26 shows the third barrier metal film formation step (S520) to the seed film formation step (S522) in FIG. Subsequent steps will be described later.

  In FIG. 26A, as a third barrier metal film forming step, a barrier metal film 248 using a barrier metal material is formed on the second barrier metal film 247. A barrier metal film 248 is formed by depositing TaN on the substrate so as to have an average film thickness of 3 nm or less using the PVD method. In particular, about 2.5 nm (for example, 2 to 3 nm) is even better. By depositing a barrier metal film 248 of 3 nm or less on the substrate, the bottom film thickness (bottom film thickness) of the opening 154 becomes 60 to 70% of the top film thickness, that is, at the bottom of the opening 154 A barrier metal film 248 having a thickness of 1.8 to 2.1 nm is formed. Therefore, the film thickness (bottom film thickness) deposited on the bottom of the opening 154 of the barrier metal film 248 is desirably 2.1 nm or less. Others may be the same as those described in FIG.

  As described above, the sum of the top film thicknesses of the first, second, and third barrier metal films is desirably smaller than 8 nm. Further, in the ALD film, since the change in film thickness at the formation position is small, it is desirable that the bottom film thickness of the second barrier metal film is also smaller than 2 nm, and the bottom film of the first, second, and third barrier metal films. The total thickness is preferably less than 6.2 nm.

  Further, the PVD method is used while reducing the film thickness by forming the second barrier metal film 247 so that the film thickness is thinner than any of the first and third barrier metal films. A controllable and effective PVD film can be formed.

  In the above description, TaN is used as the barrier metal material, but since it is not limited to this, the description is omitted because it is the same as in the first embodiment.

  In FIG. 26B, as a seed film formation process, a barrier metal film 248 is formed by using as a seed film 254 a Cu thin film serving as a cathode electrode in a subsequent electroplating process by physical vapor deposition (PVD) such as sputtering. Are deposited (formed) on the inner wall of the opening 154 and the surface of the substrate. Others may be the same as those described in FIG.

  Here, as described above, the first barrier metal film forming step to the seed film forming step may be either continuous or discontinuous processing (atmospheric exposure).

FIG. 27 is a process sectional view showing a process performed corresponding to the flowchart of FIG. 21.
FIG. 27 shows from the plating step (S524) to the planarization step (S526) in FIG.

  In FIG. 27A, as a plating process, a Cu film 264 is deposited on the opening 154 and the substrate surface by electrochemical growth such as electrolytic plating using the seed film 254 as a cathode electrode, and after the deposition, an annealing process is performed. Others may be the same as the contents described in FIG.

In FIG. 27B, as a planarization step, a Cu film 264, a seed film 254, a barrier metal film 246, and a barrier metal film 247 serving as a via layer as a conductive portion deposited on the surface of the SiO ₂ film 290 by the CMP method. Then, the barrier metal film 248 is removed by polishing to form a buried structure as shown in FIG. Others may be the same as the contents described in FIG.

  As described above, even when the upper wiring is formed on the via, it is possible to reduce the thickness of the barrier metal film by forming a sandwich structure in which the CVD film is sandwiched between PVD films and by defining the film thickness. In addition, the yield between wirings can be maintained with a low resistance even after a long time has elapsed.

Embodiment 3 FIG.
In the first embodiment, a via (hole pattern) is formed on the lower layer wiring (groove pattern), and in the second embodiment, an upper layer wiring (groove pattern) is formed on the via (hole pattern). Although a method is used, it is also effective to use a dual damascene method in which vias (hole patterns) and upper layer wirings (groove patterns) are collectively formed.

  In the above description, as a material for the wiring layer in each of the above embodiments, in addition to Cu, a material mainly composed of Cu used in the semiconductor industry, such as a Cu—Sn alloy, a Cu—Ti alloy, and a Cu—Al alloy. The same effect can be obtained using.

  The present invention is particularly effective when the miniaturization is advanced in the future. For example, it is particularly effective for the generation of 65 to 45 nodes. For example, it is particularly effective for generations with a wiring pitch of 200 nm or less. For example, it is particularly effective for generations with a via diameter of 100 nm or less. For example, this is particularly effective for generations where the relative dielectric constant k of the low dielectric constant film is 2.5 or less. For example, this is particularly effective for generations where the low dielectric constant film has a porous diameter of 2 nm or more. For example, it is particularly effective for generations where the porosity of the low dielectric constant film is 30% or more. For example, for a minimum wiring width of 100 nm, this is particularly effective for generations in which the aspect ratio of the second wiring (upper layer wiring) and the vias located thereunder is 1.5 or more.

  The embodiments have been described above with reference to specific examples. However, the present invention is not limited to these specific examples.

  For example, the film thickness of the interlayer insulating film and the size, shape, number, and the like of the opening can be appropriately selected and used as required in the semiconductor integrated circuit and various semiconductor elements.

  In addition, any semiconductor device manufacturing method that includes the elements of the present invention and whose design can be changed as appropriate by those skilled in the art is included in the scope of the present invention.

  In addition, for the sake of simplicity of explanation, techniques usually used in the semiconductor industry, such as a photolithography process, cleaning before and after processing, are omitted, but it goes without saying that these techniques are included.

3 is a flowchart showing a main part of a method for manufacturing a semiconductor device in the first embodiment. It is a figure which shows the relationship between the via resistance by the difference in the film thickness of the TaN film | membrane by ALD method, and accumulation establishment. It is a figure which shows the relationship between via resistance by the difference in a structure of a barrier metal film, and accumulation establishment. It is a figure which shows the relationship between the via | veer yield of the barrier metal film | membrane made into the sandwich structure, and stress time. It is process sectional drawing showing the process implemented corresponding to the flowchart of FIG. It is process sectional drawing showing the process implemented corresponding to the flowchart of FIG. It is a conceptual diagram of a CVD apparatus. It is process sectional drawing showing the process implemented corresponding to the flowchart of FIG. It is a conceptual diagram of a sputtering device. It is a figure which shows the supply flow of each gas in a TaN film formation process. It is a figure which shows schematic structure of an ALD apparatus. It is a conceptual diagram for demonstrating the outline | summary of the apparatus provided with the several chamber. It is a figure which shows the other schematic structural example of an ALD apparatus. It is process sectional drawing showing the process implemented corresponding to the flowchart of FIG. It is process sectional drawing showing the process implemented corresponding to the flowchart of FIG. It is a schematic diagram for demonstrating the effect of the SiC film 230 formed in this Embodiment. It is a schematic diagram for demonstrating the effect of the SiC film 230 formed in this Embodiment. It is a schematic diagram for demonstrating the effect of the SiC film 230 formed in this Embodiment. It is a figure for demonstrating the adhesiveness of TaN and Cu. It is a figure which shows the relationship between via resistance and accumulation establishment in this Embodiment. 10 is a flowchart showing a main part of a method for manufacturing a semiconductor device in a second embodiment. FIG. 22 is a process cross-sectional view illustrating a process performed corresponding to the flowchart in FIG. 21. FIG. 22 is a process cross-sectional view illustrating a process performed corresponding to the flowchart in FIG. 21. FIG. 22 is a process cross-sectional view illustrating a process performed corresponding to the flowchart in FIG. 21. FIG. 22 is a process cross-sectional view illustrating a process performed corresponding to the flowchart in FIG. 21. FIG. 22 is a process cross-sectional view illustrating a process performed corresponding to the flowchart in FIG. 21. FIG. 22 is a process cross-sectional view illustrating a process performed corresponding to the flowchart in FIG. 21. It is process sectional drawing which shows the manufacturing method of the semiconductor device which has the multilayer wiring structure which combined the conventional low-k film | membrane and Cu wiring. It is a gas supply flow figure which shows the example of film formation of the barrier metal by ALD method. It is a conceptual diagram for demonstrating a TaN film | membrane being formed in ALD method. It is sectional drawing of the semiconductor device which formed the barrier metal film which used the refractory metal by CVD method. It is a figure which shows a mode that Cu has diffused through the barrier metal film | membrane formed 10 nm by PVD method.

Explanation of symbols

10,200 substrate 20 TaR
22 TaN
150, 154 Opening 210 Device layer 212, 230, 232, 275, 286 SiC film 220, 280, 285 p-lowk film 221, 281 Insulating film 222, 284, 290 SiO ₂ film 240, 241, 242, 243, 246 , 247, 248 Barrier metal film 250, 252, 254 Seed film 260, 262, 264 Cu film 300, 510, 520, 530, 600, 700 Chamber 310 Lower electrode 320 Upper electrode 330, 630, 730 Vacuum pump 350, 500 Device 540 Transfer chamber 550 Cassette chamber 610 Substrate holder 620 Shower head 650 Container 720 Target

Claims (10)

An insulating film forming step of forming an insulating film on the substrate;
An opening forming step of forming an opening in the insulating film;
A first barrier metal film forming step of forming a first barrier metal film on the insulating film and in the opening using a physical vapor deposition (PVD) method;
A second barrier metal film forming step of forming a second barrier metal film on the first barrier metal film using a chemical vapor deposition (CVD) method;
A third barrier metal film forming step of forming a third barrier metal film on the second barrier metal film using a PVD method;
A deposition step of depositing a conductive material on the third barrier metal film;
With
A method of manufacturing a semiconductor device, wherein a total film thickness of the first, second and third barrier metal films formed on the insulating film is smaller than 8 nm.   2. The semiconductor according to claim 1, wherein, in the second barrier metal film forming step, the second barrier metal film formed on the insulating film is formed to have a thickness of less than 2 nm. Device manufacturing method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the film thickness of the second barrier metal film is formed so as to be thinner than any film thickness of the first and third barrier metal films. .   The first, second, and third barrier metal films were made of tantalum (Ta), titanium (Ti), tungsten (W), Ta compound, Ti compound, and W compound, respectively. The method of manufacturing a semiconductor device according to claim 1.   2. The method of forming a semiconductor device according to claim 1, further comprising a diffusion prevention film forming step of forming a diffusion prevention film on a wall surface of the opening before the first barrier metal film formation step. The manufacturing method of the semiconductor device of description.   6. The method of manufacturing a semiconductor device according to claim 5, wherein, in the diffusion preventing film forming step, the diffusion preventing film is formed to have a thickness of 20 nm or less.   6. The method of manufacturing a semiconductor device according to claim 5, wherein a silicon compound is used as a material of the diffusion preventing film in the diffusion preventing film forming step.   8. The silicon compound according to claim 7, wherein at least one of silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbonate (SiOC), and silicon nitride (SiN) is used as the silicon compound. A method for manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a low dielectric constant film having a relative dielectric constant of 2.5 or less. A first conductive film using a conductive material;
A second conductive film using the conductive material formed on the first conductive film;
An insulating film using an insulating material, disposed on a side surface of the second conductive film;
Using a barrier metal material, a chemical vapor deposition (CVD) method formed between the second conductive film and the insulating film and between the first and second conductive films is used. A barrier metal film having a formed CVD film and two PVD films formed to sandwich the CVD film using a physical vapor deposition (PVD) method;
With
The barrier metal film is formed between the first conductive film and the second conductive film so that a total film thickness of the CVD film and the two PVD films is smaller than 6.2 nm. .